1/* 2 * linux/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c 3 * 4 * Toshiba RBTX4927 specific interrupt handlers 5 * 6 * Author: MontaVista Software, Inc. 7 * source@mvista.com 8 * 9 * Copyright 2001-2002 MontaVista Software Inc. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 22 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 24 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 25 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * You should have received a copy of the GNU General Public License along 28 * with this program; if not, write to the Free Software Foundation, Inc., 29 * 675 Mass Ave, Cambridge, MA 02139, USA. 30 */ 31 32 33/* 34IRQ Device 3500 RBTX4927-ISA/00 3601 RBTX4927-ISA/01 PS2/Keyboard 3702 RBTX4927-ISA/02 Cascade RBTX4927-ISA (irqs 8-15) 3803 RBTX4927-ISA/03 3904 RBTX4927-ISA/04 4005 RBTX4927-ISA/05 4106 RBTX4927-ISA/06 4207 RBTX4927-ISA/07 4308 RBTX4927-ISA/08 4409 RBTX4927-ISA/09 4510 RBTX4927-ISA/10 4611 RBTX4927-ISA/11 4712 RBTX4927-ISA/12 PS2/Mouse (not supported at this time) 4813 RBTX4927-ISA/13 4914 RBTX4927-ISA/14 IDE 5015 RBTX4927-ISA/15 51 5216 TX4927-CP0/00 Software 0 5317 TX4927-CP0/01 Software 1 5418 TX4927-CP0/02 Cascade TX4927-CP0 5519 TX4927-CP0/03 Multiplexed -- do not use 5620 TX4927-CP0/04 Multiplexed -- do not use 5721 TX4927-CP0/05 Multiplexed -- do not use 5822 TX4927-CP0/06 Multiplexed -- do not use 5923 TX4927-CP0/07 CPU TIMER 60 6124 TX4927-PIC/00 6225 TX4927-PIC/01 6326 TX4927-PIC/02 6427 TX4927-PIC/03 Cascade RBTX4927-IOC 6528 TX4927-PIC/04 6629 TX4927-PIC/05 RBTX4927 RTL-8019AS ethernet 6730 TX4927-PIC/06 6831 TX4927-PIC/07 6932 TX4927-PIC/08 TX4927 SerialIO Channel 0 7033 TX4927-PIC/09 TX4927 SerialIO Channel 1 7134 TX4927-PIC/10 7235 TX4927-PIC/11 7336 TX4927-PIC/12 7437 TX4927-PIC/13 7538 TX4927-PIC/14 7639 TX4927-PIC/15 7740 TX4927-PIC/16 TX4927 PCI PCI-C 7841 TX4927-PIC/17 7942 TX4927-PIC/18 8043 TX4927-PIC/19 8144 TX4927-PIC/20 8245 TX4927-PIC/21 8346 TX4927-PIC/22 TX4927 PCI PCI-ERR 8447 TX4927-PIC/23 TX4927 PCI PCI-PMA (not used) 8548 TX4927-PIC/24 8649 TX4927-PIC/25 8750 TX4927-PIC/26 8851 TX4927-PIC/27 8952 TX4927-PIC/28 9053 TX4927-PIC/29 9154 TX4927-PIC/30 9255 TX4927-PIC/31 93 9456 RBTX4927-IOC/00 FPCIB0 PCI-D PJ4/A PJ5/B SB/C PJ6/D PJ7/A (SouthBridge/NotUsed) [RTL-8139=PJ4] 9557 RBTX4927-IOC/01 FPCIB0 PCI-C PJ4/D PJ5/A SB/B PJ6/C PJ7/D (SouthBridge/NotUsed) [RTL-8139=PJ5] 9658 RBTX4927-IOC/02 FPCIB0 PCI-B PJ4/C PJ5/D SB/A PJ6/B PJ7/C (SouthBridge/IDE/pin=1,INTR) [RTL-8139=NotSupported] 9759 RBTX4927-IOC/03 FPCIB0 PCI-A PJ4/B PJ5/C SB/D PJ6/A PJ7/B (SouthBridge/USB/pin=4) [RTL-8139=PJ6] 9860 RBTX4927-IOC/04 9961 RBTX4927-IOC/05 10062 RBTX4927-IOC/06 10163 RBTX4927-IOC/07 102 103NOTES: 104SouthBridge/INTR is mapped to SouthBridge/A=PCI-B/#58 105SouthBridge/ISA/pin=0 no pci irq used by this device 106SouthBridge/IDE/pin=1 no pci irq used by this device, using INTR via ISA IRQ14 107SouthBridge/USB/pin=4 using pci irq SouthBridge/D=PCI-A=#59 108SouthBridge/PMC/pin=0 no pci irq used by this device 109SuperIO/PS2/Keyboard, using INTR via ISA IRQ1 110SuperIO/PS2/Mouse, using INTR via ISA IRQ12 (mouse not currently supported) 111JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthBridge, JP4, JP5, JP6 112*/ 113 114#include <linux/init.h> 115#include <linux/kernel.h> 116#include <linux/types.h> 117#include <linux/mm.h> 118#include <linux/swap.h> 119#include <linux/ioport.h> 120#include <linux/sched.h> 121#include <linux/interrupt.h> 122#include <linux/pci.h> 123#include <linux/timex.h> 124#include <asm/bootinfo.h> 125#include <asm/page.h> 126#include <asm/io.h> 127#include <asm/irq.h> 128#include <asm/pci.h> 129#include <asm/processor.h> 130#include <asm/reboot.h> 131#include <asm/time.h> 132#include <asm/wbflush.h> 133#include <linux/bootmem.h> 134#include <linux/blkdev.h> 135#ifdef CONFIG_TOSHIBA_FPCIB0 136#include <asm/tx4927/smsc_fdc37m81x.h> 137#endif 138#include <asm/tx4927/toshiba_rbtx4927.h> 139 140 141#undef TOSHIBA_RBTX4927_IRQ_DEBUG 142 143#ifdef TOSHIBA_RBTX4927_IRQ_DEBUG 144#define TOSHIBA_RBTX4927_IRQ_NONE 0x00000000 145 146#define TOSHIBA_RBTX4927_IRQ_INFO ( 1 << 0 ) 147#define TOSHIBA_RBTX4927_IRQ_WARN ( 1 << 1 ) 148#define TOSHIBA_RBTX4927_IRQ_EROR ( 1 << 2 ) 149 150#define TOSHIBA_RBTX4927_IRQ_IOC_INIT ( 1 << 10 ) 151#define TOSHIBA_RBTX4927_IRQ_IOC_ENABLE ( 1 << 13 ) 152#define TOSHIBA_RBTX4927_IRQ_IOC_DISABLE ( 1 << 14 ) 153 154#define TOSHIBA_RBTX4927_IRQ_ISA_INIT ( 1 << 20 ) 155#define TOSHIBA_RBTX4927_IRQ_ISA_ENABLE ( 1 << 23 ) 156#define TOSHIBA_RBTX4927_IRQ_ISA_DISABLE ( 1 << 24 ) 157#define TOSHIBA_RBTX4927_IRQ_ISA_MASK ( 1 << 25 ) 158 159#define TOSHIBA_RBTX4927_SETUP_ALL 0xffffffff 160#endif 161 162 163#ifdef TOSHIBA_RBTX4927_IRQ_DEBUG 164static const u32 toshiba_rbtx4927_irq_debug_flag = 165 (TOSHIBA_RBTX4927_IRQ_NONE | TOSHIBA_RBTX4927_IRQ_INFO | 166 TOSHIBA_RBTX4927_IRQ_WARN | TOSHIBA_RBTX4927_IRQ_EROR 167// | TOSHIBA_RBTX4927_IRQ_IOC_INIT 168// | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE 169// | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE 170// | TOSHIBA_RBTX4927_IRQ_ISA_INIT 171// | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE 172// | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE 173// | TOSHIBA_RBTX4927_IRQ_ISA_MASK 174 ); 175#endif 176 177 178#ifdef TOSHIBA_RBTX4927_IRQ_DEBUG 179#define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag,str...) \ 180 if ( (toshiba_rbtx4927_irq_debug_flag) & (flag) ) \ 181 { \ 182 char tmp[100]; \ 183 sprintf( tmp, str ); \ 184 printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \ 185 } 186#else 187#define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag,str...) 188#endif 189 190 191 192 193#define TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG 0 194#define TOSHIBA_RBTX4927_IRQ_IOC_RAW_END 7 195 196#define TOSHIBA_RBTX4927_IRQ_IOC_BEG ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG) /* 56 */ 197#define TOSHIBA_RBTX4927_IRQ_IOC_END ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_END) /* 63 */ 198 199 200#define TOSHIBA_RBTX4927_IRQ_ISA_BEG MI8259_IRQ_ISA_BEG 201#define TOSHIBA_RBTX4927_IRQ_ISA_END MI8259_IRQ_ISA_END 202#define TOSHIBA_RBTX4927_IRQ_ISA_MID ((TOSHIBA_RBTX4927_IRQ_ISA_BEG+TOSHIBA_RBTX4927_IRQ_ISA_END+1)/2) 203 204 205#define TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC TX4927_IRQ_NEST_EXT_ON_PIC 206#define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC (TOSHIBA_RBTX4927_IRQ_IOC_BEG+2) 207#define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA (TOSHIBA_RBTX4927_IRQ_ISA_BEG+2) 208 209extern int tx4927_using_backplane; 210 211#ifdef CONFIG_TOSHIBA_FPCIB0 212extern void enable_8259A_irq(unsigned int irq); 213extern void disable_8259A_irq(unsigned int irq); 214extern void mask_and_ack_8259A(unsigned int irq); 215#endif 216 217static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq); 218static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq); 219 220#ifdef CONFIG_TOSHIBA_FPCIB0 221static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq); 222static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq); 223static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq); 224#endif 225 226#define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC" 227static struct irq_chip toshiba_rbtx4927_irq_ioc_type = { 228 .name = TOSHIBA_RBTX4927_IOC_NAME, 229 .ack = toshiba_rbtx4927_irq_ioc_disable, 230 .mask = toshiba_rbtx4927_irq_ioc_disable, 231 .mask_ack = toshiba_rbtx4927_irq_ioc_disable, 232 .unmask = toshiba_rbtx4927_irq_ioc_enable, 233}; 234#define TOSHIBA_RBTX4927_IOC_INTR_ENAB 0xbc002000 235#define TOSHIBA_RBTX4927_IOC_INTR_STAT 0xbc002006 236 237 238#ifdef CONFIG_TOSHIBA_FPCIB0 239#define TOSHIBA_RBTX4927_ISA_NAME "RBTX4927-ISA" 240static struct irq_chip toshiba_rbtx4927_irq_isa_type = { 241 .name = TOSHIBA_RBTX4927_ISA_NAME, 242 .ack = toshiba_rbtx4927_irq_isa_mask_and_ack, 243 .mask = toshiba_rbtx4927_irq_isa_disable, 244 .mask_ack = toshiba_rbtx4927_irq_isa_mask_and_ack, 245 .unmask = toshiba_rbtx4927_irq_isa_enable, 246}; 247#endif 248 249 250u32 bit2num(u32 num) 251{ 252 u32 i; 253 254 for (i = 0; i < (sizeof(num) * 8); i++) { 255 if (num & (1 << i)) { 256 return (i); 257 } 258 } 259 return (0); 260} 261 262int toshiba_rbtx4927_irq_nested(int sw_irq) 263{ 264 u32 level3; 265 u32 level4; 266 u32 level5; 267 268 level3 = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; 269 if (level3) { 270 sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + bit2num(level3); 271 if (sw_irq != TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC) { 272 goto RETURN; 273 } 274 } 275#ifdef CONFIG_TOSHIBA_FPCIB0 276 { 277 if (tx4927_using_backplane) { 278 outb(0x0A, 0x20); 279 level4 = inb(0x20) & 0xff; 280 if (level4) { 281 sw_irq = 282 TOSHIBA_RBTX4927_IRQ_ISA_BEG + 283 bit2num(level4); 284 if (sw_irq != 285 TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA) { 286 goto RETURN; 287 } 288 } 289 290 outb(0x0A, 0xA0); 291 level5 = inb(0xA0) & 0xff; 292 if (level5) { 293 sw_irq = 294 TOSHIBA_RBTX4927_IRQ_ISA_MID + 295 bit2num(level5); 296 goto RETURN; 297 } 298 } 299 } 300#endif 301 302 RETURN: 303 return (sw_irq); 304} 305 306//#define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, 0, CPU_MASK_NONE, s, NULL, NULL } 307#define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, IRQF_SHARED, CPU_MASK_NONE, s, NULL, NULL } 308static struct irqaction toshiba_rbtx4927_irq_ioc_action = 309TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_IOC_NAME); 310#ifdef CONFIG_TOSHIBA_FPCIB0 311static struct irqaction toshiba_rbtx4927_irq_isa_master = 312TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_ISA_NAME "/M"); 313static struct irqaction toshiba_rbtx4927_irq_isa_slave = 314TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_ISA_NAME "/S"); 315#endif 316 317 318/**********************************************************************************/ 319/* Functions for ioc */ 320/**********************************************************************************/ 321 322 323static void __init toshiba_rbtx4927_irq_ioc_init(void) 324{ 325 int i; 326 327 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_INIT, 328 "beg=%d end=%d\n", 329 TOSHIBA_RBTX4927_IRQ_IOC_BEG, 330 TOSHIBA_RBTX4927_IRQ_IOC_END); 331 332 for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG; 333 i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++) 334 set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type, 335 handle_level_irq); 336 337 setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC, 338 &toshiba_rbtx4927_irq_ioc_action); 339} 340 341static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq) 342{ 343 volatile unsigned char v; 344 345 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENABLE, 346 "irq=%d\n", irq); 347 348 if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG 349 || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) { 350 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR, 351 "bad irq=%d\n", irq); 352 panic("\n"); 353 } 354 355 v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB); 356 v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); 357 TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v); 358} 359 360 361static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq) 362{ 363 volatile unsigned char v; 364 365 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_DISABLE, 366 "irq=%d\n", irq); 367 368 if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG 369 || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) { 370 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR, 371 "bad irq=%d\n", irq); 372 panic("\n"); 373 } 374 375 v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB); 376 v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); 377 TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v); 378} 379 380 381/**********************************************************************************/ 382/* Functions for isa */ 383/**********************************************************************************/ 384 385 386#ifdef CONFIG_TOSHIBA_FPCIB0 387static void __init toshiba_rbtx4927_irq_isa_init(void) 388{ 389 int i; 390 391 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_INIT, 392 "beg=%d end=%d\n", 393 TOSHIBA_RBTX4927_IRQ_ISA_BEG, 394 TOSHIBA_RBTX4927_IRQ_ISA_END); 395 396 for (i = TOSHIBA_RBTX4927_IRQ_ISA_BEG; 397 i <= TOSHIBA_RBTX4927_IRQ_ISA_END; i++) 398 set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_isa_type, 399 handle_level_irq); 400 401 setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC, 402 &toshiba_rbtx4927_irq_isa_master); 403 setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA, 404 &toshiba_rbtx4927_irq_isa_slave); 405 406 /* make sure we are looking at IRR (not ISR) */ 407 outb(0x0A, 0x20); 408 outb(0x0A, 0xA0); 409} 410#endif 411 412 413#ifdef CONFIG_TOSHIBA_FPCIB0 414static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq) 415{ 416 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_ENABLE, 417 "irq=%d\n", irq); 418 419 if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG 420 || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) { 421 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR, 422 "bad irq=%d\n", irq); 423 panic("\n"); 424 } 425 426 enable_8259A_irq(irq); 427} 428#endif 429 430 431#ifdef CONFIG_TOSHIBA_FPCIB0 432static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq) 433{ 434 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_DISABLE, 435 "irq=%d\n", irq); 436 437 if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG 438 || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) { 439 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR, 440 "bad irq=%d\n", irq); 441 panic("\n"); 442 } 443 444 disable_8259A_irq(irq); 445} 446#endif 447 448 449#ifdef CONFIG_TOSHIBA_FPCIB0 450static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq) 451{ 452 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_MASK, 453 "irq=%d\n", irq); 454 455 if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG 456 || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) { 457 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR, 458 "bad irq=%d\n", irq); 459 panic("\n"); 460 } 461 462 mask_and_ack_8259A(irq); 463} 464#endif 465 466 467void __init arch_init_irq(void) 468{ 469 extern void tx4927_irq_init(void); 470 471 tx4927_irq_init(); 472 toshiba_rbtx4927_irq_ioc_init(); 473#ifdef CONFIG_TOSHIBA_FPCIB0 474 { 475 if (tx4927_using_backplane) { 476 toshiba_rbtx4927_irq_isa_init(); 477 } 478 } 479#endif 480 481 wbflush(); 482} 483 484void toshiba_rbtx4927_irq_dump(char *key) 485{ 486#ifdef TOSHIBA_RBTX4927_IRQ_DEBUG 487 { 488 u32 i, j = 0; 489 for (i = 0; i < NR_IRQS; i++) { 490 if (strcmp(irq_desc[i].chip->name, "none") 491 == 0) 492 continue; 493 494 if ((i >= 1) 495 && (irq_desc[i - 1].chip->name == 496 irq_desc[i].chip->name)) { 497 j++; 498 } else { 499 j = 0; 500 } 501 TOSHIBA_RBTX4927_IRQ_DPRINTK 502 (TOSHIBA_RBTX4927_IRQ_INFO, 503 "%s irq=0x%02x/%3d s=0x%08x h=0x%08x a=0x%08x ah=0x%08x d=%1d n=%s/%02d\n", 504 key, i, i, irq_desc[i].status, 505 (u32) irq_desc[i].chip, 506 (u32) irq_desc[i].action, 507 (u32) (irq_desc[i].action ? irq_desc[i]. 508 action->handler : 0), 509 irq_desc[i].depth, 510 irq_desc[i].chip->name, j); 511 } 512 } 513#endif 514} 515 516void toshiba_rbtx4927_irq_dump_pics(char *s) 517{ 518 u32 level0_m; 519 u32 level0_s; 520 u32 level1_m; 521 u32 level1_s; 522 u32 level2; 523 u32 level2_p; 524 u32 level2_s; 525 u32 level3_m; 526 u32 level3_s; 527 u32 level4_m; 528 u32 level4_s; 529 u32 level5_m; 530 u32 level5_s; 531 532 if (s == NULL) 533 s = "null"; 534 535 level0_m = (read_c0_status() & 0x0000ff00) >> 8; 536 level0_s = (read_c0_cause() & 0x0000ff00) >> 8; 537 538 level1_m = level0_m; 539 level1_s = level0_s & 0x87; 540 541 level2 = TX4927_RD(0xff1ff6a0); 542 level2_p = (((level2 & 0x10000)) ? 0 : 1); 543 level2_s = (((level2 & 0x1f) == 0x1f) ? 0 : (level2 & 0x1f)); 544 545 level3_m = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_ENAB) & 0x1f; 546 level3_s = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; 547 548 level4_m = inb(0x21); 549 outb(0x0A, 0x20); 550 level4_s = inb(0x20); 551 552 level5_m = inb(0xa1); 553 outb(0x0A, 0xa0); 554 level5_s = inb(0xa0); 555 556 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, 557 "dump_raw_pic() "); 558 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, 559 "cp0:m=0x%02x/s=0x%02x ", level0_m, 560 level0_s); 561 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, 562 "cp0:m=0x%02x/s=0x%02x ", level1_m, 563 level1_s); 564 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, 565 "pic:e=0x%02x/s=0x%02x ", level2_p, 566 level2_s); 567 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, 568 "ioc:m=0x%02x/s=0x%02x ", level3_m, 569 level3_s); 570 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, 571 "sbm:m=0x%02x/s=0x%02x ", level4_m, 572 level4_s); 573 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, 574 "sbs:m=0x%02x/s=0x%02x ", level5_m, 575 level5_s); 576 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, "[%s]\n", 577 s); 578} 579