1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994, 1995 Waldorf Electronics 7 * Written by Ralf Baechle and Andreas Busse 8 * Copyright (C) 1994 - 99, 2003, 06 Ralf Baechle 9 * Copyright (C) 1996 Paul M. Antoine 10 * Modified for DECStation and hence R3000 support by Paul M. Antoine 11 * Further modifications by David S. Miller and Harald Koerfgen 12 * Copyright (C) 1999 Silicon Graphics, Inc. 13 * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 14 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 15 */ 16#include <linux/init.h> 17#include <linux/threads.h> 18 19#include <asm/asm.h> 20#include <asm/asmmacro.h> 21#include <asm/irqflags.h> 22#include <asm/regdef.h> 23#include <asm/page.h> 24#include <asm/mipsregs.h> 25#include <asm/stackframe.h> 26 27#include <kernel-entry-init.h> 28 29 .macro ARC64_TWIDDLE_PC 30#if defined(CONFIG_ARC64) || defined(CONFIG_MAPPED_KERNEL) 31 /* We get launched at a XKPHYS address but the kernel is linked to 32 run at a KSEG0 address, so jump there. */ 33 PTR_LA t0, \@f 34 jr t0 35\@: 36#endif 37 .endm 38 39 /* 40 * inputs are the text nasid in t1, data nasid in t2. 41 */ 42 .macro MAPPED_KERNEL_SETUP_TLB 43#ifdef CONFIG_MAPPED_KERNEL 44 /* 45 * This needs to read the nasid - assume 0 for now. 46 * Drop in 0xffffffffc0000000 in tlbhi, 0+VG in tlblo_0, 47 * 0+DVG in tlblo_1. 48 */ 49 dli t0, 0xffffffffc0000000 50 dmtc0 t0, CP0_ENTRYHI 51 li t0, 0x1c000 # Offset of text into node memory 52 dsll t1, NASID_SHFT # Shift text nasid into place 53 dsll t2, NASID_SHFT # Same for data nasid 54 or t1, t1, t0 # Physical load address of kernel text 55 or t2, t2, t0 # Physical load address of kernel data 56 dsrl t1, 12 # 4K pfn 57 dsrl t2, 12 # 4K pfn 58 dsll t1, 6 # Get pfn into place 59 dsll t2, 6 # Get pfn into place 60 li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _CACHE_CACHABLE_COW) >> 6) 61 or t0, t0, t1 62 mtc0 t0, CP0_ENTRYLO0 # physaddr, VG, cach exlwr 63 li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _PAGE_DIRTY|_CACHE_CACHABLE_COW) >> 6) 64 or t0, t0, t2 65 mtc0 t0, CP0_ENTRYLO1 # physaddr, DVG, cach exlwr 66 li t0, 0x1ffe000 # MAPPED_KERN_TLBMASK, TLBPGMASK_16M 67 mtc0 t0, CP0_PAGEMASK 68 li t0, 0 # KMAP_INX 69 mtc0 t0, CP0_INDEX 70 li t0, 1 71 mtc0 t0, CP0_WIRED 72 tlbwi 73#else 74 mtc0 zero, CP0_WIRED 75#endif 76 .endm 77 78 /* 79 * For the moment disable interrupts, mark the kernel mode and 80 * set ST0_KX so that the CPU does not spit fire when using 81 * 64-bit addresses. A full initialization of the CPU's status 82 * register is done later in per_cpu_trap_init(). 83 */ 84 .macro setup_c0_status set clr 85 .set push 86#ifdef CONFIG_MIPS_MT_SMTC 87 /* 88 * For SMTC, we need to set privilege and disable interrupts only for 89 * the current TC, using the TCStatus register. 90 */ 91 mfc0 t0, CP0_TCSTATUS 92 /* Fortunately CU 0 is in the same place in both registers */ 93 /* Set TCU0, TMX, TKSU (for later inversion) and IXMT */ 94 li t1, ST0_CU0 | 0x08001c00 95 or t0, t1 96 /* Clear TKSU, leave IXMT */ 97 xori t0, 0x00001800 98 mtc0 t0, CP0_TCSTATUS 99 _ehb 100 /* We need to leave the global IE bit set, but clear EXL...*/ 101 mfc0 t0, CP0_STATUS 102 or t0, ST0_CU0 | ST0_EXL | ST0_ERL | \set | \clr 103 xor t0, ST0_EXL | ST0_ERL | \clr 104 mtc0 t0, CP0_STATUS 105#else 106 mfc0 t0, CP0_STATUS 107 or t0, ST0_CU0|\set|0x1f|\clr 108 xor t0, 0x1f|\clr 109 mtc0 t0, CP0_STATUS 110 .set noreorder 111 sll zero,3 # ehb 112#endif 113 .set pop 114 .endm 115 116 .macro setup_c0_status_pri 117#ifdef CONFIG_64BIT 118 setup_c0_status ST0_KX 0 119#else 120 setup_c0_status 0 0 121#endif 122 .endm 123 124 .macro setup_c0_status_sec 125#ifdef CONFIG_64BIT 126 setup_c0_status ST0_KX ST0_BEV 127#else 128 setup_c0_status 0 ST0_BEV 129#endif 130 .endm 131 132#ifdef CONFIG_BCM47XX 133#undef eret 134#define eret nop; nop; eret 135#endif 136 137 j kernel_entry 138 nop 139 140 /* 141 * Reserved space for exception handlers. 142 * Necessary for machines which link their kernels at KSEG0. 143 */ 144 .fill 0x3f4 145 146EXPORT(stext) # used for profiling 147EXPORT(_stext) 148 149#ifdef CONFIG_MIPS_SIM 150 /* 151 * Give us a fighting chance of running if execution beings at the 152 * kernel load address. This is needed because this platform does 153 * not have a ELF loader yet. 154 */ 155 j kernel_entry 156#endif 157 __INIT 158 159NESTED(kernel_entry, 16, sp) # kernel entry point 160 161 kernel_entry_setup # cpu specific setup 162 163 setup_c0_status_pri 164 165 ARC64_TWIDDLE_PC 166 167#ifdef CONFIG_MIPS_MT_SMTC 168 /* 169 * In SMTC kernel, "CLI" is thread-specific, in TCStatus. 170 * We still need to enable interrupts globally in Status, 171 * and clear EXL/ERL. 172 * 173 * TCContext is used to track interrupt levels under 174 * service in SMTC kernel. Clear for boot TC before 175 * allowing any interrupts. 176 */ 177 mtc0 zero, CP0_TCCONTEXT 178 179 mfc0 t0, CP0_STATUS 180 ori t0, t0, 0xff1f 181 xori t0, t0, 0x001e 182 mtc0 t0, CP0_STATUS 183#endif /* CONFIG_MIPS_MT_SMTC */ 184 185#if !defined(CONFIG_HWSIM) || defined(CONFIG_HWSIM_ZMEM) 186 PTR_LA t0, __bss_start # clear .bss 187 LONG_S zero, (t0) 188 PTR_LA t1, __bss_stop - LONGSIZE 1891: 190 PTR_ADDIU t0, LONGSIZE 191 LONG_S zero, (t0) 192 bne t0, t1, 1b 193#endif 194 195 LONG_S a0, fw_arg0 # firmware arguments 196 LONG_S a1, fw_arg1 197 LONG_S a2, fw_arg2 198 LONG_S a3, fw_arg3 199 200 MTC0 zero, CP0_CONTEXT # clear context register 201 PTR_LA $28, init_thread_union 202 PTR_LI sp, _THREAD_SIZE - 32 203 PTR_ADDU sp, $28 204 set_saved_sp sp, t0, t1 205 PTR_SUBU sp, 4 * SZREG # init stack pointer 206 207 j start_kernel 208 END(kernel_entry) 209 210#ifdef CONFIG_QEMU 211 __INIT 212#endif 213 214#ifdef CONFIG_SMP 215/* 216 * SMP slave cpus entry point. Board specific code for bootstrap calls this 217 * function after setting up the stack and gp registers. 218 */ 219NESTED(smp_bootstrap, 16, sp) 220#ifdef CONFIG_MIPS_MT_SMTC 221 /* 222 * Read-modify-writes of Status must be atomic, and this 223 * is one case where CLI is invoked without EXL being 224 * necessarily set. The CLI and setup_c0_status will 225 * in fact be redundant for all but the first TC of 226 * each VPE being booted. 227 */ 228 DMT 10 # dmt t2 /* t0, t1 are used by CLI and setup_c0_status() */ 229 jal mips_ihb 230#endif /* CONFIG_MIPS_MT_SMTC */ 231 setup_c0_status_sec 232 smp_slave_setup 233#ifdef CONFIG_MIPS_MT_SMTC 234 andi t2, t2, VPECONTROL_TE 235 beqz t2, 2f 236 EMT # emt 2372: 238#endif /* CONFIG_MIPS_MT_SMTC */ 239 j start_secondary 240 END(smp_bootstrap) 241#endif /* CONFIG_SMP */ 242 243 __FINIT 244