1/* 2 * System-specific setup, especially interrupts. 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 1998 Harald Koerfgen 9 * Copyright (C) 2000, 2001, 2002, 2003, 2005 Maciej W. Rozycki 10 */ 11#include <linux/console.h> 12#include <linux/init.h> 13#include <linux/interrupt.h> 14#include <linux/ioport.h> 15#include <linux/module.h> 16#include <linux/param.h> 17#include <linux/sched.h> 18#include <linux/spinlock.h> 19#include <linux/types.h> 20#include <linux/pm.h> 21 22#include <asm/bootinfo.h> 23#include <asm/cpu.h> 24#include <asm/cpu-features.h> 25#include <asm/irq.h> 26#include <asm/irq_cpu.h> 27#include <asm/mipsregs.h> 28#include <asm/reboot.h> 29#include <asm/time.h> 30#include <asm/traps.h> 31#include <asm/wbflush.h> 32 33#include <asm/dec/interrupts.h> 34#include <asm/dec/ioasic.h> 35#include <asm/dec/ioasic_addrs.h> 36#include <asm/dec/ioasic_ints.h> 37#include <asm/dec/kn01.h> 38#include <asm/dec/kn02.h> 39#include <asm/dec/kn02ba.h> 40#include <asm/dec/kn02ca.h> 41#include <asm/dec/kn03.h> 42#include <asm/dec/kn230.h> 43#include <asm/dec/system.h> 44 45 46extern void dec_machine_restart(char *command); 47extern void dec_machine_halt(void); 48extern void dec_machine_power_off(void); 49extern irqreturn_t dec_intr_halt(int irq, void *dev_id); 50 51unsigned long dec_kn_slot_base, dec_kn_slot_size; 52 53EXPORT_SYMBOL(dec_kn_slot_base); 54EXPORT_SYMBOL(dec_kn_slot_size); 55 56int dec_tc_bus; 57 58spinlock_t ioasic_ssr_lock; 59 60volatile u32 *ioasic_base; 61 62EXPORT_SYMBOL(ioasic_base); 63 64/* 65 * IRQ routing and priority tables. Priorites are set as follows: 66 * 67 * KN01 KN230 KN02 KN02-BA KN02-CA KN03 68 * 69 * MEMORY CPU CPU CPU ASIC CPU CPU 70 * RTC CPU CPU CPU ASIC CPU CPU 71 * DMA - - - ASIC ASIC ASIC 72 * SERIAL0 CPU CPU CSR ASIC ASIC ASIC 73 * SERIAL1 - - - ASIC - ASIC 74 * SCSI CPU CPU CSR ASIC ASIC ASIC 75 * ETHERNET CPU * CSR ASIC ASIC ASIC 76 * other - - - ASIC - - 77 * TC2 - - CSR CPU ASIC ASIC 78 * TC1 - - CSR CPU ASIC ASIC 79 * TC0 - - CSR CPU ASIC ASIC 80 * other - CPU - CPU ASIC ASIC 81 * other - - - - CPU CPU 82 * 83 * * -- shared with SCSI 84 */ 85 86int dec_interrupt[DEC_NR_INTS] = { 87 [0 ... DEC_NR_INTS - 1] = -1 88}; 89 90EXPORT_SYMBOL(dec_interrupt); 91 92int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2] = { 93 { { .i = ~0 }, { .p = dec_intr_unimplemented } }, 94}; 95int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2] = { 96 { { .i = ~0 }, { .p = asic_intr_unimplemented } }, 97}; 98int cpu_fpu_mask = DEC_CPU_IRQ_MASK(DEC_CPU_INR_FPU); 99 100static struct irqaction ioirq = { 101 .handler = no_action, 102 .name = "cascade", 103}; 104static struct irqaction fpuirq = { 105 .handler = no_action, 106 .name = "fpu", 107}; 108 109static struct irqaction busirq = { 110 .flags = IRQF_DISABLED, 111 .name = "bus error", 112}; 113 114static struct irqaction haltirq = { 115 .handler = dec_intr_halt, 116 .name = "halt", 117}; 118 119 120/* 121 * Bus error (DBE/IBE exceptions and bus interrupts) handling setup. 122 */ 123static void __init dec_be_init(void) 124{ 125 switch (mips_machtype) { 126 case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */ 127 board_be_handler = dec_kn01_be_handler; 128 busirq.handler = dec_kn01_be_interrupt; 129 busirq.flags |= IRQF_SHARED; 130 dec_kn01_be_init(); 131 break; 132 case MACH_DS5000_1XX: /* DS5000/1xx 3min */ 133 case MACH_DS5000_XX: /* DS5000/xx Maxine */ 134 board_be_handler = dec_kn02xa_be_handler; 135 busirq.handler = dec_kn02xa_be_interrupt; 136 dec_kn02xa_be_init(); 137 break; 138 case MACH_DS5000_200: /* DS5000/200 3max */ 139 case MACH_DS5000_2X0: /* DS5000/240 3max+ */ 140 case MACH_DS5900: /* DS5900 bigmax */ 141 board_be_handler = dec_ecc_be_handler; 142 busirq.handler = dec_ecc_be_interrupt; 143 dec_ecc_be_init(); 144 break; 145 } 146} 147 148 149extern void dec_time_init(void); 150 151void __init plat_mem_setup(void) 152{ 153 board_be_init = dec_be_init; 154 board_time_init = dec_time_init; 155 156 wbflush_setup(); 157 158 _machine_restart = dec_machine_restart; 159 _machine_halt = dec_machine_halt; 160 pm_power_off = dec_machine_power_off; 161 162 ioport_resource.start = ~0UL; 163 ioport_resource.end = 0UL; 164} 165 166/* 167 * Machine-specific initialisation for KN01, aka DS2100 (aka Pmin) 168 * or DS3100 (aka Pmax). 169 */ 170static int kn01_interrupt[DEC_NR_INTS] __initdata = { 171 [DEC_IRQ_CASCADE] = -1, 172 [DEC_IRQ_AB_RECV] = -1, 173 [DEC_IRQ_AB_XMIT] = -1, 174 [DEC_IRQ_DZ11] = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11), 175 [DEC_IRQ_ASC] = -1, 176 [DEC_IRQ_FLOPPY] = -1, 177 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), 178 [DEC_IRQ_HALT] = -1, 179 [DEC_IRQ_ISDN] = -1, 180 [DEC_IRQ_LANCE] = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE), 181 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS), 182 [DEC_IRQ_PSU] = -1, 183 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC), 184 [DEC_IRQ_SCC0] = -1, 185 [DEC_IRQ_SCC1] = -1, 186 [DEC_IRQ_SII] = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII), 187 [DEC_IRQ_TC0] = -1, 188 [DEC_IRQ_TC1] = -1, 189 [DEC_IRQ_TC2] = -1, 190 [DEC_IRQ_TIMER] = -1, 191 [DEC_IRQ_VIDEO] = DEC_CPU_IRQ_NR(KN01_CPU_INR_VIDEO), 192 [DEC_IRQ_ASC_MERR] = -1, 193 [DEC_IRQ_ASC_ERR] = -1, 194 [DEC_IRQ_ASC_DMA] = -1, 195 [DEC_IRQ_FLOPPY_ERR] = -1, 196 [DEC_IRQ_ISDN_ERR] = -1, 197 [DEC_IRQ_ISDN_RXDMA] = -1, 198 [DEC_IRQ_ISDN_TXDMA] = -1, 199 [DEC_IRQ_LANCE_MERR] = -1, 200 [DEC_IRQ_SCC0A_RXERR] = -1, 201 [DEC_IRQ_SCC0A_RXDMA] = -1, 202 [DEC_IRQ_SCC0A_TXERR] = -1, 203 [DEC_IRQ_SCC0A_TXDMA] = -1, 204 [DEC_IRQ_AB_RXERR] = -1, 205 [DEC_IRQ_AB_RXDMA] = -1, 206 [DEC_IRQ_AB_TXERR] = -1, 207 [DEC_IRQ_AB_TXDMA] = -1, 208 [DEC_IRQ_SCC1A_RXERR] = -1, 209 [DEC_IRQ_SCC1A_RXDMA] = -1, 210 [DEC_IRQ_SCC1A_TXERR] = -1, 211 [DEC_IRQ_SCC1A_TXDMA] = -1, 212}; 213 214static int_ptr kn01_cpu_mask_nr_tbl[][2] __initdata = { 215 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_BUS) }, 216 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS) } }, 217 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_RTC) }, 218 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC) } }, 219 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_DZ11) }, 220 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11) } }, 221 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_SII) }, 222 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII) } }, 223 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_LANCE) }, 224 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE) } }, 225 { { .i = DEC_CPU_IRQ_ALL }, 226 { .p = cpu_all_int } }, 227}; 228 229static void __init dec_init_kn01(void) 230{ 231 /* IRQ routing. */ 232 memcpy(&dec_interrupt, &kn01_interrupt, 233 sizeof(kn01_interrupt)); 234 235 /* CPU IRQ priorities. */ 236 memcpy(&cpu_mask_nr_tbl, &kn01_cpu_mask_nr_tbl, 237 sizeof(kn01_cpu_mask_nr_tbl)); 238 239 mips_cpu_irq_init(); 240 241} /* dec_init_kn01 */ 242 243 244/* 245 * Machine-specific initialisation for KN230, aka DS5100, aka MIPSmate. 246 */ 247static int kn230_interrupt[DEC_NR_INTS] __initdata = { 248 [DEC_IRQ_CASCADE] = -1, 249 [DEC_IRQ_AB_RECV] = -1, 250 [DEC_IRQ_AB_XMIT] = -1, 251 [DEC_IRQ_DZ11] = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11), 252 [DEC_IRQ_ASC] = -1, 253 [DEC_IRQ_FLOPPY] = -1, 254 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), 255 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN230_CPU_INR_HALT), 256 [DEC_IRQ_ISDN] = -1, 257 [DEC_IRQ_LANCE] = DEC_CPU_IRQ_NR(KN230_CPU_INR_LANCE), 258 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS), 259 [DEC_IRQ_PSU] = -1, 260 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC), 261 [DEC_IRQ_SCC0] = -1, 262 [DEC_IRQ_SCC1] = -1, 263 [DEC_IRQ_SII] = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII), 264 [DEC_IRQ_TC0] = -1, 265 [DEC_IRQ_TC1] = -1, 266 [DEC_IRQ_TC2] = -1, 267 [DEC_IRQ_TIMER] = -1, 268 [DEC_IRQ_VIDEO] = -1, 269 [DEC_IRQ_ASC_MERR] = -1, 270 [DEC_IRQ_ASC_ERR] = -1, 271 [DEC_IRQ_ASC_DMA] = -1, 272 [DEC_IRQ_FLOPPY_ERR] = -1, 273 [DEC_IRQ_ISDN_ERR] = -1, 274 [DEC_IRQ_ISDN_RXDMA] = -1, 275 [DEC_IRQ_ISDN_TXDMA] = -1, 276 [DEC_IRQ_LANCE_MERR] = -1, 277 [DEC_IRQ_SCC0A_RXERR] = -1, 278 [DEC_IRQ_SCC0A_RXDMA] = -1, 279 [DEC_IRQ_SCC0A_TXERR] = -1, 280 [DEC_IRQ_SCC0A_TXDMA] = -1, 281 [DEC_IRQ_AB_RXERR] = -1, 282 [DEC_IRQ_AB_RXDMA] = -1, 283 [DEC_IRQ_AB_TXERR] = -1, 284 [DEC_IRQ_AB_TXDMA] = -1, 285 [DEC_IRQ_SCC1A_RXERR] = -1, 286 [DEC_IRQ_SCC1A_RXDMA] = -1, 287 [DEC_IRQ_SCC1A_TXERR] = -1, 288 [DEC_IRQ_SCC1A_TXDMA] = -1, 289}; 290 291static int_ptr kn230_cpu_mask_nr_tbl[][2] __initdata = { 292 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_BUS) }, 293 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS) } }, 294 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_RTC) }, 295 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC) } }, 296 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_DZ11) }, 297 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11) } }, 298 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_SII) }, 299 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII) } }, 300 { { .i = DEC_CPU_IRQ_ALL }, 301 { .p = cpu_all_int } }, 302}; 303 304static void __init dec_init_kn230(void) 305{ 306 /* IRQ routing. */ 307 memcpy(&dec_interrupt, &kn230_interrupt, 308 sizeof(kn230_interrupt)); 309 310 /* CPU IRQ priorities. */ 311 memcpy(&cpu_mask_nr_tbl, &kn230_cpu_mask_nr_tbl, 312 sizeof(kn230_cpu_mask_nr_tbl)); 313 314 mips_cpu_irq_init(); 315 316} /* dec_init_kn230 */ 317 318 319/* 320 * Machine-specific initialisation for KN02, aka DS5000/200, aka 3max. 321 */ 322static int kn02_interrupt[DEC_NR_INTS] __initdata = { 323 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02_CPU_INR_CASCADE), 324 [DEC_IRQ_AB_RECV] = -1, 325 [DEC_IRQ_AB_XMIT] = -1, 326 [DEC_IRQ_DZ11] = KN02_IRQ_NR(KN02_CSR_INR_DZ11), 327 [DEC_IRQ_ASC] = KN02_IRQ_NR(KN02_CSR_INR_ASC), 328 [DEC_IRQ_FLOPPY] = -1, 329 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), 330 [DEC_IRQ_HALT] = -1, 331 [DEC_IRQ_ISDN] = -1, 332 [DEC_IRQ_LANCE] = KN02_IRQ_NR(KN02_CSR_INR_LANCE), 333 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS), 334 [DEC_IRQ_PSU] = -1, 335 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC), 336 [DEC_IRQ_SCC0] = -1, 337 [DEC_IRQ_SCC1] = -1, 338 [DEC_IRQ_SII] = -1, 339 [DEC_IRQ_TC0] = KN02_IRQ_NR(KN02_CSR_INR_TC0), 340 [DEC_IRQ_TC1] = KN02_IRQ_NR(KN02_CSR_INR_TC1), 341 [DEC_IRQ_TC2] = KN02_IRQ_NR(KN02_CSR_INR_TC2), 342 [DEC_IRQ_TIMER] = -1, 343 [DEC_IRQ_VIDEO] = -1, 344 [DEC_IRQ_ASC_MERR] = -1, 345 [DEC_IRQ_ASC_ERR] = -1, 346 [DEC_IRQ_ASC_DMA] = -1, 347 [DEC_IRQ_FLOPPY_ERR] = -1, 348 [DEC_IRQ_ISDN_ERR] = -1, 349 [DEC_IRQ_ISDN_RXDMA] = -1, 350 [DEC_IRQ_ISDN_TXDMA] = -1, 351 [DEC_IRQ_LANCE_MERR] = -1, 352 [DEC_IRQ_SCC0A_RXERR] = -1, 353 [DEC_IRQ_SCC0A_RXDMA] = -1, 354 [DEC_IRQ_SCC0A_TXERR] = -1, 355 [DEC_IRQ_SCC0A_TXDMA] = -1, 356 [DEC_IRQ_AB_RXERR] = -1, 357 [DEC_IRQ_AB_RXDMA] = -1, 358 [DEC_IRQ_AB_TXERR] = -1, 359 [DEC_IRQ_AB_TXDMA] = -1, 360 [DEC_IRQ_SCC1A_RXERR] = -1, 361 [DEC_IRQ_SCC1A_RXDMA] = -1, 362 [DEC_IRQ_SCC1A_TXERR] = -1, 363 [DEC_IRQ_SCC1A_TXDMA] = -1, 364}; 365 366static int_ptr kn02_cpu_mask_nr_tbl[][2] __initdata = { 367 { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_BUS) }, 368 { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS) } }, 369 { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_RTC) }, 370 { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC) } }, 371 { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_CASCADE) }, 372 { .p = kn02_io_int } }, 373 { { .i = DEC_CPU_IRQ_ALL }, 374 { .p = cpu_all_int } }, 375}; 376 377static int_ptr kn02_asic_mask_nr_tbl[][2] __initdata = { 378 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_DZ11) }, 379 { .i = KN02_IRQ_NR(KN02_CSR_INR_DZ11) } }, 380 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_ASC) }, 381 { .i = KN02_IRQ_NR(KN02_CSR_INR_ASC) } }, 382 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_LANCE) }, 383 { .i = KN02_IRQ_NR(KN02_CSR_INR_LANCE) } }, 384 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC2) }, 385 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC2) } }, 386 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC1) }, 387 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC1) } }, 388 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC0) }, 389 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC0) } }, 390 { { .i = KN02_IRQ_ALL }, 391 { .p = kn02_all_int } }, 392}; 393 394static void __init dec_init_kn02(void) 395{ 396 /* IRQ routing. */ 397 memcpy(&dec_interrupt, &kn02_interrupt, 398 sizeof(kn02_interrupt)); 399 400 /* CPU IRQ priorities. */ 401 memcpy(&cpu_mask_nr_tbl, &kn02_cpu_mask_nr_tbl, 402 sizeof(kn02_cpu_mask_nr_tbl)); 403 404 /* KN02 CSR IRQ priorities. */ 405 memcpy(&asic_mask_nr_tbl, &kn02_asic_mask_nr_tbl, 406 sizeof(kn02_asic_mask_nr_tbl)); 407 408 mips_cpu_irq_init(); 409 init_kn02_irqs(KN02_IRQ_BASE); 410 411} /* dec_init_kn02 */ 412 413 414/* 415 * Machine-specific initialisation for KN02-BA, aka DS5000/1xx 416 * (xx = 20, 25, 33), aka 3min. Also applies to KN04(-BA), aka 417 * DS5000/150, aka 4min. 418 */ 419static int kn02ba_interrupt[DEC_NR_INTS] __initdata = { 420 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_CASCADE), 421 [DEC_IRQ_AB_RECV] = -1, 422 [DEC_IRQ_AB_XMIT] = -1, 423 [DEC_IRQ_DZ11] = -1, 424 [DEC_IRQ_ASC] = IO_IRQ_NR(KN02BA_IO_INR_ASC), 425 [DEC_IRQ_FLOPPY] = -1, 426 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), 427 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_HALT), 428 [DEC_IRQ_ISDN] = -1, 429 [DEC_IRQ_LANCE] = IO_IRQ_NR(KN02BA_IO_INR_LANCE), 430 [DEC_IRQ_BUS] = IO_IRQ_NR(KN02BA_IO_INR_BUS), 431 [DEC_IRQ_PSU] = IO_IRQ_NR(KN02BA_IO_INR_PSU), 432 [DEC_IRQ_RTC] = IO_IRQ_NR(KN02BA_IO_INR_RTC), 433 [DEC_IRQ_SCC0] = IO_IRQ_NR(KN02BA_IO_INR_SCC0), 434 [DEC_IRQ_SCC1] = IO_IRQ_NR(KN02BA_IO_INR_SCC1), 435 [DEC_IRQ_SII] = -1, 436 [DEC_IRQ_TC0] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0), 437 [DEC_IRQ_TC1] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1), 438 [DEC_IRQ_TC2] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2), 439 [DEC_IRQ_TIMER] = -1, 440 [DEC_IRQ_VIDEO] = -1, 441 [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR), 442 [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR), 443 [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA), 444 [DEC_IRQ_FLOPPY_ERR] = -1, 445 [DEC_IRQ_ISDN_ERR] = -1, 446 [DEC_IRQ_ISDN_RXDMA] = -1, 447 [DEC_IRQ_ISDN_TXDMA] = -1, 448 [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR), 449 [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR), 450 [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA), 451 [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR), 452 [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA), 453 [DEC_IRQ_AB_RXERR] = -1, 454 [DEC_IRQ_AB_RXDMA] = -1, 455 [DEC_IRQ_AB_TXERR] = -1, 456 [DEC_IRQ_AB_TXDMA] = -1, 457 [DEC_IRQ_SCC1A_RXERR] = IO_IRQ_NR(IO_INR_SCC1A_RXERR), 458 [DEC_IRQ_SCC1A_RXDMA] = IO_IRQ_NR(IO_INR_SCC1A_RXDMA), 459 [DEC_IRQ_SCC1A_TXERR] = IO_IRQ_NR(IO_INR_SCC1A_TXERR), 460 [DEC_IRQ_SCC1A_TXDMA] = IO_IRQ_NR(IO_INR_SCC1A_TXDMA), 461}; 462 463static int_ptr kn02ba_cpu_mask_nr_tbl[][2] __initdata = { 464 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_CASCADE) }, 465 { .p = kn02xa_io_int } }, 466 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC2) }, 467 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2) } }, 468 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC1) }, 469 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1) } }, 470 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC0) }, 471 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0) } }, 472 { { .i = DEC_CPU_IRQ_ALL }, 473 { .p = cpu_all_int } }, 474}; 475 476static int_ptr kn02ba_asic_mask_nr_tbl[][2] __initdata = { 477 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_BUS) }, 478 { .i = IO_IRQ_NR(KN02BA_IO_INR_BUS) } }, 479 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_RTC) }, 480 { .i = IO_IRQ_NR(KN02BA_IO_INR_RTC) } }, 481 { { .i = IO_IRQ_DMA }, 482 { .p = asic_dma_int } }, 483 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC0) }, 484 { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC0) } }, 485 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC1) }, 486 { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC1) } }, 487 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_ASC) }, 488 { .i = IO_IRQ_NR(KN02BA_IO_INR_ASC) } }, 489 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_LANCE) }, 490 { .i = IO_IRQ_NR(KN02BA_IO_INR_LANCE) } }, 491 { { .i = IO_IRQ_ALL }, 492 { .p = asic_all_int } }, 493}; 494 495static void __init dec_init_kn02ba(void) 496{ 497 /* IRQ routing. */ 498 memcpy(&dec_interrupt, &kn02ba_interrupt, 499 sizeof(kn02ba_interrupt)); 500 501 /* CPU IRQ priorities. */ 502 memcpy(&cpu_mask_nr_tbl, &kn02ba_cpu_mask_nr_tbl, 503 sizeof(kn02ba_cpu_mask_nr_tbl)); 504 505 /* I/O ASIC IRQ priorities. */ 506 memcpy(&asic_mask_nr_tbl, &kn02ba_asic_mask_nr_tbl, 507 sizeof(kn02ba_asic_mask_nr_tbl)); 508 509 mips_cpu_irq_init(); 510 init_ioasic_irqs(IO_IRQ_BASE); 511 512} /* dec_init_kn02ba */ 513 514 515/* 516 * Machine-specific initialisation for KN02-CA, aka DS5000/xx, 517 * (xx = 20, 25, 33), aka MAXine. Also applies to KN04(-CA), aka 518 * DS5000/50, aka 4MAXine. 519 */ 520static int kn02ca_interrupt[DEC_NR_INTS] __initdata = { 521 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_CASCADE), 522 [DEC_IRQ_AB_RECV] = IO_IRQ_NR(KN02CA_IO_INR_AB_RECV), 523 [DEC_IRQ_AB_XMIT] = IO_IRQ_NR(KN02CA_IO_INR_AB_XMIT), 524 [DEC_IRQ_DZ11] = -1, 525 [DEC_IRQ_ASC] = IO_IRQ_NR(KN02CA_IO_INR_ASC), 526 [DEC_IRQ_FLOPPY] = IO_IRQ_NR(KN02CA_IO_INR_FLOPPY), 527 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), 528 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_HALT), 529 [DEC_IRQ_ISDN] = IO_IRQ_NR(KN02CA_IO_INR_ISDN), 530 [DEC_IRQ_LANCE] = IO_IRQ_NR(KN02CA_IO_INR_LANCE), 531 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS), 532 [DEC_IRQ_PSU] = -1, 533 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC), 534 [DEC_IRQ_SCC0] = IO_IRQ_NR(KN02CA_IO_INR_SCC0), 535 [DEC_IRQ_SCC1] = -1, 536 [DEC_IRQ_SII] = -1, 537 [DEC_IRQ_TC0] = IO_IRQ_NR(KN02CA_IO_INR_TC0), 538 [DEC_IRQ_TC1] = IO_IRQ_NR(KN02CA_IO_INR_TC1), 539 [DEC_IRQ_TC2] = -1, 540 [DEC_IRQ_TIMER] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_TIMER), 541 [DEC_IRQ_VIDEO] = IO_IRQ_NR(KN02CA_IO_INR_VIDEO), 542 [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR), 543 [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR), 544 [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA), 545 [DEC_IRQ_FLOPPY_ERR] = IO_IRQ_NR(IO_INR_FLOPPY_ERR), 546 [DEC_IRQ_ISDN_ERR] = IO_IRQ_NR(IO_INR_ISDN_ERR), 547 [DEC_IRQ_ISDN_RXDMA] = IO_IRQ_NR(IO_INR_ISDN_RXDMA), 548 [DEC_IRQ_ISDN_TXDMA] = IO_IRQ_NR(IO_INR_ISDN_TXDMA), 549 [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR), 550 [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR), 551 [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA), 552 [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR), 553 [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA), 554 [DEC_IRQ_AB_RXERR] = IO_IRQ_NR(IO_INR_AB_RXERR), 555 [DEC_IRQ_AB_RXDMA] = IO_IRQ_NR(IO_INR_AB_RXDMA), 556 [DEC_IRQ_AB_TXERR] = IO_IRQ_NR(IO_INR_AB_TXERR), 557 [DEC_IRQ_AB_TXDMA] = IO_IRQ_NR(IO_INR_AB_TXDMA), 558 [DEC_IRQ_SCC1A_RXERR] = -1, 559 [DEC_IRQ_SCC1A_RXDMA] = -1, 560 [DEC_IRQ_SCC1A_TXERR] = -1, 561 [DEC_IRQ_SCC1A_TXDMA] = -1, 562}; 563 564static int_ptr kn02ca_cpu_mask_nr_tbl[][2] __initdata = { 565 { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_BUS) }, 566 { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS) } }, 567 { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_RTC) }, 568 { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC) } }, 569 { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_CASCADE) }, 570 { .p = kn02xa_io_int } }, 571 { { .i = DEC_CPU_IRQ_ALL }, 572 { .p = cpu_all_int } }, 573}; 574 575static int_ptr kn02ca_asic_mask_nr_tbl[][2] __initdata = { 576 { { .i = IO_IRQ_DMA }, 577 { .p = asic_dma_int } }, 578 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_SCC0) }, 579 { .i = IO_IRQ_NR(KN02CA_IO_INR_SCC0) } }, 580 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_ASC) }, 581 { .i = IO_IRQ_NR(KN02CA_IO_INR_ASC) } }, 582 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_LANCE) }, 583 { .i = IO_IRQ_NR(KN02CA_IO_INR_LANCE) } }, 584 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC1) }, 585 { .i = IO_IRQ_NR(KN02CA_IO_INR_TC1) } }, 586 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC0) }, 587 { .i = IO_IRQ_NR(KN02CA_IO_INR_TC0) } }, 588 { { .i = IO_IRQ_ALL }, 589 { .p = asic_all_int } }, 590}; 591 592static void __init dec_init_kn02ca(void) 593{ 594 /* IRQ routing. */ 595 memcpy(&dec_interrupt, &kn02ca_interrupt, 596 sizeof(kn02ca_interrupt)); 597 598 /* CPU IRQ priorities. */ 599 memcpy(&cpu_mask_nr_tbl, &kn02ca_cpu_mask_nr_tbl, 600 sizeof(kn02ca_cpu_mask_nr_tbl)); 601 602 /* I/O ASIC IRQ priorities. */ 603 memcpy(&asic_mask_nr_tbl, &kn02ca_asic_mask_nr_tbl, 604 sizeof(kn02ca_asic_mask_nr_tbl)); 605 606 mips_cpu_irq_init(); 607 init_ioasic_irqs(IO_IRQ_BASE); 608 609} /* dec_init_kn02ca */ 610 611 612/* 613 * Machine-specific initialisation for KN03, aka DS5000/240, 614 * aka 3max+ and DS5900, aka BIGmax. Also applies to KN05, aka 615 * DS5000/260, aka 4max+ and DS5900/260. 616 */ 617static int kn03_interrupt[DEC_NR_INTS] __initdata = { 618 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN03_CPU_INR_CASCADE), 619 [DEC_IRQ_AB_RECV] = -1, 620 [DEC_IRQ_AB_XMIT] = -1, 621 [DEC_IRQ_DZ11] = -1, 622 [DEC_IRQ_ASC] = IO_IRQ_NR(KN03_IO_INR_ASC), 623 [DEC_IRQ_FLOPPY] = -1, 624 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), 625 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN03_CPU_INR_HALT), 626 [DEC_IRQ_ISDN] = -1, 627 [DEC_IRQ_LANCE] = IO_IRQ_NR(KN03_IO_INR_LANCE), 628 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS), 629 [DEC_IRQ_PSU] = IO_IRQ_NR(KN03_IO_INR_PSU), 630 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC), 631 [DEC_IRQ_SCC0] = IO_IRQ_NR(KN03_IO_INR_SCC0), 632 [DEC_IRQ_SCC1] = IO_IRQ_NR(KN03_IO_INR_SCC1), 633 [DEC_IRQ_SII] = -1, 634 [DEC_IRQ_TC0] = IO_IRQ_NR(KN03_IO_INR_TC0), 635 [DEC_IRQ_TC1] = IO_IRQ_NR(KN03_IO_INR_TC1), 636 [DEC_IRQ_TC2] = IO_IRQ_NR(KN03_IO_INR_TC2), 637 [DEC_IRQ_TIMER] = -1, 638 [DEC_IRQ_VIDEO] = -1, 639 [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR), 640 [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR), 641 [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA), 642 [DEC_IRQ_FLOPPY_ERR] = -1, 643 [DEC_IRQ_ISDN_ERR] = -1, 644 [DEC_IRQ_ISDN_RXDMA] = -1, 645 [DEC_IRQ_ISDN_TXDMA] = -1, 646 [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR), 647 [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR), 648 [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA), 649 [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR), 650 [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA), 651 [DEC_IRQ_AB_RXERR] = -1, 652 [DEC_IRQ_AB_RXDMA] = -1, 653 [DEC_IRQ_AB_TXERR] = -1, 654 [DEC_IRQ_AB_TXDMA] = -1, 655 [DEC_IRQ_SCC1A_RXERR] = IO_IRQ_NR(IO_INR_SCC1A_RXERR), 656 [DEC_IRQ_SCC1A_RXDMA] = IO_IRQ_NR(IO_INR_SCC1A_RXDMA), 657 [DEC_IRQ_SCC1A_TXERR] = IO_IRQ_NR(IO_INR_SCC1A_TXERR), 658 [DEC_IRQ_SCC1A_TXDMA] = IO_IRQ_NR(IO_INR_SCC1A_TXDMA), 659}; 660 661static int_ptr kn03_cpu_mask_nr_tbl[][2] __initdata = { 662 { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_BUS) }, 663 { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS) } }, 664 { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_RTC) }, 665 { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC) } }, 666 { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_CASCADE) }, 667 { .p = kn03_io_int } }, 668 { { .i = DEC_CPU_IRQ_ALL }, 669 { .p = cpu_all_int } }, 670}; 671 672static int_ptr kn03_asic_mask_nr_tbl[][2] __initdata = { 673 { { .i = IO_IRQ_DMA }, 674 { .p = asic_dma_int } }, 675 { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC0) }, 676 { .i = IO_IRQ_NR(KN03_IO_INR_SCC0) } }, 677 { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC1) }, 678 { .i = IO_IRQ_NR(KN03_IO_INR_SCC1) } }, 679 { { .i = IO_IRQ_MASK(KN03_IO_INR_ASC) }, 680 { .i = IO_IRQ_NR(KN03_IO_INR_ASC) } }, 681 { { .i = IO_IRQ_MASK(KN03_IO_INR_LANCE) }, 682 { .i = IO_IRQ_NR(KN03_IO_INR_LANCE) } }, 683 { { .i = IO_IRQ_MASK(KN03_IO_INR_TC2) }, 684 { .i = IO_IRQ_NR(KN03_IO_INR_TC2) } }, 685 { { .i = IO_IRQ_MASK(KN03_IO_INR_TC1) }, 686 { .i = IO_IRQ_NR(KN03_IO_INR_TC1) } }, 687 { { .i = IO_IRQ_MASK(KN03_IO_INR_TC0) }, 688 { .i = IO_IRQ_NR(KN03_IO_INR_TC0) } }, 689 { { .i = IO_IRQ_ALL }, 690 { .p = asic_all_int } }, 691}; 692 693static void __init dec_init_kn03(void) 694{ 695 /* IRQ routing. */ 696 memcpy(&dec_interrupt, &kn03_interrupt, 697 sizeof(kn03_interrupt)); 698 699 /* CPU IRQ priorities. */ 700 memcpy(&cpu_mask_nr_tbl, &kn03_cpu_mask_nr_tbl, 701 sizeof(kn03_cpu_mask_nr_tbl)); 702 703 /* I/O ASIC IRQ priorities. */ 704 memcpy(&asic_mask_nr_tbl, &kn03_asic_mask_nr_tbl, 705 sizeof(kn03_asic_mask_nr_tbl)); 706 707 mips_cpu_irq_init(); 708 init_ioasic_irqs(IO_IRQ_BASE); 709 710} /* dec_init_kn03 */ 711 712 713void __init arch_init_irq(void) 714{ 715 switch (mips_machtype) { 716 case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */ 717 dec_init_kn01(); 718 break; 719 case MACH_DS5100: /* DS5100 MIPSmate */ 720 dec_init_kn230(); 721 break; 722 case MACH_DS5000_200: /* DS5000/200 3max */ 723 dec_init_kn02(); 724 break; 725 case MACH_DS5000_1XX: /* DS5000/1xx 3min */ 726 dec_init_kn02ba(); 727 break; 728 case MACH_DS5000_2X0: /* DS5000/240 3max+ */ 729 case MACH_DS5900: /* DS5900 bigmax */ 730 dec_init_kn03(); 731 break; 732 case MACH_DS5000_XX: /* Personal DS5000/xx */ 733 dec_init_kn02ca(); 734 break; 735 case MACH_DS5800: /* DS5800 Isis */ 736 panic("Don't know how to set this up!"); 737 break; 738 case MACH_DS5400: /* DS5400 MIPSfair */ 739 panic("Don't know how to set this up!"); 740 break; 741 case MACH_DS5500: /* DS5500 MIPSfair-2 */ 742 panic("Don't know how to set this up!"); 743 break; 744 } 745 746 /* Free the FPU interrupt if the exception is present. */ 747 if (!cpu_has_nofpuex) { 748 cpu_fpu_mask = 0; 749 dec_interrupt[DEC_IRQ_FPU] = -1; 750 } 751 752 /* Register board interrupts: FPU and cascade. */ 753 if (dec_interrupt[DEC_IRQ_FPU] >= 0) 754 setup_irq(dec_interrupt[DEC_IRQ_FPU], &fpuirq); 755 if (dec_interrupt[DEC_IRQ_CASCADE] >= 0) 756 setup_irq(dec_interrupt[DEC_IRQ_CASCADE], &ioirq); 757 758 /* Register the bus error interrupt. */ 759 if (dec_interrupt[DEC_IRQ_BUS] >= 0 && busirq.handler) 760 setup_irq(dec_interrupt[DEC_IRQ_BUS], &busirq); 761 762 /* Register the HALT interrupt. */ 763 if (dec_interrupt[DEC_IRQ_HALT] >= 0) 764 setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq); 765} 766 767asmlinkage unsigned int dec_irq_dispatch(unsigned int irq) 768{ 769 do_IRQ(irq); 770 return 0; 771} 772