1/* 2 * 3 * Copyright 2001 MontaVista Software Inc. 4 * Author: jsun@mvista.com or jsun@junsun.net 5 * 6 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) 7 * 8 * arch/mips/ddb5xxx/ddb5477/setup.c 9 * Setup file for DDB5477. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 */ 16#include <linux/init.h> 17#include <linux/kernel.h> 18#include <linux/types.h> 19#include <linux/sched.h> 20#include <linux/pci.h> 21#include <linux/ide.h> 22#include <linux/irq.h> 23#include <linux/fs.h> 24#include <linux/ioport.h> 25#include <linux/param.h> /* for HZ */ 26#include <linux/major.h> 27#include <linux/kdev_t.h> 28#include <linux/root_dev.h> 29#include <linux/pm.h> 30 31#include <asm/cpu.h> 32#include <asm/bootinfo.h> 33#include <asm/addrspace.h> 34#include <asm/time.h> 35#include <asm/bcache.h> 36#include <asm/irq.h> 37#include <asm/reboot.h> 38#include <asm/gdb-stub.h> 39#include <asm/traps.h> 40#include <asm/debug.h> 41 42#include <asm/ddb5xxx/ddb5xxx.h> 43 44#include "lcd44780.h" 45 46 47#define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */ 48 49#define SP_TIMER_BASE DDB_SPT1CTRL_L 50#define SP_TIMER_IRQ VRC5477_IRQ_SPT1 51 52static int bus_frequency = CONFIG_DDB5477_BUS_FREQUENCY*1000; 53 54static void ddb_machine_restart(char *command) 55{ 56 static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000; 57 58 u32 t; 59 60 /* PCI cold reset */ 61 ddb_pci_reset_bus(); 62 63 /* CPU cold reset */ 64 t = ddb_in32(DDB_CPUSTAT); 65 db_assert((t&1)); 66 ddb_out32(DDB_CPUSTAT, t); 67 68 /* Call the PROM */ 69 back_to_prom(); 70} 71 72static void ddb_machine_halt(void) 73{ 74 printk("DDB Vrc-5477 halted.\n"); 75 while (1); 76} 77 78static void ddb_machine_power_off(void) 79{ 80 printk("DDB Vrc-5477 halted. Please turn off the power.\n"); 81 while (1); 82} 83 84extern void rtc_ds1386_init(unsigned long base); 85 86static unsigned int __init detect_bus_frequency(unsigned long rtc_base) 87{ 88 unsigned int freq; 89 unsigned char c; 90 unsigned int t1, t2; 91 unsigned i; 92 93 ddb_out32(SP_TIMER_BASE, 0xffffffff); 94 ddb_out32(SP_TIMER_BASE+4, 0x1); 95 ddb_out32(SP_TIMER_BASE+8, 0xffffffff); 96 97 /* check if rtc is running */ 98 c= *(volatile unsigned char*)rtc_base; 99 for(i=0; (c == *(volatile unsigned char*)rtc_base) && (i<100000000); i++); 100 if (c == *(volatile unsigned char*)rtc_base) { 101 printk("Failed to detect bus frequency. Use default 83.3MHz.\n"); 102 return 83333000; 103 } 104 105 c= *(volatile unsigned char*)rtc_base; 106 while (c == *(volatile unsigned char*)rtc_base); 107 /* we are now at the turn of 1/100th second, if no error. */ 108 t1 = ddb_in32(SP_TIMER_BASE+8); 109 110 for (i=0; i< 10; i++) { 111 c= *(volatile unsigned char*)rtc_base; 112 while (c == *(volatile unsigned char*)rtc_base); 113 /* we are now at the turn of another 1/100th second */ 114 t2 = ddb_in32(SP_TIMER_BASE+8); 115 } 116 117 ddb_out32(SP_TIMER_BASE+4, 0x0); /* disable it again */ 118 119 freq = (t1 - t2)*10; 120 printk("DDB bus frequency detection : %u \n", freq); 121 return freq; 122} 123 124static void __init ddb_time_init(void) 125{ 126 unsigned long rtc_base; 127 unsigned int i; 128 129 /* we have ds1396 RTC chip */ 130 if (mips_machtype == MACH_NEC_ROCKHOPPER 131 || mips_machtype == MACH_NEC_ROCKHOPPERII) { 132 rtc_base = KSEG1ADDR(DDB_LCS2_BASE); 133 } else { 134 rtc_base = KSEG1ADDR(DDB_LCS1_BASE); 135 } 136 rtc_ds1386_init(rtc_base); 137 138 /* do we need to do run-time detection of bus speed? */ 139 if (bus_frequency == 0) { 140 bus_frequency = detect_bus_frequency(rtc_base); 141 } 142 143 /* mips_hpt_frequency is 1/2 of the cpu core freq */ 144 i = (read_c0_config() >> 28 ) & 7; 145 if ((current_cpu_data.cputype == CPU_R5432) && (i == 3)) 146 i = 4; 147 mips_hpt_frequency = bus_frequency*(i+4)/4; 148} 149 150void __init plat_timer_setup(struct irqaction *irq) 151{ 152#if defined(USE_CPU_COUNTER_TIMER) 153 154 /* we are using the cpu counter for timer interrupts */ 155 setup_irq(CPU_IRQ_BASE + 7, irq); 156 157#else 158 159 /* if we use Special purpose timer 1 */ 160 ddb_out32(SP_TIMER_BASE, bus_frequency/HZ); 161 ddb_out32(SP_TIMER_BASE+4, 0x1); 162 setup_irq(SP_TIMER_IRQ, irq); 163 164#endif 165} 166 167static void ddb5477_board_init(void); 168 169extern struct pci_controller ddb5477_ext_controller; 170extern struct pci_controller ddb5477_io_controller; 171 172void __init plat_mem_setup(void) 173{ 174 /* initialize board - we don't trust the loader */ 175 ddb5477_board_init(); 176 177 set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE)); 178 179 board_time_init = ddb_time_init; 180 181 _machine_restart = ddb_machine_restart; 182 _machine_halt = ddb_machine_halt; 183 pm_power_off = ddb_machine_power_off; 184 185 /* setup resource limits */ 186 ioport_resource.end = DDB_PCI0_IO_SIZE + DDB_PCI1_IO_SIZE - 1; 187 iomem_resource.end = 0xffffffff; 188 189 /* Reboot on panic */ 190 panic_timeout = 180; 191 192 register_pci_controller (&ddb5477_ext_controller); 193 register_pci_controller (&ddb5477_io_controller); 194} 195 196static void __init ddb5477_board_init(void) 197{ 198 /* ----------- setup PDARs ------------ */ 199 200 /* SDRAM should have been set */ 201 db_assert(ddb_in32(DDB_SDRAM0) == 202 ddb_calc_pdar(DDB_SDRAM_BASE, board_ram_size, 32, 0, 1)); 203 204 /* SDRAM1 should be turned off. What is this for anyway ? */ 205 db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0); 206 207 /* Setup local bus. */ 208 209 /* Flash U12 PDAR and timing. */ 210 ddb_set_pdar(DDB_LCS0, DDB_LCS0_BASE, DDB_LCS0_SIZE, 16, 0, 0); 211 ddb_out32(DDB_LCST0, 0x00090842); 212 213 /* We need to setup LCS1 and LCS2 differently based on the 214 board_version */ 215 if (mips_machtype == MACH_NEC_ROCKHOPPER) { 216 /* Flash U13 PDAR and timing. */ 217 ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 16, 0, 0); 218 ddb_out32(DDB_LCST1, 0x00090842); 219 220 /* EPLD (NVRAM, switch, LCD, and mezzanie). */ 221 ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 8, 0, 0); 222 } else { 223 /* misc */ 224 ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 8, 0, 0); 225 /* mezzanie (?) */ 226 ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 16, 0, 0); 227 } 228 229 /* verify VRC5477 base addr */ 230 db_assert(ddb_in32(DDB_VRC5477) == 231 ddb_calc_pdar(DDB_VRC5477_BASE, DDB_VRC5477_SIZE, 32, 0, 1)); 232 233 /* verify BOOT ROM addr */ 234 db_assert(ddb_in32(DDB_BOOTCS) == 235 ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0)); 236 237 /* setup PCI windows - window0 for MEM/config, window1 for IO */ 238 ddb_set_pdar(DDB_PCIW0, DDB_PCI0_MEM_BASE, DDB_PCI0_MEM_SIZE, 32, 0, 1); 239 ddb_set_pdar(DDB_PCIW1, DDB_PCI0_IO_BASE, DDB_PCI0_IO_SIZE, 32, 0, 1); 240 ddb_set_pdar(DDB_IOPCIW0, DDB_PCI1_MEM_BASE, DDB_PCI1_MEM_SIZE, 32, 0, 1); 241 ddb_set_pdar(DDB_IOPCIW1, DDB_PCI1_IO_BASE, DDB_PCI1_IO_SIZE, 32, 0, 1); 242 243 /* ------------ reset PCI bus and BARs ----------------- */ 244 ddb_pci_reset_bus(); 245 246 ddb_out32(DDB_BARM010, 0x00000008); 247 ddb_out32(DDB_BARM011, 0x00000008); 248 249 ddb_out32(DDB_BARC0, 0xffffffff); 250 ddb_out32(DDB_BARM230, 0xffffffff); 251 ddb_out32(DDB_BAR00, 0xffffffff); 252 ddb_out32(DDB_BAR10, 0xffffffff); 253 ddb_out32(DDB_BAR20, 0xffffffff); 254 ddb_out32(DDB_BAR30, 0xffffffff); 255 ddb_out32(DDB_BAR40, 0xffffffff); 256 ddb_out32(DDB_BAR50, 0xffffffff); 257 ddb_out32(DDB_BARB0, 0xffffffff); 258 259 ddb_out32(DDB_BARC1, 0xffffffff); 260 ddb_out32(DDB_BARM231, 0xffffffff); 261 ddb_out32(DDB_BAR01, 0xffffffff); 262 ddb_out32(DDB_BAR11, 0xffffffff); 263 ddb_out32(DDB_BAR21, 0xffffffff); 264 ddb_out32(DDB_BAR31, 0xffffffff); 265 ddb_out32(DDB_BAR41, 0xffffffff); 266 ddb_out32(DDB_BAR51, 0xffffffff); 267 ddb_out32(DDB_BARB1, 0xffffffff); 268 269 /* 270 * We use pci master register 0 for memory space / config space 271 * And we use register 1 for IO space. 272 * Note that for memory space, we bump up the pci base address 273 * so that we have 1:1 mapping between PCI memory and cpu physical. 274 * For PCI IO space, it starts from 0 in PCI IO space but with 275 * DDB_xx_IO_BASE in CPU physical address space. 276 */ 277 ddb_set_pmr(DDB_PCIINIT00, DDB_PCICMD_MEM, DDB_PCI0_MEM_BASE, 278 DDB_PCI_ACCESS_32); 279 ddb_set_pmr(DDB_PCIINIT10, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32); 280 281 ddb_set_pmr(DDB_PCIINIT01, DDB_PCICMD_MEM, DDB_PCI1_MEM_BASE, 282 DDB_PCI_ACCESS_32); 283 ddb_set_pmr(DDB_PCIINIT11, DDB_PCICMD_IO, DDB_PCI0_IO_SIZE, 284 DDB_PCI_ACCESS_32); 285 286 287 /* PCI cross window should be set properly */ 288 ddb_set_pdar(DDB_BARP00, DDB_PCI1_MEM_BASE, DDB_PCI1_MEM_SIZE, 32, 0, 1); 289 ddb_set_pdar(DDB_BARP10, DDB_PCI1_IO_BASE, DDB_PCI1_IO_SIZE, 32, 0, 1); 290 ddb_set_pdar(DDB_BARP01, DDB_PCI0_MEM_BASE, DDB_PCI0_MEM_SIZE, 32, 0, 1); 291 ddb_set_pdar(DDB_BARP11, DDB_PCI0_IO_BASE, DDB_PCI0_IO_SIZE, 32, 0, 1); 292 293 if (mips_machtype == MACH_NEC_ROCKHOPPER 294 || mips_machtype == MACH_NEC_ROCKHOPPERII) { 295 /* Disable bus diagnostics. */ 296 ddb_out32(DDB_PCICTL0_L, 0); 297 ddb_out32(DDB_PCICTL0_H, 0); 298 ddb_out32(DDB_PCICTL1_L, 0); 299 ddb_out32(DDB_PCICTL1_H, 0); 300 } 301 302 if (mips_machtype == MACH_NEC_ROCKHOPPER) { 303 u16 vid; 304 struct pci_bus bus; 305 struct pci_dev dev_m1533; 306 extern struct pci_ops ddb5477_ext_pci_ops; 307 308 bus.parent = NULL; /* we scan the top level only */ 309 bus.ops = &ddb5477_ext_pci_ops; 310 dev_m1533.bus = &bus; 311 dev_m1533.sysdata = NULL; 312 dev_m1533.devfn = 7*8; // slot 7: M1533 SouthBridge. 313 pci_read_config_word(&dev_m1533, 0, &vid); 314 if (vid == PCI_VENDOR_ID_AL) { 315 printk("Changing mips_machtype to MACH_NEC_ROCKHOPPERII\n"); 316 mips_machtype = MACH_NEC_ROCKHOPPERII; 317 } 318 } 319 320 /* enable USB input buffers */ 321 ddb_out32(DDB_PIBMISC, 0x00000007); 322 323 /* For dual-function pins, make them all non-GPIO */ 324 ddb_out32(DDB_GIUFUNSEL, 0x0); 325 // ddb_out32(DDB_GIUFUNSEL, 0xfe0fcfff); /* NEC recommanded value */ 326 327 if (mips_machtype == MACH_NEC_ROCKHOPPERII) { 328 329 /* enable IDE controller on Ali chip (south bridge) */ 330 u8 temp8; 331 struct pci_bus bus; 332 struct pci_dev dev_m1533; 333 struct pci_dev dev_m5229; 334 extern struct pci_ops ddb5477_ext_pci_ops; 335 336 /* Setup M1535 registers */ 337 bus.parent = NULL; /* we scan the top level only */ 338 bus.ops = &ddb5477_ext_pci_ops; 339 dev_m1533.bus = &bus; 340 dev_m1533.sysdata = NULL; 341 dev_m1533.devfn = 7*8; // slot 7: M1533 SouthBridge. 342 343 /* setup IDE controller 344 * enable IDE controller (bit 6 - 1) 345 * IDE IDSEL to be addr:A15 (bit 4:5 - 11) 346 * disable IDE ATA Secondary Bus Signal Pad Control (bit 3 - 0) 347 * enable IDE ATA Primary Bus Signal Pad Control (bit 2 - 1) 348 */ 349 pci_write_config_byte(&dev_m1533, 0x58, 0x74); 350 351 /* 352 * positive decode (bit6 -0) 353 * enable IDE controler interrupt (bit 4 -1) 354 * setup SIRQ to point to IRQ 14 (bit 3:0 - 1101) 355 */ 356 pci_write_config_byte(&dev_m1533, 0x44, 0x1d); 357 358 /* Setup M5229 registers */ 359 dev_m5229.bus = &bus; 360 dev_m5229.sysdata = NULL; 361 dev_m5229.devfn = 4*8; // slot 4 (AD15): M5229 IDE 362 363 /* 364 * enable IDE in the M5229 config register 0x50 (bit 0 - 1) 365 * M5229 IDSEL is addr:15; see above setting 366 */ 367 pci_read_config_byte(&dev_m5229, 0x50, &temp8); 368 pci_write_config_byte(&dev_m5229, 0x50, temp8 | 0x1); 369 370 /* 371 * enable bus master (bit 2) and IO decoding (bit 0) 372 */ 373 pci_read_config_byte(&dev_m5229, 0x04, &temp8); 374 pci_write_config_byte(&dev_m5229, 0x04, temp8 | 0x5); 375 376 /* 377 * enable native, copied from arch/ppc/k2boot/head.S 378 * TODO - need volatile, need to be portable 379 */ 380 pci_write_config_byte(&dev_m5229, 0x09, 0xef); 381 382 /* Set Primary Channel Command Block Timing */ 383 pci_write_config_byte(&dev_m5229, 0x59, 0x31); 384 385 /* 386 * Enable primary channel 40-pin cable 387 * M5229 register 0x4a (bit 0) 388 */ 389 pci_read_config_byte(&dev_m5229, 0x4a, &temp8); 390 pci_write_config_byte(&dev_m5229, 0x4a, temp8 | 0x1); 391 } 392 393 if (mips_machtype == MACH_NEC_ROCKHOPPER 394 || mips_machtype == MACH_NEC_ROCKHOPPERII) { 395 printk("lcd44780: initializing\n"); 396 lcd44780_init(); 397 lcd44780_puts("MontaVista Linux"); 398 } 399} 400