1/* 2 * Copyright 2001 MontaVista Software Inc. 3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net 4 * 5 * arch/mips/ddb5xxx/ddb5477/irq.c 6 * The irq setup and misc routines for DDB5476. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 */ 13#include <linux/init.h> 14#include <linux/interrupt.h> 15#include <linux/irq.h> 16#include <linux/types.h> 17#include <linux/ptrace.h> 18 19#include <asm/i8259.h> 20#include <asm/irq_cpu.h> 21#include <asm/system.h> 22#include <asm/mipsregs.h> 23#include <asm/debug.h> 24#include <asm/addrspace.h> 25#include <asm/bootinfo.h> 26 27#include <asm/ddb5xxx/ddb5xxx.h> 28 29 30/* 31 * IRQ mapping 32 * 33 * 0-7: 8 CPU interrupts 34 * 0 - software interrupt 0 35 * 1 - software interrupt 1 36 * 2 - most Vrc5477 interrupts are routed to this pin 37 * 3 - (optional) some other interrupts routed to this pin for debugg 38 * 4 - not used 39 * 5 - not used 40 * 6 - not used 41 * 7 - cpu timer (used by default) 42 * 43 * 8-39: 32 Vrc5477 interrupt sources 44 * (refer to the Vrc5477 manual) 45 */ 46 47#define PCI0 DDB_INTPPES0 48#define PCI1 DDB_INTPPES1 49 50#define ACTIVE_LOW 1 51#define ACTIVE_HIGH 0 52 53#define LEVEL_SENSE 2 54#define EDGE_TRIGGER 0 55 56#define INTA 0 57#define INTB 1 58#define INTC 2 59#define INTD 3 60#define INTE 4 61 62static inline void 63set_pci_int_attr(u32 pci, u32 intn, u32 active, u32 trigger) 64{ 65 u32 reg_value; 66 u32 reg_bitmask; 67 68 reg_value = ddb_in32(pci); 69 reg_bitmask = 0x3 << (intn * 2); 70 71 reg_value &= ~reg_bitmask; 72 reg_value |= (active | trigger) << (intn * 2); 73 ddb_out32(pci, reg_value); 74} 75 76extern void vrc5477_irq_init(u32 base); 77static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL }; 78 79void __init arch_init_irq(void) 80{ 81 /* by default, we disable all interrupts and route all vrc5477 82 * interrupts to pin 0 (irq 2) */ 83 ddb_out32(DDB_INTCTRL0, 0); 84 ddb_out32(DDB_INTCTRL1, 0); 85 ddb_out32(DDB_INTCTRL2, 0); 86 ddb_out32(DDB_INTCTRL3, 0); 87 88 clear_c0_status(0xff00); 89 set_c0_status(0x0400); 90 91 /* setup PCI interrupt attributes */ 92 set_pci_int_attr(PCI0, INTA, ACTIVE_LOW, LEVEL_SENSE); 93 set_pci_int_attr(PCI0, INTB, ACTIVE_LOW, LEVEL_SENSE); 94 if (mips_machtype == MACH_NEC_ROCKHOPPERII) 95 set_pci_int_attr(PCI0, INTC, ACTIVE_HIGH, LEVEL_SENSE); 96 else 97 set_pci_int_attr(PCI0, INTC, ACTIVE_LOW, LEVEL_SENSE); 98 set_pci_int_attr(PCI0, INTD, ACTIVE_LOW, LEVEL_SENSE); 99 set_pci_int_attr(PCI0, INTE, ACTIVE_LOW, LEVEL_SENSE); 100 101 set_pci_int_attr(PCI1, INTA, ACTIVE_LOW, LEVEL_SENSE); 102 set_pci_int_attr(PCI1, INTB, ACTIVE_LOW, LEVEL_SENSE); 103 set_pci_int_attr(PCI1, INTC, ACTIVE_LOW, LEVEL_SENSE); 104 set_pci_int_attr(PCI1, INTD, ACTIVE_LOW, LEVEL_SENSE); 105 set_pci_int_attr(PCI1, INTE, ACTIVE_LOW, LEVEL_SENSE); 106 107 /* 108 * for debugging purpose, we enable several error interrupts 109 * and route them to pin 1. (IP3) 110 */ 111 /* cpu parity check - 0 */ 112 ll_vrc5477_irq_route(0, 1); ll_vrc5477_irq_enable(0); 113 /* cpu no-target decode - 1 */ 114 ll_vrc5477_irq_route(1, 1); ll_vrc5477_irq_enable(1); 115 /* local bus read time-out - 7 */ 116 ll_vrc5477_irq_route(7, 1); ll_vrc5477_irq_enable(7); 117 /* PCI SERR# - 14 */ 118 ll_vrc5477_irq_route(14, 1); ll_vrc5477_irq_enable(14); 119 /* PCI internal error - 15 */ 120 ll_vrc5477_irq_route(15, 1); ll_vrc5477_irq_enable(15); 121 /* IOPCI SERR# - 30 */ 122 ll_vrc5477_irq_route(30, 1); ll_vrc5477_irq_enable(30); 123 /* IOPCI internal error - 31 */ 124 ll_vrc5477_irq_route(31, 1); ll_vrc5477_irq_enable(31); 125 126 /* init all controllers */ 127 init_i8259_irqs(); 128 mips_cpu_irq_init(); 129 vrc5477_irq_init(VRC5477_IRQ_BASE); 130 131 132 /* setup cascade interrupts */ 133 setup_irq(VRC5477_IRQ_BASE + VRC5477_I8259_CASCADE, &irq_cascade); 134 setup_irq(CPU_IRQ_BASE + CPU_VRC5477_CASCADE, &irq_cascade); 135} 136 137u8 i8259_interrupt_ack(void) 138{ 139 u8 irq; 140 u32 reg; 141 142 /* Set window 0 for interrupt acknowledge */ 143 reg = ddb_in32(DDB_PCIINIT10); 144 145 ddb_set_pmr(DDB_PCIINIT10, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32); 146 irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE); 147 ddb_out32(DDB_PCIINIT10, reg); 148 149 return irq; 150} 151/* 152 * the first level int-handler will jump here if it is a vrc5477 irq 153 */ 154#define NUM_5477_IRQS 32 155static void vrc5477_irq_dispatch(void) 156{ 157 u32 intStatus; 158 u32 bitmask; 159 u32 i; 160 161 db_assert(ddb_in32(DDB_INT2STAT) == 0); 162 db_assert(ddb_in32(DDB_INT3STAT) == 0); 163 db_assert(ddb_in32(DDB_INT4STAT) == 0); 164 db_assert(ddb_in32(DDB_NMISTAT) == 0); 165 166 if (ddb_in32(DDB_INT1STAT) != 0) { 167#if defined(CONFIG_RUNTIME_DEBUG) 168 vrc5477_show_int_regs(); 169#endif 170 panic("error interrupt has happened."); 171 } 172 173 intStatus = ddb_in32(DDB_INT0STAT); 174 175 if (mips_machtype == MACH_NEC_ROCKHOPPERII) { 176 /* check for i8259 interrupts */ 177 if (intStatus & (1 << VRC5477_I8259_CASCADE)) { 178 int i8259_irq = i8259_interrupt_ack(); 179 do_IRQ(i8259_irq); 180 return; 181 } 182 } 183 184 for (i=0, bitmask=1; i<= NUM_5477_IRQS; bitmask <<=1, i++) { 185 /* do we need to "and" with the int mask? */ 186 if (intStatus & bitmask) { 187 do_IRQ(VRC5477_IRQ_BASE + i); 188 return; 189 } 190 } 191} 192 193#define VR5477INTS (STATUSF_IP2|STATUSF_IP3|STATUSF_IP4|STATUSF_IP5|STATUSF_IP6) 194 195asmlinkage void plat_irq_dispatch(void) 196{ 197 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; 198 199 if (pending & STATUSF_IP7) 200 do_IRQ(CPU_IRQ_BASE + 7); 201 else if (pending & VR5477INTS) 202 vrc5477_irq_dispatch(); 203 else if (pending & STATUSF_IP0) 204 do_IRQ(CPU_IRQ_BASE); 205 else if (pending & STATUSF_IP1) 206 do_IRQ(CPU_IRQ_BASE + 1); 207 else 208 spurious_interrupt(); 209} 210