1/*
2 * Copyright 2000 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc.
4 *         	ppopov@mvista.com or source@mvista.com
5 *
6 *  This program is free software; you can redistribute  it and/or modify it
7 *  under  the terms of  the GNU General  Public License as published by the
8 *  Free Software Foundation;  either version 2 of the  License, or (at your
9 *  option) any later version.
10 *
11 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
12 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
13 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
14 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
15 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
17 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
19 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 *  You should have received a copy of the  GNU General Public License along
23 *  with this program; if not, write  to the Free Software Foundation, Inc.,
24 *  675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26#include <linux/init.h>
27#include <linux/sched.h>
28#include <linux/ioport.h>
29#include <linux/mm.h>
30#include <linux/console.h>
31#include <linux/delay.h>
32
33#include <asm/cpu.h>
34#include <asm/bootinfo.h>
35#include <asm/irq.h>
36#include <asm/mipsregs.h>
37#include <asm/reboot.h>
38#include <asm/pgtable.h>
39#include <asm/mach-au1x00/au1000.h>
40#include <asm/mach-pb1x00/pb1500.h>
41
42void board_reset (void)
43{
44    /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
45    au_writel(0x00000000, 0xAE00001C);
46}
47
48void __init board_setup(void)
49{
50	u32 pin_func;
51	u32 sys_freqctrl, sys_clksrc;
52
53	sys_clksrc = sys_freqctrl = pin_func = 0;
54	// set AUX clock to 12MHz * 8 = 96 MHz
55	au_writel(8, SYS_AUXPLL);
56	au_writel(0, SYS_PINSTATERD);
57	udelay(100);
58
59#ifdef CONFIG_USB_OHCI
60
61	/* GPIO201 is input for PCMCIA card detect */
62	/* GPIO203 is input for PCMCIA interrupt request */
63	au_writel(au_readl(GPIO2_DIR) & (u32)(~((1<<1)|(1<<3))), GPIO2_DIR);
64
65	/* zero and disable FREQ2 */
66	sys_freqctrl = au_readl(SYS_FREQCTRL0);
67	sys_freqctrl &= ~0xFFF00000;
68	au_writel(sys_freqctrl, SYS_FREQCTRL0);
69
70	/* zero and disable USBH/USBD clocks */
71	sys_clksrc = au_readl(SYS_CLKSRC);
72	sys_clksrc &= ~0x00007FE0;
73	au_writel(sys_clksrc, SYS_CLKSRC);
74
75	sys_freqctrl = au_readl(SYS_FREQCTRL0);
76	sys_freqctrl &= ~0xFFF00000;
77
78	sys_clksrc = au_readl(SYS_CLKSRC);
79	sys_clksrc &= ~0x00007FE0;
80
81	// FREQ2 = aux/2 = 48 MHz
82	sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20));
83	au_writel(sys_freqctrl, SYS_FREQCTRL0);
84
85	/*
86	 * Route 48MHz FREQ2 into USB Host and/or Device
87	 */
88#ifdef CONFIG_USB_OHCI
89	sys_clksrc |= ((4<<12) | (0<<11) | (0<<10));
90#endif
91	au_writel(sys_clksrc, SYS_CLKSRC);
92
93
94	pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8000);
95	// 2nd USB port is USB host
96	pin_func |= 0x8000;
97	au_writel(pin_func, SYS_PINFUNC);
98#endif // defined (CONFIG_USB_OHCI)
99
100
101
102#ifdef CONFIG_PCI
103	// Setup PCI bus controller
104	au_writel(0, Au1500_PCI_CMEM);
105	au_writel(0x00003fff, Au1500_CFG_BASE);
106#if defined(__MIPSEB__)
107	au_writel(0xf | (2<<6) | (1<<4), Au1500_PCI_CFG);
108#else
109	au_writel(0xf, Au1500_PCI_CFG);
110#endif
111	au_writel(0xf0000000, Au1500_PCI_MWMASK_DEV);
112	au_writel(0, Au1500_PCI_MWBASE_REV_CCL);
113	au_writel(0x02a00356, Au1500_PCI_STATCMD);
114	au_writel(0x00003c04, Au1500_PCI_HDRTYPE);
115	au_writel(0x00000008, Au1500_PCI_MBAR);
116	au_sync();
117#endif
118
119	/* Enable sys bus clock divider when IDLE state or no bus activity. */
120	au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
121
122	/* Enable the RTC if not already enabled */
123	if (!(au_readl(0xac000028) & 0x20)) {
124		printk("enabling clock ...\n");
125		au_writel((au_readl(0xac000028) | 0x20), 0xac000028);
126	}
127	/* Put the clock in BCD mode */
128	if (au_readl(0xac00002C) & 0x4) { /* reg B */
129		au_writel(au_readl(0xac00002c) & ~0x4, 0xac00002c);
130		au_sync();
131	}
132}
133