1/*
2 * Copyright 2000 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc.
4 *         	ppopov@mvista.com or source@mvista.com
5 *
6 * Updates to 2.6, Pete Popov, Embedded Alley Solutions, Inc.
7 *
8 *  This program is free software; you can redistribute  it and/or modify it
9 *  under  the terms of  the GNU General  Public License as published by the
10 *  Free Software Foundation;  either version 2 of the  License, or (at your
11 *  option) any later version.
12 *
13 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
14 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
15 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
16 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
17 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
19 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
21 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 *  You should have received a copy of the  GNU General Public License along
25 *  with this program; if not, write  to the Free Software Foundation, Inc.,
26 *  675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28#include <linux/init.h>
29#include <linux/sched.h>
30#include <linux/ioport.h>
31#include <linux/mm.h>
32#include <linux/delay.h>
33#include <linux/interrupt.h>
34#include <linux/module.h>
35#include <linux/pm.h>
36
37#include <asm/cpu.h>
38#include <asm/bootinfo.h>
39#include <asm/irq.h>
40#include <asm/mipsregs.h>
41#include <asm/reboot.h>
42#include <asm/pgtable.h>
43#include <asm/mach-au1x00/au1000.h>
44#include <asm/time.h>
45
46extern char * prom_getcmdline(void);
47extern void __init board_setup(void);
48extern void au1000_restart(char *);
49extern void au1000_halt(void);
50extern void au1000_power_off(void);
51extern void au1x_time_init(void);
52extern void au1x_timer_setup(struct irqaction *irq);
53extern void au1xxx_time_init(void);
54extern void set_cpuspec(void);
55
56void __init plat_mem_setup(void)
57{
58	struct	cpu_spec *sp;
59	char *argptr;
60	unsigned long prid, cpupll, bclk = 1;
61
62	set_cpuspec();
63	sp = cur_cpu_spec[0];
64
65	board_setup();  /* board specific setup */
66
67	prid = read_c0_prid();
68	cpupll = (au_readl(0xB1900060) & 0x3F) * 12;
69	printk("(PRId %08lx) @ %ldMHZ\n", prid, cpupll);
70
71	bclk = sp->cpu_bclk;
72	if (bclk)
73	{
74		/* Enable BCLK switching */
75		bclk = au_readl(0xB190003C);
76		au_writel(bclk | 0x60, 0xB190003C);
77		printk("BCLK switching enabled!\n");
78	}
79
80	if (sp->cpu_od) {
81		/* Various early Au1000 Errata corrected by this */
82		set_c0_config(1<<19); /* Set Config[OD] */
83	}
84	else {
85		/* Clear to obtain best system bus performance */
86		clear_c0_config(1<<19); /* Clear Config[OD] */
87	}
88
89	argptr = prom_getcmdline();
90
91#ifdef CONFIG_SERIAL_8250_CONSOLE
92	if ((argptr = strstr(argptr, "console=")) == NULL) {
93		argptr = prom_getcmdline();
94		strcat(argptr, " console=ttyS0,115200");
95	}
96#endif
97
98#ifdef CONFIG_FB_AU1100
99    if ((argptr = strstr(argptr, "video=")) == NULL) {
100        argptr = prom_getcmdline();
101        /* default panel */
102        /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/
103#ifdef CONFIG_MIPS_HYDROGEN3
104         strcat(argptr, " video=au1100fb:panel:Hydrogen_3_NEC_panel_320x240,nohwcursor");
105#endif
106    }
107#endif
108
109#ifdef CONFIG_FB_XPERT98
110	if ((argptr = strstr(argptr, "video=")) == NULL) {
111		argptr = prom_getcmdline();
112		strcat(argptr, " video=atyfb:1024x768-8@70");
113	}
114#endif
115
116#if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000)
117	/* au1000 does not support vra, au1500 and au1100 do */
118	strcat(argptr, " au1000_audio=vra");
119	argptr = prom_getcmdline();
120#endif
121	_machine_restart = au1000_restart;
122	_machine_halt = au1000_halt;
123	pm_power_off = au1000_power_off;
124	board_time_init = au1xxx_time_init;
125
126	/* IO/MEM resources. */
127	set_io_port_base(0);
128	ioport_resource.start = IOPORT_RESOURCE_START;
129	ioport_resource.end = IOPORT_RESOURCE_END;
130	iomem_resource.start = IOMEM_RESOURCE_START;
131	iomem_resource.end = IOMEM_RESOURCE_END;
132
133	while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_E0S);
134	au_writel(SYS_CNTRL_E0 | SYS_CNTRL_EN0, SYS_COUNTER_CNTRL);
135	au_sync();
136	while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S);
137	au_writel(0, SYS_TOYTRIM);
138}
139
140#if defined(CONFIG_64BIT_PHYS_ADDR)
141/* This routine should be valid for all Au1x based boards */
142phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
143{
144	/* Don't fixup 36 bit addresses */
145	if ((phys_addr >> 32) != 0)
146		return phys_addr;
147
148#ifdef CONFIG_PCI
149	{
150		u32 start, end;
151
152		start = (u32)Au1500_PCI_MEM_START;
153		end = (u32)Au1500_PCI_MEM_END;
154		/* check for pci memory window */
155		if ((phys_addr >= start) && ((phys_addr + size) < end))
156			return (phys_t)
157			       ((phys_addr - start) + Au1500_PCI_MEM_START);
158	}
159#endif
160
161	/* All Au1x SOCs have a pcmcia controller */
162	/* We setup our 32 bit pseudo addresses to be equal to the
163	 * 36 bit addr >> 4, to make it easier to check the address
164	 * and fix it.
165	 * The Au1x socket 0 phys attribute address is 0xF 4000 0000.
166	 * The pseudo address we use is 0xF400 0000. Any address over
167	 * 0xF400 0000 is a pcmcia pseudo address.
168	 */
169	if ((phys_addr >= 0xF4000000) && (phys_addr < 0xFFFFFFFF)) {
170		return (phys_t)(phys_addr << 4);
171	}
172
173	/* default nop */
174	return phys_addr;
175}
176EXPORT_SYMBOL(__fixup_bigphys_addr);
177#endif
178