1/* 2 * BRIEF MODULE DESCRIPTION 3 * Au1xxx processor specific IRQ tables 4 * 5 * Copyright 2004 Embedded Edge, LLC 6 * dan@embeddededge.com 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 * 24 * You should have received a copy of the GNU General Public License along 25 * with this program; if not, write to the Free Software Foundation, Inc., 26 * 675 Mass Ave, Cambridge, MA 02139, USA. 27 */ 28#include <linux/errno.h> 29#include <linux/init.h> 30#include <linux/irq.h> 31#include <linux/kernel_stat.h> 32#include <linux/module.h> 33#include <linux/signal.h> 34#include <linux/sched.h> 35#include <linux/types.h> 36#include <linux/interrupt.h> 37#include <linux/ioport.h> 38#include <linux/timex.h> 39#include <linux/slab.h> 40#include <linux/random.h> 41#include <linux/delay.h> 42#include <linux/bitops.h> 43 44#include <asm/bootinfo.h> 45#include <asm/io.h> 46#include <asm/mipsregs.h> 47#include <asm/system.h> 48#include <asm/mach-au1x00/au1000.h> 49 50/* The IC0 interrupt table. This is processor, rather than 51 * board dependent, so no reason to keep this info in the board 52 * dependent files. 53 * 54 * Careful if you change match 2 request! 55 * The interrupt handler is called directly from the low level dispatch code. 56 */ 57au1xxx_irq_map_t __initdata au1xxx_ic0_map[] = { 58 59#if defined(CONFIG_SOC_AU1000) 60 { AU1000_UART0_INT, INTC_INT_HIGH_LEVEL, 0}, 61 { AU1000_UART1_INT, INTC_INT_HIGH_LEVEL, 0}, 62 { AU1000_UART2_INT, INTC_INT_HIGH_LEVEL, 0}, 63 { AU1000_UART3_INT, INTC_INT_HIGH_LEVEL, 0}, 64 { AU1000_SSI0_INT, INTC_INT_HIGH_LEVEL, 0}, 65 { AU1000_SSI1_INT, INTC_INT_HIGH_LEVEL, 0}, 66 { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0}, 67 { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0}, 68 { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0}, 69 { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0}, 70 { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0}, 71 { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0}, 72 { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0}, 73 { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0}, 74 { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, 75 { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, 76 { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, 77 { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, 78 { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 }, 79 { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, 80 { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, 81 { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, 82 { AU1000_IRDA_TX_INT, INTC_INT_HIGH_LEVEL, 0}, 83 { AU1000_IRDA_RX_INT, INTC_INT_HIGH_LEVEL, 0}, 84 { AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 }, 85 { AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 }, 86 { AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 }, 87 { AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 }, 88 { AU1000_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0}, 89 { AU1000_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0}, 90 { AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 }, 91 92#elif defined(CONFIG_SOC_AU1500) 93 94 { AU1500_UART0_INT, INTC_INT_HIGH_LEVEL, 0}, 95 { AU1000_PCI_INTA, INTC_INT_LOW_LEVEL, 0 }, 96 { AU1000_PCI_INTB, INTC_INT_LOW_LEVEL, 0 }, 97 { AU1500_UART3_INT, INTC_INT_HIGH_LEVEL, 0}, 98 { AU1000_PCI_INTC, INTC_INT_LOW_LEVEL, 0 }, 99 { AU1000_PCI_INTD, INTC_INT_LOW_LEVEL, 0 }, 100 { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0}, 101 { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0}, 102 { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0}, 103 { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0}, 104 { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0}, 105 { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0}, 106 { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0}, 107 { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0}, 108 { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, 109 { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, 110 { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, 111 { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, 112 { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 }, 113 { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, 114 { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, 115 { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, 116 { AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 }, 117 { AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 }, 118 { AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 }, 119 { AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 }, 120 { AU1500_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0}, 121 { AU1500_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0}, 122 { AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 }, 123 124#elif defined(CONFIG_SOC_AU1100) 125 126 { AU1100_UART0_INT, INTC_INT_HIGH_LEVEL, 0}, 127 { AU1100_UART1_INT, INTC_INT_HIGH_LEVEL, 0}, 128 { AU1100_SD_INT, INTC_INT_HIGH_LEVEL, 0}, 129 { AU1100_UART3_INT, INTC_INT_HIGH_LEVEL, 0}, 130 { AU1000_SSI0_INT, INTC_INT_HIGH_LEVEL, 0}, 131 { AU1000_SSI1_INT, INTC_INT_HIGH_LEVEL, 0}, 132 { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0}, 133 { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0}, 134 { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0}, 135 { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0}, 136 { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0}, 137 { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0}, 138 { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0}, 139 { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0}, 140 { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, 141 { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, 142 { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, 143 { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, 144 { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 }, 145 { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, 146 { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, 147 { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, 148 { AU1000_IRDA_TX_INT, INTC_INT_HIGH_LEVEL, 0}, 149 { AU1000_IRDA_RX_INT, INTC_INT_HIGH_LEVEL, 0}, 150 { AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 }, 151 { AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 }, 152 { AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 }, 153 { AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 }, 154 { AU1100_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0}, 155 /*{ AU1000_GPIO215_208_INT, INTC_INT_HIGH_LEVEL, 0},*/ 156 { AU1100_LCD_INT, INTC_INT_HIGH_LEVEL, 0}, 157 { AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 }, 158 159#elif defined(CONFIG_SOC_AU1550) 160 161 { AU1550_UART0_INT, INTC_INT_HIGH_LEVEL, 0}, 162 { AU1550_PCI_INTA, INTC_INT_LOW_LEVEL, 0 }, 163 { AU1550_PCI_INTB, INTC_INT_LOW_LEVEL, 0 }, 164 { AU1550_DDMA_INT, INTC_INT_HIGH_LEVEL, 0}, 165 { AU1550_CRYPTO_INT, INTC_INT_HIGH_LEVEL, 0}, 166 { AU1550_PCI_INTC, INTC_INT_LOW_LEVEL, 0 }, 167 { AU1550_PCI_INTD, INTC_INT_LOW_LEVEL, 0 }, 168 { AU1550_PCI_RST_INT, INTC_INT_LOW_LEVEL, 0 }, 169 { AU1550_UART1_INT, INTC_INT_HIGH_LEVEL, 0}, 170 { AU1550_UART3_INT, INTC_INT_HIGH_LEVEL, 0}, 171 { AU1550_PSC0_INT, INTC_INT_HIGH_LEVEL, 0}, 172 { AU1550_PSC1_INT, INTC_INT_HIGH_LEVEL, 0}, 173 { AU1550_PSC2_INT, INTC_INT_HIGH_LEVEL, 0}, 174 { AU1550_PSC3_INT, INTC_INT_HIGH_LEVEL, 0}, 175 { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, 176 { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, 177 { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, 178 { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, 179 { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 }, 180 { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, 181 { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, 182 { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, 183 { AU1550_NAND_INT, INTC_INT_RISE_EDGE, 0}, 184 { AU1550_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 }, 185 { AU1550_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 }, 186 { AU1550_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 }, 187 { AU1550_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0}, 188 { AU1550_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0}, 189 190#elif defined(CONFIG_SOC_AU1200) 191 192 { AU1200_UART0_INT, INTC_INT_HIGH_LEVEL, 0}, 193 { AU1200_SWT_INT, INTC_INT_RISE_EDGE, 0 }, 194 { AU1200_SD_INT, INTC_INT_HIGH_LEVEL, 0}, 195 { AU1200_DDMA_INT, INTC_INT_HIGH_LEVEL, 0}, 196 { AU1200_MAE_BE_INT, INTC_INT_HIGH_LEVEL, 0 }, 197 { AU1200_UART1_INT, INTC_INT_HIGH_LEVEL, 0}, 198 { AU1200_MAE_FE_INT, INTC_INT_HIGH_LEVEL, 0 }, 199 { AU1200_PSC0_INT, INTC_INT_HIGH_LEVEL, 0}, 200 { AU1200_PSC1_INT, INTC_INT_HIGH_LEVEL, 0}, 201 { AU1200_AES_INT, INTC_INT_HIGH_LEVEL, 0}, 202 { AU1200_CAMERA_INT, INTC_INT_HIGH_LEVEL, 0}, 203 { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, 204 { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, 205 { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, 206 { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, 207 { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 }, 208 { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, 209 { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, 210 { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, 211 { AU1200_NAND_INT, INTC_INT_RISE_EDGE, 0}, 212 { AU1200_USB_INT, INTC_INT_HIGH_LEVEL, 0 }, 213 { AU1200_LCD_INT, INTC_INT_HIGH_LEVEL, 0}, 214 { AU1200_MAE_BOTH_INT, INTC_INT_HIGH_LEVEL, 0}, 215 216#else 217#error "Error: Unknown Alchemy SOC" 218#endif 219 220}; 221 222int __initdata au1xxx_ic0_nr_irqs = ARRAY_SIZE(au1xxx_ic0_map); 223