1/* 2 * arch/ia64/kernel/ivt.S 3 * 4 * Copyright (C) 1998-2001, 2003, 2005 Hewlett-Packard Co 5 * Stephane Eranian <eranian@hpl.hp.com> 6 * David Mosberger <davidm@hpl.hp.com> 7 * Copyright (C) 2000, 2002-2003 Intel Co 8 * Asit Mallick <asit.k.mallick@intel.com> 9 * Suresh Siddha <suresh.b.siddha@intel.com> 10 * Kenneth Chen <kenneth.w.chen@intel.com> 11 * Fenghua Yu <fenghua.yu@intel.com> 12 * 13 * 00/08/23 Asit Mallick <asit.k.mallick@intel.com> TLB handling for SMP 14 * 00/12/20 David Mosberger-Tang <davidm@hpl.hp.com> DTLB/ITLB handler now uses virtual PT. 15 */ 16/* 17 * This file defines the interruption vector table used by the CPU. 18 * It does not include one entry per possible cause of interruption. 19 * 20 * The first 20 entries of the table contain 64 bundles each while the 21 * remaining 48 entries contain only 16 bundles each. 22 * 23 * The 64 bundles are used to allow inlining the whole handler for critical 24 * interruptions like TLB misses. 25 * 26 * For each entry, the comment is as follows: 27 * 28 * // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51) 29 * entry offset ----/ / / / / 30 * entry number ---------/ / / / 31 * size of the entry -------------/ / / 32 * vector name -------------------------------------/ / 33 * interruptions triggering this vector ----------------------/ 34 * 35 * The table is 32KB in size and must be aligned on 32KB boundary. 36 * (The CPU ignores the 15 lower bits of the address) 37 * 38 * Table is based upon EAS2.6 (Oct 1999) 39 */ 40 41 42#include <asm/asmmacro.h> 43#include <asm/break.h> 44#include <asm/ia32.h> 45#include <asm/kregs.h> 46#include <asm/asm-offsets.h> 47#include <asm/pgtable.h> 48#include <asm/processor.h> 49#include <asm/ptrace.h> 50#include <asm/system.h> 51#include <asm/thread_info.h> 52#include <asm/unistd.h> 53#include <asm/errno.h> 54 55# define PSR_DEFAULT_BITS psr.ac 56 57# define DBG_FAULT(i) 58 59#include "minstate.h" 60 61#define FAULT(n) \ 62 mov r31=pr; \ 63 mov r19=n;; /* prepare to save predicates */ \ 64 br.sptk.many dispatch_to_fault_handler 65 66 .section .text.ivt,"ax" 67 68 .align 32768 // align on 32KB boundary 69 .global ia64_ivt 70ia64_ivt: 71///////////////////////////////////////////////////////////////////////////////////////// 72// 0x0000 Entry 0 (size 64 bundles) VHPT Translation (8,20,47) 73ENTRY(vhpt_miss) 74 DBG_FAULT(0) 75 /* 76 * The VHPT vector is invoked when the TLB entry for the virtual page table 77 * is missing. This happens only as a result of a previous 78 * (the "original") TLB miss, which may either be caused by an instruction 79 * fetch or a data access (or non-access). 80 * 81 * What we do here is normal TLB miss handing for the _original_ miss, 82 * followed by inserting the TLB entry for the virtual page table page 83 * that the VHPT walker was attempting to access. The latter gets 84 * inserted as long as page table entry above pte level have valid 85 * mappings for the faulting address. The TLB entry for the original 86 * miss gets inserted only if the pte entry indicates that the page is 87 * present. 88 * 89 * do_page_fault gets invoked in the following cases: 90 * - the faulting virtual address uses unimplemented address bits 91 * - the faulting virtual address has no valid page table mapping 92 */ 93 mov r16=cr.ifa // get address that caused the TLB miss 94#ifdef CONFIG_HUGETLB_PAGE 95 movl r18=PAGE_SHIFT 96 mov r25=cr.itir 97#endif 98 ;; 99 rsm psr.dt // use physical addressing for data 100 mov r31=pr // save the predicate registers 101 mov r19=IA64_KR(PT_BASE) // get page table base address 102 shl r21=r16,3 // shift bit 60 into sign bit 103 shr.u r17=r16,61 // get the region number into r17 104 ;; 105 shr.u r22=r21,3 106#ifdef CONFIG_HUGETLB_PAGE 107 extr.u r26=r25,2,6 108 ;; 109 cmp.ne p8,p0=r18,r26 110 sub r27=r26,r18 111 ;; 112(p8) dep r25=r18,r25,2,6 113(p8) shr r22=r22,r27 114#endif 115 ;; 116 cmp.eq p6,p7=5,r17 // is IFA pointing into to region 5? 117 shr.u r18=r22,PGDIR_SHIFT // get bottom portion of pgd index bit 118 ;; 119(p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place 120 121 srlz.d 122 LOAD_PHYSICAL(p6, r19, swapper_pg_dir) // region 5 is rooted at swapper_pg_dir 123 124 .pred.rel "mutex", p6, p7 125(p6) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT 126(p7) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT-3 127 ;; 128(p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=pgd_offset for region 5 129(p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=pgd_offset for region[0-4] 130 cmp.eq p7,p6=0,r21 // unused address bits all zeroes? 131#ifdef CONFIG_PGTABLE_4 132 shr.u r28=r22,PUD_SHIFT // shift pud index into position 133#else 134 shr.u r18=r22,PMD_SHIFT // shift pmd index into position 135#endif 136 ;; 137 ld8 r17=[r17] // get *pgd (may be 0) 138 ;; 139(p7) cmp.eq p6,p7=r17,r0 // was pgd_present(*pgd) == NULL? 140#ifdef CONFIG_PGTABLE_4 141 dep r28=r28,r17,3,(PAGE_SHIFT-3) // r28=pud_offset(pgd,addr) 142 ;; 143 shr.u r18=r22,PMD_SHIFT // shift pmd index into position 144(p7) ld8 r29=[r28] // get *pud (may be 0) 145 ;; 146(p7) cmp.eq.or.andcm p6,p7=r29,r0 // was pud_present(*pud) == NULL? 147 dep r17=r18,r29,3,(PAGE_SHIFT-3) // r17=pmd_offset(pud,addr) 148#else 149 dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=pmd_offset(pgd,addr) 150#endif 151 ;; 152(p7) ld8 r20=[r17] // get *pmd (may be 0) 153 shr.u r19=r22,PAGE_SHIFT // shift pte index into position 154 ;; 155(p7) cmp.eq.or.andcm p6,p7=r20,r0 // was pmd_present(*pmd) == NULL? 156 dep r21=r19,r20,3,(PAGE_SHIFT-3) // r21=pte_offset(pmd,addr) 157 ;; 158(p7) ld8 r18=[r21] // read *pte 159 mov r19=cr.isr // cr.isr bit 32 tells us if this is an insn miss 160 ;; 161(p7) tbit.z p6,p7=r18,_PAGE_P_BIT // page present bit cleared? 162 mov r22=cr.iha // get the VHPT address that caused the TLB miss 163 ;; // avoid RAW on p7 164(p7) tbit.nz.unc p10,p11=r19,32 // is it an instruction TLB miss? 165 dep r23=0,r20,0,PAGE_SHIFT // clear low bits to get page address 166 ;; 167(p10) itc.i r18 // insert the instruction TLB entry 168(p11) itc.d r18 // insert the data TLB entry 169(p6) br.cond.spnt.many page_fault // handle bad address/page not present (page fault) 170 mov cr.ifa=r22 171 172#ifdef CONFIG_HUGETLB_PAGE 173(p8) mov cr.itir=r25 // change to default page-size for VHPT 174#endif 175 176 /* 177 * Now compute and insert the TLB entry for the virtual page table. We never 178 * execute in a page table page so there is no need to set the exception deferral 179 * bit. 180 */ 181 adds r24=__DIRTY_BITS_NO_ED|_PAGE_PL_0|_PAGE_AR_RW,r23 182 ;; 183(p7) itc.d r24 184 ;; 185#ifdef CONFIG_SMP 186 /* 187 * Tell the assemblers dependency-violation checker that the above "itc" instructions 188 * cannot possibly affect the following loads: 189 */ 190 dv_serialize_data 191 192 /* 193 * Re-check pagetable entry. If they changed, we may have received a ptc.g 194 * between reading the pagetable and the "itc". If so, flush the entry we 195 * inserted and retry. At this point, we have: 196 * 197 * r28 = equivalent of pud_offset(pgd, ifa) 198 * r17 = equivalent of pmd_offset(pud, ifa) 199 * r21 = equivalent of pte_offset(pmd, ifa) 200 * 201 * r29 = *pud 202 * r20 = *pmd 203 * r18 = *pte 204 */ 205 ld8 r25=[r21] // read *pte again 206 ld8 r26=[r17] // read *pmd again 207#ifdef CONFIG_PGTABLE_4 208 ld8 r19=[r28] // read *pud again 209#endif 210 cmp.ne p6,p7=r0,r0 211 ;; 212 cmp.ne.or.andcm p6,p7=r26,r20 // did *pmd change 213#ifdef CONFIG_PGTABLE_4 214 cmp.ne.or.andcm p6,p7=r19,r29 // did *pud change 215#endif 216 mov r27=PAGE_SHIFT<<2 217 ;; 218(p6) ptc.l r22,r27 // purge PTE page translation 219(p7) cmp.ne.or.andcm p6,p7=r25,r18 // did *pte change 220 ;; 221(p6) ptc.l r16,r27 // purge translation 222#endif 223 224 mov pr=r31,-1 // restore predicate registers 225 rfi 226END(vhpt_miss) 227 228 .org ia64_ivt+0x400 229///////////////////////////////////////////////////////////////////////////////////////// 230// 0x0400 Entry 1 (size 64 bundles) ITLB (21) 231ENTRY(itlb_miss) 232 DBG_FAULT(1) 233 /* 234 * The ITLB handler accesses the PTE via the virtually mapped linear 235 * page table. If a nested TLB miss occurs, we switch into physical 236 * mode, walk the page table, and then re-execute the PTE read and 237 * go on normally after that. 238 */ 239 mov r16=cr.ifa // get virtual address 240 mov r29=b0 // save b0 241 mov r31=pr // save predicates 242.itlb_fault: 243 mov r17=cr.iha // get virtual address of PTE 244 movl r30=1f // load nested fault continuation point 245 ;; 2461: ld8 r18=[r17] // read *pte 247 ;; 248 mov b0=r29 249 tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared? 250(p6) br.cond.spnt page_fault 251 ;; 252 itc.i r18 253 ;; 254#ifdef CONFIG_SMP 255 /* 256 * Tell the assemblers dependency-violation checker that the above "itc" instructions 257 * cannot possibly affect the following loads: 258 */ 259 dv_serialize_data 260 261 ld8 r19=[r17] // read *pte again and see if same 262 mov r20=PAGE_SHIFT<<2 // setup page size for purge 263 ;; 264 cmp.ne p7,p0=r18,r19 265 ;; 266(p7) ptc.l r16,r20 267#endif 268 mov pr=r31,-1 269 rfi 270END(itlb_miss) 271 272 .org ia64_ivt+0x0800 273///////////////////////////////////////////////////////////////////////////////////////// 274// 0x0800 Entry 2 (size 64 bundles) DTLB (9,48) 275ENTRY(dtlb_miss) 276 DBG_FAULT(2) 277 /* 278 * The DTLB handler accesses the PTE via the virtually mapped linear 279 * page table. If a nested TLB miss occurs, we switch into physical 280 * mode, walk the page table, and then re-execute the PTE read and 281 * go on normally after that. 282 */ 283 mov r16=cr.ifa // get virtual address 284 mov r29=b0 // save b0 285 mov r31=pr // save predicates 286dtlb_fault: 287 mov r17=cr.iha // get virtual address of PTE 288 movl r30=1f // load nested fault continuation point 289 ;; 2901: ld8 r18=[r17] // read *pte 291 ;; 292 mov b0=r29 293 tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared? 294(p6) br.cond.spnt page_fault 295 ;; 296 itc.d r18 297 ;; 298#ifdef CONFIG_SMP 299 /* 300 * Tell the assemblers dependency-violation checker that the above "itc" instructions 301 * cannot possibly affect the following loads: 302 */ 303 dv_serialize_data 304 305 ld8 r19=[r17] // read *pte again and see if same 306 mov r20=PAGE_SHIFT<<2 // setup page size for purge 307 ;; 308 cmp.ne p7,p0=r18,r19 309 ;; 310(p7) ptc.l r16,r20 311#endif 312 mov pr=r31,-1 313 rfi 314END(dtlb_miss) 315 316 .org ia64_ivt+0x0c00 317///////////////////////////////////////////////////////////////////////////////////////// 318// 0x0c00 Entry 3 (size 64 bundles) Alt ITLB (19) 319ENTRY(alt_itlb_miss) 320 DBG_FAULT(3) 321 mov r16=cr.ifa // get address that caused the TLB miss 322 movl r17=PAGE_KERNEL 323 mov r21=cr.ipsr 324 movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff) 325 mov r31=pr 326 ;; 327#ifdef CONFIG_DISABLE_VHPT 328 shr.u r22=r16,61 // get the region number into r21 329 ;; 330 cmp.gt p8,p0=6,r22 // user mode 331 ;; 332(p8) thash r17=r16 333 ;; 334(p8) mov cr.iha=r17 335(p8) mov r29=b0 // save b0 336(p8) br.cond.dptk .itlb_fault 337#endif 338 extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl 339 and r19=r19,r16 // clear ed, reserved bits, and PTE control bits 340 shr.u r18=r16,57 // move address bit 61 to bit 4 341 ;; 342 andcm r18=0x10,r18 // bit 4=~address-bit(61) 343 cmp.ne p8,p0=r0,r23 // psr.cpl != 0? 344 or r19=r17,r19 // insert PTE control bits into r19 345 ;; 346 or r19=r19,r18 // set bit 4 (uncached) if the access was to region 6 347(p8) br.cond.spnt page_fault 348 ;; 349 itc.i r19 // insert the TLB entry 350 mov pr=r31,-1 351 rfi 352END(alt_itlb_miss) 353 354 .org ia64_ivt+0x1000 355///////////////////////////////////////////////////////////////////////////////////////// 356// 0x1000 Entry 4 (size 64 bundles) Alt DTLB (7,46) 357ENTRY(alt_dtlb_miss) 358 DBG_FAULT(4) 359 mov r16=cr.ifa // get address that caused the TLB miss 360 movl r17=PAGE_KERNEL 361 mov r20=cr.isr 362 movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff) 363 mov r21=cr.ipsr 364 mov r31=pr 365 mov r24=PERCPU_ADDR 366 ;; 367#ifdef CONFIG_DISABLE_VHPT 368 shr.u r22=r16,61 // get the region number into r21 369 ;; 370 cmp.gt p8,p0=6,r22 // access to region 0-5 371 ;; 372(p8) thash r17=r16 373 ;; 374(p8) mov cr.iha=r17 375(p8) mov r29=b0 // save b0 376(p8) br.cond.dptk dtlb_fault 377#endif 378 cmp.ge p10,p11=r16,r24 // access to per_cpu_data? 379 tbit.z p12,p0=r16,61 // access to region 6? 380 mov r25=PERCPU_PAGE_SHIFT << 2 381 mov r26=PERCPU_PAGE_SIZE 382 nop.m 0 383 nop.b 0 384 ;; 385(p10) mov r19=IA64_KR(PER_CPU_DATA) 386(p11) and r19=r19,r16 // clear non-ppn fields 387 extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl 388 and r22=IA64_ISR_CODE_MASK,r20 // get the isr.code field 389 tbit.nz p6,p7=r20,IA64_ISR_SP_BIT // is speculation bit on? 390 tbit.nz p9,p0=r20,IA64_ISR_NA_BIT // is non-access bit on? 391 ;; 392(p10) sub r19=r19,r26 393(p10) mov cr.itir=r25 394 cmp.ne p8,p0=r0,r23 395(p9) cmp.eq.or.andcm p6,p7=IA64_ISR_CODE_LFETCH,r22 // check isr.code field 396(p12) dep r17=-1,r17,4,1 // set ma=UC for region 6 addr 397(p8) br.cond.spnt page_fault 398 399 dep r21=-1,r21,IA64_PSR_ED_BIT,1 400 ;; 401 or r19=r19,r17 // insert PTE control bits into r19 402(p6) mov cr.ipsr=r21 403 ;; 404(p7) itc.d r19 // insert the TLB entry 405 mov pr=r31,-1 406 rfi 407END(alt_dtlb_miss) 408 409 .org ia64_ivt+0x1400 410///////////////////////////////////////////////////////////////////////////////////////// 411// 0x1400 Entry 5 (size 64 bundles) Data nested TLB (6,45) 412ENTRY(nested_dtlb_miss) 413 /* 414 * In the absence of kernel bugs, we get here when the virtually mapped linear 415 * page table is accessed non-speculatively (e.g., in the Dirty-bit, Instruction 416 * Access-bit, or Data Access-bit faults). If the DTLB entry for the virtual page 417 * table is missing, a nested TLB miss fault is triggered and control is 418 * transferred to this point. When this happens, we lookup the pte for the 419 * faulting address by walking the page table in physical mode and return to the 420 * continuation point passed in register r30 (or call page_fault if the address is 421 * not mapped). 422 * 423 * Input: r16: faulting address 424 * r29: saved b0 425 * r30: continuation address 426 * r31: saved pr 427 * 428 * Output: r17: physical address of PTE of faulting address 429 * r29: saved b0 430 * r30: continuation address 431 * r31: saved pr 432 * 433 * Clobbered: b0, r18, r19, r21, r22, psr.dt (cleared) 434 */ 435 rsm psr.dt // switch to using physical data addressing 436 mov r19=IA64_KR(PT_BASE) // get the page table base address 437 shl r21=r16,3 // shift bit 60 into sign bit 438 mov r18=cr.itir 439 ;; 440 shr.u r17=r16,61 // get the region number into r17 441 extr.u r18=r18,2,6 // get the faulting page size 442 ;; 443 cmp.eq p6,p7=5,r17 // is faulting address in region 5? 444 add r22=-PAGE_SHIFT,r18 // adjustment for hugetlb address 445 add r18=PGDIR_SHIFT-PAGE_SHIFT,r18 446 ;; 447 shr.u r22=r16,r22 448 shr.u r18=r16,r18 449(p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place 450 451 srlz.d 452 LOAD_PHYSICAL(p6, r19, swapper_pg_dir) // region 5 is rooted at swapper_pg_dir 453 454 .pred.rel "mutex", p6, p7 455(p6) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT 456(p7) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT-3 457 ;; 458(p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=pgd_offset for region 5 459(p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=pgd_offset for region[0-4] 460 cmp.eq p7,p6=0,r21 // unused address bits all zeroes? 461#ifdef CONFIG_PGTABLE_4 462 shr.u r18=r22,PUD_SHIFT // shift pud index into position 463#else 464 shr.u r18=r22,PMD_SHIFT // shift pmd index into position 465#endif 466 ;; 467 ld8 r17=[r17] // get *pgd (may be 0) 468 ;; 469(p7) cmp.eq p6,p7=r17,r0 // was pgd_present(*pgd) == NULL? 470 dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=p[u|m]d_offset(pgd,addr) 471 ;; 472#ifdef CONFIG_PGTABLE_4 473(p7) ld8 r17=[r17] // get *pud (may be 0) 474 shr.u r18=r22,PMD_SHIFT // shift pmd index into position 475 ;; 476(p7) cmp.eq.or.andcm p6,p7=r17,r0 // was pud_present(*pud) == NULL? 477 dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=pmd_offset(pud,addr) 478 ;; 479#endif 480(p7) ld8 r17=[r17] // get *pmd (may be 0) 481 shr.u r19=r22,PAGE_SHIFT // shift pte index into position 482 ;; 483(p7) cmp.eq.or.andcm p6,p7=r17,r0 // was pmd_present(*pmd) == NULL? 484 dep r17=r19,r17,3,(PAGE_SHIFT-3) // r17=pte_offset(pmd,addr); 485(p6) br.cond.spnt page_fault 486 mov b0=r30 487 br.sptk.many b0 // return to continuation point 488END(nested_dtlb_miss) 489 490 .org ia64_ivt+0x1800 491///////////////////////////////////////////////////////////////////////////////////////// 492// 0x1800 Entry 6 (size 64 bundles) Instruction Key Miss (24) 493ENTRY(ikey_miss) 494 DBG_FAULT(6) 495 FAULT(6) 496END(ikey_miss) 497 498 //----------------------------------------------------------------------------------- 499 // call do_page_fault (predicates are in r31, psr.dt may be off, r16 is faulting address) 500ENTRY(page_fault) 501 ssm psr.dt 502 ;; 503 srlz.i 504 ;; 505 SAVE_MIN_WITH_COVER 506 alloc r15=ar.pfs,0,0,3,0 507 mov out0=cr.ifa 508 mov out1=cr.isr 509 adds r3=8,r2 // set up second base pointer 510 ;; 511 ssm psr.ic | PSR_DEFAULT_BITS 512 ;; 513 srlz.i // guarantee that interruption collectin is on 514 ;; 515(p15) ssm psr.i // restore psr.i 516 movl r14=ia64_leave_kernel 517 ;; 518 SAVE_REST 519 mov rp=r14 520 ;; 521 adds out2=16,r12 // out2 = pointer to pt_regs 522 br.call.sptk.many b6=ia64_do_page_fault // ignore return address 523END(page_fault) 524 525 .org ia64_ivt+0x1c00 526///////////////////////////////////////////////////////////////////////////////////////// 527// 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51) 528ENTRY(dkey_miss) 529 DBG_FAULT(7) 530 FAULT(7) 531END(dkey_miss) 532 533 .org ia64_ivt+0x2000 534///////////////////////////////////////////////////////////////////////////////////////// 535// 0x2000 Entry 8 (size 64 bundles) Dirty-bit (54) 536ENTRY(dirty_bit) 537 DBG_FAULT(8) 538 /* 539 * What we do here is to simply turn on the dirty bit in the PTE. We need to 540 * update both the page-table and the TLB entry. To efficiently access the PTE, 541 * we address it through the virtual page table. Most likely, the TLB entry for 542 * the relevant virtual page table page is still present in the TLB so we can 543 * normally do this without additional TLB misses. In case the necessary virtual 544 * page table TLB entry isn't present, we take a nested TLB miss hit where we look 545 * up the physical address of the L3 PTE and then continue at label 1 below. 546 */ 547 mov r16=cr.ifa // get the address that caused the fault 548 movl r30=1f // load continuation point in case of nested fault 549 ;; 550 thash r17=r16 // compute virtual address of L3 PTE 551 mov r29=b0 // save b0 in case of nested fault 552 mov r31=pr // save pr 553#ifdef CONFIG_SMP 554 mov r28=ar.ccv // save ar.ccv 555 ;; 5561: ld8 r18=[r17] 557 ;; // avoid RAW on r18 558 mov ar.ccv=r18 // set compare value for cmpxchg 559 or r25=_PAGE_D|_PAGE_A,r18 // set the dirty and accessed bits 560 tbit.z p7,p6 = r18,_PAGE_P_BIT // Check present bit 561 ;; 562(p6) cmpxchg8.acq r26=[r17],r25,ar.ccv // Only update if page is present 563 mov r24=PAGE_SHIFT<<2 564 ;; 565(p6) cmp.eq p6,p7=r26,r18 // Only compare if page is present 566 ;; 567(p6) itc.d r25 // install updated PTE 568 ;; 569 /* 570 * Tell the assemblers dependency-violation checker that the above "itc" instructions 571 * cannot possibly affect the following loads: 572 */ 573 dv_serialize_data 574 575 ld8 r18=[r17] // read PTE again 576 ;; 577 cmp.eq p6,p7=r18,r25 // is it same as the newly installed 578 ;; 579(p7) ptc.l r16,r24 580 mov b0=r29 // restore b0 581 mov ar.ccv=r28 582#else 583 ;; 5841: ld8 r18=[r17] 585 ;; // avoid RAW on r18 586 or r18=_PAGE_D|_PAGE_A,r18 // set the dirty and accessed bits 587 mov b0=r29 // restore b0 588 ;; 589 st8 [r17]=r18 // store back updated PTE 590 itc.d r18 // install updated PTE 591#endif 592 mov pr=r31,-1 // restore pr 593 rfi 594END(dirty_bit) 595 596 .org ia64_ivt+0x2400 597///////////////////////////////////////////////////////////////////////////////////////// 598// 0x2400 Entry 9 (size 64 bundles) Instruction Access-bit (27) 599ENTRY(iaccess_bit) 600 DBG_FAULT(9) 601 // Like Entry 8, except for instruction access 602 mov r16=cr.ifa // get the address that caused the fault 603 movl r30=1f // load continuation point in case of nested fault 604 mov r31=pr // save predicates 605#ifdef CONFIG_ITANIUM 606 /* 607 * Erratum 10 (IFA may contain incorrect address) has "NoFix" status. 608 */ 609 mov r17=cr.ipsr 610 ;; 611 mov r18=cr.iip 612 tbit.z p6,p0=r17,IA64_PSR_IS_BIT // IA64 instruction set? 613 ;; 614(p6) mov r16=r18 // if so, use cr.iip instead of cr.ifa 615#endif /* CONFIG_ITANIUM */ 616 ;; 617 thash r17=r16 // compute virtual address of L3 PTE 618 mov r29=b0 // save b0 in case of nested fault) 619#ifdef CONFIG_SMP 620 mov r28=ar.ccv // save ar.ccv 621 ;; 6221: ld8 r18=[r17] 623 ;; 624 mov ar.ccv=r18 // set compare value for cmpxchg 625 or r25=_PAGE_A,r18 // set the accessed bit 626 tbit.z p7,p6 = r18,_PAGE_P_BIT // Check present bit 627 ;; 628(p6) cmpxchg8.acq r26=[r17],r25,ar.ccv // Only if page present 629 mov r24=PAGE_SHIFT<<2 630 ;; 631(p6) cmp.eq p6,p7=r26,r18 // Only if page present 632 ;; 633(p6) itc.i r25 // install updated PTE 634 ;; 635 /* 636 * Tell the assemblers dependency-violation checker that the above "itc" instructions 637 * cannot possibly affect the following loads: 638 */ 639 dv_serialize_data 640 641 ld8 r18=[r17] // read PTE again 642 ;; 643 cmp.eq p6,p7=r18,r25 // is it same as the newly installed 644 ;; 645(p7) ptc.l r16,r24 646 mov b0=r29 // restore b0 647 mov ar.ccv=r28 648#else /* !CONFIG_SMP */ 649 ;; 6501: ld8 r18=[r17] 651 ;; 652 or r18=_PAGE_A,r18 // set the accessed bit 653 mov b0=r29 // restore b0 654 ;; 655 st8 [r17]=r18 // store back updated PTE 656 itc.i r18 // install updated PTE 657#endif /* !CONFIG_SMP */ 658 mov pr=r31,-1 659 rfi 660END(iaccess_bit) 661 662 .org ia64_ivt+0x2800 663///////////////////////////////////////////////////////////////////////////////////////// 664// 0x2800 Entry 10 (size 64 bundles) Data Access-bit (15,55) 665ENTRY(daccess_bit) 666 DBG_FAULT(10) 667 // Like Entry 8, except for data access 668 mov r16=cr.ifa // get the address that caused the fault 669 movl r30=1f // load continuation point in case of nested fault 670 ;; 671 thash r17=r16 // compute virtual address of L3 PTE 672 mov r31=pr 673 mov r29=b0 // save b0 in case of nested fault) 674#ifdef CONFIG_SMP 675 mov r28=ar.ccv // save ar.ccv 676 ;; 6771: ld8 r18=[r17] 678 ;; // avoid RAW on r18 679 mov ar.ccv=r18 // set compare value for cmpxchg 680 or r25=_PAGE_A,r18 // set the dirty bit 681 tbit.z p7,p6 = r18,_PAGE_P_BIT // Check present bit 682 ;; 683(p6) cmpxchg8.acq r26=[r17],r25,ar.ccv // Only if page is present 684 mov r24=PAGE_SHIFT<<2 685 ;; 686(p6) cmp.eq p6,p7=r26,r18 // Only if page is present 687 ;; 688(p6) itc.d r25 // install updated PTE 689 /* 690 * Tell the assemblers dependency-violation checker that the above "itc" instructions 691 * cannot possibly affect the following loads: 692 */ 693 dv_serialize_data 694 ;; 695 ld8 r18=[r17] // read PTE again 696 ;; 697 cmp.eq p6,p7=r18,r25 // is it same as the newly installed 698 ;; 699(p7) ptc.l r16,r24 700 mov ar.ccv=r28 701#else 702 ;; 7031: ld8 r18=[r17] 704 ;; // avoid RAW on r18 705 or r18=_PAGE_A,r18 // set the accessed bit 706 ;; 707 st8 [r17]=r18 // store back updated PTE 708 itc.d r18 // install updated PTE 709#endif 710 mov b0=r29 // restore b0 711 mov pr=r31,-1 712 rfi 713END(daccess_bit) 714 715 .org ia64_ivt+0x2c00 716///////////////////////////////////////////////////////////////////////////////////////// 717// 0x2c00 Entry 11 (size 64 bundles) Break instruction (33) 718ENTRY(break_fault) 719 /* 720 * The streamlined system call entry/exit paths only save/restore the initial part 721 * of pt_regs. This implies that the callers of system-calls must adhere to the 722 * normal procedure calling conventions. 723 * 724 * Registers to be saved & restored: 725 * CR registers: cr.ipsr, cr.iip, cr.ifs 726 * AR registers: ar.unat, ar.pfs, ar.rsc, ar.rnat, ar.bspstore, ar.fpsr 727 * others: pr, b0, b6, loadrs, r1, r11, r12, r13, r15 728 * Registers to be restored only: 729 * r8-r11: output value from the system call. 730 * 731 * During system call exit, scratch registers (including r15) are modified/cleared 732 * to prevent leaking bits from kernel to user level. 733 */ 734 DBG_FAULT(11) 735 mov.m r16=IA64_KR(CURRENT) // M2 r16 <- current task (12 cyc) 736 mov r29=cr.ipsr // M2 (12 cyc) 737 mov r31=pr // I0 (2 cyc) 738 739 mov r17=cr.iim // M2 (2 cyc) 740 mov.m r27=ar.rsc // M2 (12 cyc) 741 mov r18=__IA64_BREAK_SYSCALL // A 742 743 mov.m ar.rsc=0 // M2 744 mov.m r21=ar.fpsr // M2 (12 cyc) 745 mov r19=b6 // I0 (2 cyc) 746 ;; 747 mov.m r23=ar.bspstore // M2 (12 cyc) 748 mov.m r24=ar.rnat // M2 (5 cyc) 749 mov.i r26=ar.pfs // I0 (2 cyc) 750 751 invala // M0|1 752 nop.m 0 // M 753 mov r20=r1 // A save r1 754 755 nop.m 0 756 movl r30=sys_call_table // X 757 758 mov r28=cr.iip // M2 (2 cyc) 759 cmp.eq p0,p7=r18,r17 // I0 is this a system call? 760(p7) br.cond.spnt non_syscall // B no -> 761 // 762 // From this point on, we are definitely on the syscall-path 763 // and we can use (non-banked) scratch registers. 764 // 765/////////////////////////////////////////////////////////////////////// 766 mov r1=r16 // A move task-pointer to "addl"-addressable reg 767 mov r2=r16 // A setup r2 for ia64_syscall_setup 768 add r9=TI_FLAGS+IA64_TASK_SIZE,r16 // A r9 = ¤t_thread_info()->flags 769 770 adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16 771 adds r15=-1024,r15 // A subtract 1024 from syscall number 772 mov r3=NR_syscalls - 1 773 ;; 774 ld1.bias r17=[r16] // M0|1 r17 = current->thread.on_ustack flag 775 ld4 r9=[r9] // M0|1 r9 = current_thread_info()->flags 776 extr.u r8=r29,41,2 // I0 extract ei field from cr.ipsr 777 778 shladd r30=r15,3,r30 // A r30 = sys_call_table + 8*(syscall-1024) 779 addl r22=IA64_RBS_OFFSET,r1 // A compute base of RBS 780 cmp.leu p6,p7=r15,r3 // A syscall number in range? 781 ;; 782 783 lfetch.fault.excl.nt1 [r22] // M0|1 prefetch RBS 784(p6) ld8 r30=[r30] // M0|1 load address of syscall entry point 785 tnat.nz.or p7,p0=r15 // I0 is syscall nr a NaT? 786 787 mov.m ar.bspstore=r22 // M2 switch to kernel RBS 788 cmp.eq p8,p9=2,r8 // A isr.ei==2? 789 ;; 790 791(p8) mov r8=0 // A clear ei to 0 792(p7) movl r30=sys_ni_syscall // X 793 794(p8) adds r28=16,r28 // A switch cr.iip to next bundle 795(p9) adds r8=1,r8 // A increment ei to next slot 796 nop.i 0 797 ;; 798 799 mov.m r25=ar.unat // M2 (5 cyc) 800 dep r29=r8,r29,41,2 // I0 insert new ei into cr.ipsr 801 adds r15=1024,r15 // A restore original syscall number 802 // 803 // If any of the above loads miss in L1D, we'll stall here until 804 // the data arrives. 805 // 806/////////////////////////////////////////////////////////////////////// 807 st1 [r16]=r0 // M2|3 clear current->thread.on_ustack flag 808 mov b6=r30 // I0 setup syscall handler branch reg early 809 cmp.eq pKStk,pUStk=r0,r17 // A were we on kernel stacks already? 810 811 and r9=_TIF_SYSCALL_TRACEAUDIT,r9 // A mask trace or audit 812 mov r18=ar.bsp // M2 (12 cyc) 813(pKStk) br.cond.spnt .break_fixup // B we're already in kernel-mode -- fix up RBS 814 ;; 815.back_from_break_fixup: 816(pUStk) addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r1 // A compute base of memory stack 817 cmp.eq p14,p0=r9,r0 // A are syscalls being traced/audited? 818 br.call.sptk.many b7=ia64_syscall_setup // B 8191: 820 mov ar.rsc=0x3 // M2 set eager mode, pl 0, LE, loadrs=0 821 nop 0 822 bsw.1 // B (6 cyc) regs are saved, switch to bank 1 823 ;; 824 825 ssm psr.ic | PSR_DEFAULT_BITS // M2 now it's safe to re-enable intr.-collection 826 movl r3=ia64_ret_from_syscall // X 827 ;; 828 829 srlz.i // M0 ensure interruption collection is on 830 mov rp=r3 // I0 set the real return addr 831(p10) br.cond.spnt.many ia64_ret_from_syscall // B return if bad call-frame or r15 is a NaT 832 833(p15) ssm psr.i // M2 restore psr.i 834(p14) br.call.sptk.many b6=b6 // B invoke syscall-handker (ignore return addr) 835 br.cond.spnt.many ia64_trace_syscall // B do syscall-tracing thingamagic 836 // NOT REACHED 837/////////////////////////////////////////////////////////////////////// 838 // On entry, we optimistically assumed that we're coming from user-space. 839 // For the rare cases where a system-call is done from within the kernel, 840 // we fix things up at this point: 841.break_fixup: 842 add r1=-IA64_PT_REGS_SIZE,sp // A allocate space for pt_regs structure 843 mov ar.rnat=r24 // M2 restore kernel's AR.RNAT 844 ;; 845 mov ar.bspstore=r23 // M2 restore kernel's AR.BSPSTORE 846 br.cond.sptk .back_from_break_fixup 847END(break_fault) 848 849 .org ia64_ivt+0x3000 850///////////////////////////////////////////////////////////////////////////////////////// 851// 0x3000 Entry 12 (size 64 bundles) External Interrupt (4) 852ENTRY(interrupt) 853 DBG_FAULT(12) 854 mov r31=pr // prepare to save predicates 855 ;; 856 SAVE_MIN_WITH_COVER // uses r31; defines r2 and r3 857 ssm psr.ic | PSR_DEFAULT_BITS 858 ;; 859 adds r3=8,r2 // set up second base pointer for SAVE_REST 860 srlz.i // ensure everybody knows psr.ic is back on 861 ;; 862 SAVE_REST 863 ;; 864 MCA_RECOVER_RANGE(interrupt) 865 alloc r14=ar.pfs,0,0,2,0 // must be first in an insn group 866 mov out0=cr.ivr // pass cr.ivr as first arg 867 add out1=16,sp // pass pointer to pt_regs as second arg 868 ;; 869 srlz.d // make sure we see the effect of cr.ivr 870 movl r14=ia64_leave_kernel 871 ;; 872 mov rp=r14 873 br.call.sptk.many b6=ia64_handle_irq 874END(interrupt) 875 876 .org ia64_ivt+0x3400 877///////////////////////////////////////////////////////////////////////////////////////// 878// 0x3400 Entry 13 (size 64 bundles) Reserved 879 DBG_FAULT(13) 880 FAULT(13) 881 882 .org ia64_ivt+0x3800 883///////////////////////////////////////////////////////////////////////////////////////// 884// 0x3800 Entry 14 (size 64 bundles) Reserved 885 DBG_FAULT(14) 886 FAULT(14) 887 888 /* 889 * There is no particular reason for this code to be here, other than that 890 * there happens to be space here that would go unused otherwise. If this 891 * fault ever gets "unreserved", simply moved the following code to a more 892 * suitable spot... 893 * 894 * ia64_syscall_setup() is a separate subroutine so that it can 895 * allocate stacked registers so it can safely demine any 896 * potential NaT values from the input registers. 897 * 898 * On entry: 899 * - executing on bank 0 or bank 1 register set (doesn't matter) 900 * - r1: stack pointer 901 * - r2: current task pointer 902 * - r3: preserved 903 * - r11: original contents (saved ar.pfs to be saved) 904 * - r12: original contents (sp to be saved) 905 * - r13: original contents (tp to be saved) 906 * - r15: original contents (syscall # to be saved) 907 * - r18: saved bsp (after switching to kernel stack) 908 * - r19: saved b6 909 * - r20: saved r1 (gp) 910 * - r21: saved ar.fpsr 911 * - r22: kernel's register backing store base (krbs_base) 912 * - r23: saved ar.bspstore 913 * - r24: saved ar.rnat 914 * - r25: saved ar.unat 915 * - r26: saved ar.pfs 916 * - r27: saved ar.rsc 917 * - r28: saved cr.iip 918 * - r29: saved cr.ipsr 919 * - r31: saved pr 920 * - b0: original contents (to be saved) 921 * On exit: 922 * - p10: TRUE if syscall is invoked with more than 8 out 923 * registers or r15's Nat is true 924 * - r1: kernel's gp 925 * - r3: preserved (same as on entry) 926 * - r8: -EINVAL if p10 is true 927 * - r12: points to kernel stack 928 * - r13: points to current task 929 * - r14: preserved (same as on entry) 930 * - p13: preserved 931 * - p15: TRUE if interrupts need to be re-enabled 932 * - ar.fpsr: set to kernel settings 933 * - b6: preserved (same as on entry) 934 */ 935GLOBAL_ENTRY(ia64_syscall_setup) 936#if PT(B6) != 0 937# error This code assumes that b6 is the first field in pt_regs. 938#endif 939 st8 [r1]=r19 // save b6 940 add r16=PT(CR_IPSR),r1 // initialize first base pointer 941 add r17=PT(R11),r1 // initialize second base pointer 942 ;; 943 alloc r19=ar.pfs,8,0,0,0 // ensure in0-in7 are writable 944 st8 [r16]=r29,PT(AR_PFS)-PT(CR_IPSR) // save cr.ipsr 945 tnat.nz p8,p0=in0 946 947 st8.spill [r17]=r11,PT(CR_IIP)-PT(R11) // save r11 948 tnat.nz p9,p0=in1 949(pKStk) mov r18=r0 // make sure r18 isn't NaT 950 ;; 951 952 st8 [r16]=r26,PT(CR_IFS)-PT(AR_PFS) // save ar.pfs 953 st8 [r17]=r28,PT(AR_UNAT)-PT(CR_IIP) // save cr.iip 954 mov r28=b0 // save b0 (2 cyc) 955 ;; 956 957 st8 [r17]=r25,PT(AR_RSC)-PT(AR_UNAT) // save ar.unat 958 dep r19=0,r19,38,26 // clear all bits but 0..37 [I0] 959(p8) mov in0=-1 960 ;; 961 962 st8 [r16]=r19,PT(AR_RNAT)-PT(CR_IFS) // store ar.pfs.pfm in cr.ifs 963 extr.u r11=r19,7,7 // I0 // get sol of ar.pfs 964 and r8=0x7f,r19 // A // get sof of ar.pfs 965 966 st8 [r17]=r27,PT(AR_BSPSTORE)-PT(AR_RSC)// save ar.rsc 967 tbit.nz p15,p0=r29,IA64_PSR_I_BIT // I0 968(p9) mov in1=-1 969 ;; 970 971(pUStk) sub r18=r18,r22 // r18=RSE.ndirty*8 972 tnat.nz p10,p0=in2 973 add r11=8,r11 974 ;; 975(pKStk) adds r16=PT(PR)-PT(AR_RNAT),r16 // skip over ar_rnat field 976(pKStk) adds r17=PT(B0)-PT(AR_BSPSTORE),r17 // skip over ar_bspstore field 977 tnat.nz p11,p0=in3 978 ;; 979(p10) mov in2=-1 980 tnat.nz p12,p0=in4 // [I0] 981(p11) mov in3=-1 982 ;; 983(pUStk) st8 [r16]=r24,PT(PR)-PT(AR_RNAT) // save ar.rnat 984(pUStk) st8 [r17]=r23,PT(B0)-PT(AR_BSPSTORE) // save ar.bspstore 985 shl r18=r18,16 // compute ar.rsc to be used for "loadrs" 986 ;; 987 st8 [r16]=r31,PT(LOADRS)-PT(PR) // save predicates 988 st8 [r17]=r28,PT(R1)-PT(B0) // save b0 989 tnat.nz p13,p0=in5 // [I0] 990 ;; 991 st8 [r16]=r18,PT(R12)-PT(LOADRS) // save ar.rsc value for "loadrs" 992 st8.spill [r17]=r20,PT(R13)-PT(R1) // save original r1 993(p12) mov in4=-1 994 ;; 995 996.mem.offset 0,0; st8.spill [r16]=r12,PT(AR_FPSR)-PT(R12) // save r12 997.mem.offset 8,0; st8.spill [r17]=r13,PT(R15)-PT(R13) // save r13 998(p13) mov in5=-1 999 ;; 1000 st8 [r16]=r21,PT(R8)-PT(AR_FPSR) // save ar.fpsr 1001 tnat.nz p13,p0=in6 1002 cmp.lt p10,p9=r11,r8 // frame size can't be more than local+8 1003 ;; 1004 mov r8=1 1005(p9) tnat.nz p10,p0=r15 1006 adds r12=-16,r1 // switch to kernel memory stack (with 16 bytes of scratch) 1007 1008 st8.spill [r17]=r15 // save r15 1009 tnat.nz p8,p0=in7 1010 nop.i 0 1011 1012 mov r13=r2 // establish `current' 1013 movl r1=__gp // establish kernel global pointer 1014 ;; 1015 st8 [r16]=r8 // ensure pt_regs.r8 != 0 (see handle_syscall_error) 1016(p13) mov in6=-1 1017(p8) mov in7=-1 1018 1019 cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0 1020 movl r17=FPSR_DEFAULT 1021 ;; 1022 mov.m ar.fpsr=r17 // set ar.fpsr to kernel default value 1023(p10) mov r8=-EINVAL 1024 br.ret.sptk.many b7 1025END(ia64_syscall_setup) 1026 1027 .org ia64_ivt+0x3c00 1028///////////////////////////////////////////////////////////////////////////////////////// 1029// 0x3c00 Entry 15 (size 64 bundles) Reserved 1030 DBG_FAULT(15) 1031 FAULT(15) 1032 1033 /* 1034 * Squatting in this space ... 1035 * 1036 * This special case dispatcher for illegal operation faults allows preserved 1037 * registers to be modified through a callback function (asm only) that is handed 1038 * back from the fault handler in r8. Up to three arguments can be passed to the 1039 * callback function by returning an aggregate with the callback as its first 1040 * element, followed by the arguments. 1041 */ 1042ENTRY(dispatch_illegal_op_fault) 1043 .prologue 1044 .body 1045 SAVE_MIN_WITH_COVER 1046 ssm psr.ic | PSR_DEFAULT_BITS 1047 ;; 1048 srlz.i // guarantee that interruption collection is on 1049 ;; 1050(p15) ssm psr.i // restore psr.i 1051 adds r3=8,r2 // set up second base pointer for SAVE_REST 1052 ;; 1053 alloc r14=ar.pfs,0,0,1,0 // must be first in insn group 1054 mov out0=ar.ec 1055 ;; 1056 SAVE_REST 1057 PT_REGS_UNWIND_INFO(0) 1058 ;; 1059 br.call.sptk.many rp=ia64_illegal_op_fault 1060.ret0: ;; 1061 alloc r14=ar.pfs,0,0,3,0 // must be first in insn group 1062 mov out0=r9 1063 mov out1=r10 1064 mov out2=r11 1065 movl r15=ia64_leave_kernel 1066 ;; 1067 mov rp=r15 1068 mov b6=r8 1069 ;; 1070 cmp.ne p6,p0=0,r8 1071(p6) br.call.dpnt.many b6=b6 // call returns to ia64_leave_kernel 1072 br.sptk.many ia64_leave_kernel 1073END(dispatch_illegal_op_fault) 1074 1075 .org ia64_ivt+0x4000 1076///////////////////////////////////////////////////////////////////////////////////////// 1077// 0x4000 Entry 16 (size 64 bundles) Reserved 1078 DBG_FAULT(16) 1079 FAULT(16) 1080 1081 .org ia64_ivt+0x4400 1082///////////////////////////////////////////////////////////////////////////////////////// 1083// 0x4400 Entry 17 (size 64 bundles) Reserved 1084 DBG_FAULT(17) 1085 FAULT(17) 1086 1087ENTRY(non_syscall) 1088 mov ar.rsc=r27 // restore ar.rsc before SAVE_MIN_WITH_COVER 1089 ;; 1090 SAVE_MIN_WITH_COVER 1091 1092 // There is no particular reason for this code to be here, other than that 1093 // there happens to be space here that would go unused otherwise. If this 1094 // fault ever gets "unreserved", simply moved the following code to a more 1095 // suitable spot... 1096 1097 alloc r14=ar.pfs,0,0,2,0 1098 mov out0=cr.iim 1099 add out1=16,sp 1100 adds r3=8,r2 // set up second base pointer for SAVE_REST 1101 1102 ssm psr.ic | PSR_DEFAULT_BITS 1103 ;; 1104 srlz.i // guarantee that interruption collection is on 1105 ;; 1106(p15) ssm psr.i // restore psr.i 1107 movl r15=ia64_leave_kernel 1108 ;; 1109 SAVE_REST 1110 mov rp=r15 1111 ;; 1112 br.call.sptk.many b6=ia64_bad_break // avoid WAW on CFM and ignore return addr 1113END(non_syscall) 1114 1115 .org ia64_ivt+0x4800 1116///////////////////////////////////////////////////////////////////////////////////////// 1117// 0x4800 Entry 18 (size 64 bundles) Reserved 1118 DBG_FAULT(18) 1119 FAULT(18) 1120 1121 /* 1122 * There is no particular reason for this code to be here, other than that 1123 * there happens to be space here that would go unused otherwise. If this 1124 * fault ever gets "unreserved", simply moved the following code to a more 1125 * suitable spot... 1126 */ 1127 1128ENTRY(dispatch_unaligned_handler) 1129 SAVE_MIN_WITH_COVER 1130 ;; 1131 alloc r14=ar.pfs,0,0,2,0 // now it's safe (must be first in insn group!) 1132 mov out0=cr.ifa 1133 adds out1=16,sp 1134 1135 ssm psr.ic | PSR_DEFAULT_BITS 1136 ;; 1137 srlz.i // guarantee that interruption collection is on 1138 ;; 1139(p15) ssm psr.i // restore psr.i 1140 adds r3=8,r2 // set up second base pointer 1141 ;; 1142 SAVE_REST 1143 movl r14=ia64_leave_kernel 1144 ;; 1145 mov rp=r14 1146 br.sptk.many ia64_prepare_handle_unaligned 1147END(dispatch_unaligned_handler) 1148 1149 .org ia64_ivt+0x4c00 1150///////////////////////////////////////////////////////////////////////////////////////// 1151// 0x4c00 Entry 19 (size 64 bundles) Reserved 1152 DBG_FAULT(19) 1153 FAULT(19) 1154 1155 /* 1156 * There is no particular reason for this code to be here, other than that 1157 * there happens to be space here that would go unused otherwise. If this 1158 * fault ever gets "unreserved", simply moved the following code to a more 1159 * suitable spot... 1160 */ 1161 1162ENTRY(dispatch_to_fault_handler) 1163 /* 1164 * Input: 1165 * psr.ic: off 1166 * r19: fault vector number (e.g., 24 for General Exception) 1167 * r31: contains saved predicates (pr) 1168 */ 1169 SAVE_MIN_WITH_COVER_R19 1170 alloc r14=ar.pfs,0,0,5,0 1171 mov out0=r15 1172 mov out1=cr.isr 1173 mov out2=cr.ifa 1174 mov out3=cr.iim 1175 mov out4=cr.itir 1176 ;; 1177 ssm psr.ic | PSR_DEFAULT_BITS 1178 ;; 1179 srlz.i // guarantee that interruption collection is on 1180 ;; 1181(p15) ssm psr.i // restore psr.i 1182 adds r3=8,r2 // set up second base pointer for SAVE_REST 1183 ;; 1184 SAVE_REST 1185 movl r14=ia64_leave_kernel 1186 ;; 1187 mov rp=r14 1188 br.call.sptk.many b6=ia64_fault 1189END(dispatch_to_fault_handler) 1190 1191// 1192// --- End of long entries, Beginning of short entries 1193// 1194 1195 .org ia64_ivt+0x5000 1196///////////////////////////////////////////////////////////////////////////////////////// 1197// 0x5000 Entry 20 (size 16 bundles) Page Not Present (10,22,49) 1198ENTRY(page_not_present) 1199 DBG_FAULT(20) 1200 mov r16=cr.ifa 1201 rsm psr.dt 1202 /* 1203 * The Linux page fault handler doesn't expect non-present pages to be in 1204 * the TLB. Flush the existing entry now, so we meet that expectation. 1205 */ 1206 mov r17=PAGE_SHIFT<<2 1207 ;; 1208 ptc.l r16,r17 1209 ;; 1210 mov r31=pr 1211 srlz.d 1212 br.sptk.many page_fault 1213END(page_not_present) 1214 1215 .org ia64_ivt+0x5100 1216///////////////////////////////////////////////////////////////////////////////////////// 1217// 0x5100 Entry 21 (size 16 bundles) Key Permission (13,25,52) 1218ENTRY(key_permission) 1219 DBG_FAULT(21) 1220 mov r16=cr.ifa 1221 rsm psr.dt 1222 mov r31=pr 1223 ;; 1224 srlz.d 1225 br.sptk.many page_fault 1226END(key_permission) 1227 1228 .org ia64_ivt+0x5200 1229///////////////////////////////////////////////////////////////////////////////////////// 1230// 0x5200 Entry 22 (size 16 bundles) Instruction Access Rights (26) 1231ENTRY(iaccess_rights) 1232 DBG_FAULT(22) 1233 mov r16=cr.ifa 1234 rsm psr.dt 1235 mov r31=pr 1236 ;; 1237 srlz.d 1238 br.sptk.many page_fault 1239END(iaccess_rights) 1240 1241 .org ia64_ivt+0x5300 1242///////////////////////////////////////////////////////////////////////////////////////// 1243// 0x5300 Entry 23 (size 16 bundles) Data Access Rights (14,53) 1244ENTRY(daccess_rights) 1245 DBG_FAULT(23) 1246 mov r16=cr.ifa 1247 rsm psr.dt 1248 mov r31=pr 1249 ;; 1250 srlz.d 1251 br.sptk.many page_fault 1252END(daccess_rights) 1253 1254 .org ia64_ivt+0x5400 1255///////////////////////////////////////////////////////////////////////////////////////// 1256// 0x5400 Entry 24 (size 16 bundles) General Exception (5,32,34,36,38,39) 1257ENTRY(general_exception) 1258 DBG_FAULT(24) 1259 mov r16=cr.isr 1260 mov r31=pr 1261 ;; 1262 cmp4.eq p6,p0=0,r16 1263(p6) br.sptk.many dispatch_illegal_op_fault 1264 ;; 1265 mov r19=24 // fault number 1266 br.sptk.many dispatch_to_fault_handler 1267END(general_exception) 1268 1269 .org ia64_ivt+0x5500 1270///////////////////////////////////////////////////////////////////////////////////////// 1271// 0x5500 Entry 25 (size 16 bundles) Disabled FP-Register (35) 1272ENTRY(disabled_fp_reg) 1273 DBG_FAULT(25) 1274 rsm psr.dfh // ensure we can access fph 1275 ;; 1276 srlz.d 1277 mov r31=pr 1278 mov r19=25 1279 br.sptk.many dispatch_to_fault_handler 1280END(disabled_fp_reg) 1281 1282 .org ia64_ivt+0x5600 1283///////////////////////////////////////////////////////////////////////////////////////// 1284// 0x5600 Entry 26 (size 16 bundles) Nat Consumption (11,23,37,50) 1285ENTRY(nat_consumption) 1286 DBG_FAULT(26) 1287 1288 mov r16=cr.ipsr 1289 mov r17=cr.isr 1290 mov r31=pr // save PR 1291 ;; 1292 and r18=0xf,r17 // r18 = cr.ipsr.code{3:0} 1293 tbit.z p6,p0=r17,IA64_ISR_NA_BIT 1294 ;; 1295 cmp.ne.or p6,p0=IA64_ISR_CODE_LFETCH,r18 1296 dep r16=-1,r16,IA64_PSR_ED_BIT,1 1297(p6) br.cond.spnt 1f // branch if (cr.ispr.na == 0 || cr.ipsr.code{3:0} != LFETCH) 1298 ;; 1299 mov cr.ipsr=r16 // set cr.ipsr.na 1300 mov pr=r31,-1 1301 ;; 1302 rfi 1303 13041: mov pr=r31,-1 1305 ;; 1306 FAULT(26) 1307END(nat_consumption) 1308 1309 .org ia64_ivt+0x5700 1310///////////////////////////////////////////////////////////////////////////////////////// 1311// 0x5700 Entry 27 (size 16 bundles) Speculation (40) 1312ENTRY(speculation_vector) 1313 DBG_FAULT(27) 1314 /* 1315 * A [f]chk.[as] instruction needs to take the branch to the recovery code but 1316 * this part of the architecture is not implemented in hardware on some CPUs, such 1317 * as Itanium. Thus, in general we need to emulate the behavior. IIM contains 1318 * the relative target (not yet sign extended). So after sign extending it we 1319 * simply add it to IIP. We also need to reset the EI field of the IPSR to zero, 1320 * i.e., the slot to restart into. 1321 * 1322 * cr.imm contains zero_ext(imm21) 1323 */ 1324 mov r18=cr.iim 1325 ;; 1326 mov r17=cr.iip 1327 shl r18=r18,43 // put sign bit in position (43=64-21) 1328 ;; 1329 1330 mov r16=cr.ipsr 1331 shr r18=r18,39 // sign extend (39=43-4) 1332 ;; 1333 1334 add r17=r17,r18 // now add the offset 1335 ;; 1336 mov cr.iip=r17 1337 dep r16=0,r16,41,2 // clear EI 1338 ;; 1339 1340 mov cr.ipsr=r16 1341 ;; 1342 1343 rfi // and go back 1344END(speculation_vector) 1345 1346 .org ia64_ivt+0x5800 1347///////////////////////////////////////////////////////////////////////////////////////// 1348// 0x5800 Entry 28 (size 16 bundles) Reserved 1349 DBG_FAULT(28) 1350 FAULT(28) 1351 1352 .org ia64_ivt+0x5900 1353///////////////////////////////////////////////////////////////////////////////////////// 1354// 0x5900 Entry 29 (size 16 bundles) Debug (16,28,56) 1355ENTRY(debug_vector) 1356 DBG_FAULT(29) 1357 FAULT(29) 1358END(debug_vector) 1359 1360 .org ia64_ivt+0x5a00 1361///////////////////////////////////////////////////////////////////////////////////////// 1362// 0x5a00 Entry 30 (size 16 bundles) Unaligned Reference (57) 1363ENTRY(unaligned_access) 1364 DBG_FAULT(30) 1365 mov r31=pr // prepare to save predicates 1366 ;; 1367 br.sptk.many dispatch_unaligned_handler 1368END(unaligned_access) 1369 1370 .org ia64_ivt+0x5b00 1371///////////////////////////////////////////////////////////////////////////////////////// 1372// 0x5b00 Entry 31 (size 16 bundles) Unsupported Data Reference (57) 1373ENTRY(unsupported_data_reference) 1374 DBG_FAULT(31) 1375 FAULT(31) 1376END(unsupported_data_reference) 1377 1378 .org ia64_ivt+0x5c00 1379///////////////////////////////////////////////////////////////////////////////////////// 1380// 0x5c00 Entry 32 (size 16 bundles) Floating-Point Fault (64) 1381ENTRY(floating_point_fault) 1382 DBG_FAULT(32) 1383 FAULT(32) 1384END(floating_point_fault) 1385 1386 .org ia64_ivt+0x5d00 1387///////////////////////////////////////////////////////////////////////////////////////// 1388// 0x5d00 Entry 33 (size 16 bundles) Floating Point Trap (66) 1389ENTRY(floating_point_trap) 1390 DBG_FAULT(33) 1391 FAULT(33) 1392END(floating_point_trap) 1393 1394 .org ia64_ivt+0x5e00 1395///////////////////////////////////////////////////////////////////////////////////////// 1396// 0x5e00 Entry 34 (size 16 bundles) Lower Privilege Transfer Trap (66) 1397ENTRY(lower_privilege_trap) 1398 DBG_FAULT(34) 1399 FAULT(34) 1400END(lower_privilege_trap) 1401 1402 .org ia64_ivt+0x5f00 1403///////////////////////////////////////////////////////////////////////////////////////// 1404// 0x5f00 Entry 35 (size 16 bundles) Taken Branch Trap (68) 1405ENTRY(taken_branch_trap) 1406 DBG_FAULT(35) 1407 FAULT(35) 1408END(taken_branch_trap) 1409 1410 .org ia64_ivt+0x6000 1411///////////////////////////////////////////////////////////////////////////////////////// 1412// 0x6000 Entry 36 (size 16 bundles) Single Step Trap (69) 1413ENTRY(single_step_trap) 1414 DBG_FAULT(36) 1415 FAULT(36) 1416END(single_step_trap) 1417 1418 .org ia64_ivt+0x6100 1419///////////////////////////////////////////////////////////////////////////////////////// 1420// 0x6100 Entry 37 (size 16 bundles) Reserved 1421 DBG_FAULT(37) 1422 FAULT(37) 1423 1424 .org ia64_ivt+0x6200 1425///////////////////////////////////////////////////////////////////////////////////////// 1426// 0x6200 Entry 38 (size 16 bundles) Reserved 1427 DBG_FAULT(38) 1428 FAULT(38) 1429 1430 .org ia64_ivt+0x6300 1431///////////////////////////////////////////////////////////////////////////////////////// 1432// 0x6300 Entry 39 (size 16 bundles) Reserved 1433 DBG_FAULT(39) 1434 FAULT(39) 1435 1436 .org ia64_ivt+0x6400 1437///////////////////////////////////////////////////////////////////////////////////////// 1438// 0x6400 Entry 40 (size 16 bundles) Reserved 1439 DBG_FAULT(40) 1440 FAULT(40) 1441 1442 .org ia64_ivt+0x6500 1443///////////////////////////////////////////////////////////////////////////////////////// 1444// 0x6500 Entry 41 (size 16 bundles) Reserved 1445 DBG_FAULT(41) 1446 FAULT(41) 1447 1448 .org ia64_ivt+0x6600 1449///////////////////////////////////////////////////////////////////////////////////////// 1450// 0x6600 Entry 42 (size 16 bundles) Reserved 1451 DBG_FAULT(42) 1452 FAULT(42) 1453 1454 .org ia64_ivt+0x6700 1455///////////////////////////////////////////////////////////////////////////////////////// 1456// 0x6700 Entry 43 (size 16 bundles) Reserved 1457 DBG_FAULT(43) 1458 FAULT(43) 1459 1460 .org ia64_ivt+0x6800 1461///////////////////////////////////////////////////////////////////////////////////////// 1462// 0x6800 Entry 44 (size 16 bundles) Reserved 1463 DBG_FAULT(44) 1464 FAULT(44) 1465 1466 .org ia64_ivt+0x6900 1467///////////////////////////////////////////////////////////////////////////////////////// 1468// 0x6900 Entry 45 (size 16 bundles) IA-32 Exeception (17,18,29,41,42,43,44,58,60,61,62,72,73,75,76,77) 1469ENTRY(ia32_exception) 1470 DBG_FAULT(45) 1471 FAULT(45) 1472END(ia32_exception) 1473 1474 .org ia64_ivt+0x6a00 1475///////////////////////////////////////////////////////////////////////////////////////// 1476// 0x6a00 Entry 46 (size 16 bundles) IA-32 Intercept (30,31,59,70,71) 1477ENTRY(ia32_intercept) 1478 DBG_FAULT(46) 1479#ifdef CONFIG_IA32_SUPPORT 1480 mov r31=pr 1481 mov r16=cr.isr 1482 ;; 1483 extr.u r17=r16,16,8 // get ISR.code 1484 mov r18=ar.eflag 1485 mov r19=cr.iim // old eflag value 1486 ;; 1487 cmp.ne p6,p0=2,r17 1488(p6) br.cond.spnt 1f // not a system flag fault 1489 xor r16=r18,r19 1490 ;; 1491 extr.u r17=r16,18,1 // get the eflags.ac bit 1492 ;; 1493 cmp.eq p6,p0=0,r17 1494(p6) br.cond.spnt 1f // eflags.ac bit didn't change 1495 ;; 1496 mov pr=r31,-1 // restore predicate registers 1497 rfi 1498 14991: 1500#endif // CONFIG_IA32_SUPPORT 1501 FAULT(46) 1502END(ia32_intercept) 1503 1504 .org ia64_ivt+0x6b00 1505///////////////////////////////////////////////////////////////////////////////////////// 1506// 0x6b00 Entry 47 (size 16 bundles) IA-32 Interrupt (74) 1507ENTRY(ia32_interrupt) 1508 DBG_FAULT(47) 1509#ifdef CONFIG_IA32_SUPPORT 1510 mov r31=pr 1511 br.sptk.many dispatch_to_ia32_handler 1512#else 1513 FAULT(47) 1514#endif 1515END(ia32_interrupt) 1516 1517 .org ia64_ivt+0x6c00 1518///////////////////////////////////////////////////////////////////////////////////////// 1519// 0x6c00 Entry 48 (size 16 bundles) Reserved 1520 DBG_FAULT(48) 1521 FAULT(48) 1522 1523 .org ia64_ivt+0x6d00 1524///////////////////////////////////////////////////////////////////////////////////////// 1525// 0x6d00 Entry 49 (size 16 bundles) Reserved 1526 DBG_FAULT(49) 1527 FAULT(49) 1528 1529 .org ia64_ivt+0x6e00 1530///////////////////////////////////////////////////////////////////////////////////////// 1531// 0x6e00 Entry 50 (size 16 bundles) Reserved 1532 DBG_FAULT(50) 1533 FAULT(50) 1534 1535 .org ia64_ivt+0x6f00 1536///////////////////////////////////////////////////////////////////////////////////////// 1537// 0x6f00 Entry 51 (size 16 bundles) Reserved 1538 DBG_FAULT(51) 1539 FAULT(51) 1540 1541 .org ia64_ivt+0x7000 1542///////////////////////////////////////////////////////////////////////////////////////// 1543// 0x7000 Entry 52 (size 16 bundles) Reserved 1544 DBG_FAULT(52) 1545 FAULT(52) 1546 1547 .org ia64_ivt+0x7100 1548///////////////////////////////////////////////////////////////////////////////////////// 1549// 0x7100 Entry 53 (size 16 bundles) Reserved 1550 DBG_FAULT(53) 1551 FAULT(53) 1552 1553 .org ia64_ivt+0x7200 1554///////////////////////////////////////////////////////////////////////////////////////// 1555// 0x7200 Entry 54 (size 16 bundles) Reserved 1556 DBG_FAULT(54) 1557 FAULT(54) 1558 1559 .org ia64_ivt+0x7300 1560///////////////////////////////////////////////////////////////////////////////////////// 1561// 0x7300 Entry 55 (size 16 bundles) Reserved 1562 DBG_FAULT(55) 1563 FAULT(55) 1564 1565 .org ia64_ivt+0x7400 1566///////////////////////////////////////////////////////////////////////////////////////// 1567// 0x7400 Entry 56 (size 16 bundles) Reserved 1568 DBG_FAULT(56) 1569 FAULT(56) 1570 1571 .org ia64_ivt+0x7500 1572///////////////////////////////////////////////////////////////////////////////////////// 1573// 0x7500 Entry 57 (size 16 bundles) Reserved 1574 DBG_FAULT(57) 1575 FAULT(57) 1576 1577 .org ia64_ivt+0x7600 1578///////////////////////////////////////////////////////////////////////////////////////// 1579// 0x7600 Entry 58 (size 16 bundles) Reserved 1580 DBG_FAULT(58) 1581 FAULT(58) 1582 1583 .org ia64_ivt+0x7700 1584///////////////////////////////////////////////////////////////////////////////////////// 1585// 0x7700 Entry 59 (size 16 bundles) Reserved 1586 DBG_FAULT(59) 1587 FAULT(59) 1588 1589 .org ia64_ivt+0x7800 1590///////////////////////////////////////////////////////////////////////////////////////// 1591// 0x7800 Entry 60 (size 16 bundles) Reserved 1592 DBG_FAULT(60) 1593 FAULT(60) 1594 1595 .org ia64_ivt+0x7900 1596///////////////////////////////////////////////////////////////////////////////////////// 1597// 0x7900 Entry 61 (size 16 bundles) Reserved 1598 DBG_FAULT(61) 1599 FAULT(61) 1600 1601 .org ia64_ivt+0x7a00 1602///////////////////////////////////////////////////////////////////////////////////////// 1603// 0x7a00 Entry 62 (size 16 bundles) Reserved 1604 DBG_FAULT(62) 1605 FAULT(62) 1606 1607 .org ia64_ivt+0x7b00 1608///////////////////////////////////////////////////////////////////////////////////////// 1609// 0x7b00 Entry 63 (size 16 bundles) Reserved 1610 DBG_FAULT(63) 1611 FAULT(63) 1612 1613 .org ia64_ivt+0x7c00 1614///////////////////////////////////////////////////////////////////////////////////////// 1615// 0x7c00 Entry 64 (size 16 bundles) Reserved 1616 DBG_FAULT(64) 1617 FAULT(64) 1618 1619 .org ia64_ivt+0x7d00 1620///////////////////////////////////////////////////////////////////////////////////////// 1621// 0x7d00 Entry 65 (size 16 bundles) Reserved 1622 DBG_FAULT(65) 1623 FAULT(65) 1624 1625 .org ia64_ivt+0x7e00 1626///////////////////////////////////////////////////////////////////////////////////////// 1627// 0x7e00 Entry 66 (size 16 bundles) Reserved 1628 DBG_FAULT(66) 1629 FAULT(66) 1630 1631 .org ia64_ivt+0x7f00 1632///////////////////////////////////////////////////////////////////////////////////////// 1633// 0x7f00 Entry 67 (size 16 bundles) Reserved 1634 DBG_FAULT(67) 1635 FAULT(67) 1636 1637#ifdef CONFIG_IA32_SUPPORT 1638 1639 /* 1640 * There is no particular reason for this code to be here, other than that 1641 * there happens to be space here that would go unused otherwise. If this 1642 * fault ever gets "unreserved", simply moved the following code to a more 1643 * suitable spot... 1644 */ 1645 1646 // IA32 interrupt entry point 1647 1648ENTRY(dispatch_to_ia32_handler) 1649 SAVE_MIN 1650 ;; 1651 mov r14=cr.isr 1652 ssm psr.ic | PSR_DEFAULT_BITS 1653 ;; 1654 srlz.i // guarantee that interruption collection is on 1655 ;; 1656(p15) ssm psr.i 1657 adds r3=8,r2 // Base pointer for SAVE_REST 1658 ;; 1659 SAVE_REST 1660 ;; 1661 mov r15=0x80 1662 shr r14=r14,16 // Get interrupt number 1663 ;; 1664 cmp.ne p6,p0=r14,r15 1665(p6) br.call.dpnt.many b6=non_ia32_syscall 1666 1667 adds r14=IA64_PT_REGS_R8_OFFSET + 16,sp // 16 byte hole per SW conventions 1668 adds r15=IA64_PT_REGS_R1_OFFSET + 16,sp 1669 ;; 1670 cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0 1671 ld8 r8=[r14] // get r8 1672 ;; 1673 st8 [r15]=r8 // save original EAX in r1 (IA32 procs don't use the GP) 1674 ;; 1675 alloc r15=ar.pfs,0,0,6,0 // must first in an insn group 1676 ;; 1677 ld4 r8=[r14],8 // r8 == eax (syscall number) 1678 mov r15=IA32_NR_syscalls 1679 ;; 1680 cmp.ltu.unc p6,p7=r8,r15 1681 ld4 out1=[r14],8 // r9 == ecx 1682 ;; 1683 ld4 out2=[r14],8 // r10 == edx 1684 ;; 1685 ld4 out0=[r14] // r11 == ebx 1686 adds r14=(IA64_PT_REGS_R13_OFFSET) + 16,sp 1687 ;; 1688 ld4 out5=[r14],PT(R14)-PT(R13) // r13 == ebp 1689 ;; 1690 ld4 out3=[r14],PT(R15)-PT(R14) // r14 == esi 1691 adds r2=TI_FLAGS+IA64_TASK_SIZE,r13 1692 ;; 1693 ld4 out4=[r14] // r15 == edi 1694 movl r16=ia32_syscall_table 1695 ;; 1696(p6) shladd r16=r8,3,r16 // force ni_syscall if not valid syscall number 1697 ld4 r2=[r2] // r2 = current_thread_info()->flags 1698 ;; 1699 ld8 r16=[r16] 1700 and r2=_TIF_SYSCALL_TRACEAUDIT,r2 // mask trace or audit 1701 ;; 1702 mov b6=r16 1703 movl r15=ia32_ret_from_syscall 1704 cmp.eq p8,p0=r2,r0 1705 ;; 1706 mov rp=r15 1707(p8) br.call.sptk.many b6=b6 1708 br.cond.sptk ia32_trace_syscall 1709 1710non_ia32_syscall: 1711 alloc r15=ar.pfs,0,0,2,0 1712 mov out0=r14 // interrupt # 1713 add out1=16,sp // pointer to pt_regs 1714 ;; // avoid WAW on CFM 1715 br.call.sptk.many rp=ia32_bad_interrupt 1716.ret1: movl r15=ia64_leave_kernel 1717 ;; 1718 mov rp=r15 1719 br.ret.sptk.many rp 1720END(dispatch_to_ia32_handler) 1721 1722#endif /* CONFIG_IA32_SUPPORT */ 1723