1#include <linux/kernel.h>
2#include <linux/init.h>
3#include <linux/bitops.h>
4#include <asm/processor.h>
5
6#include "cpu.h"
7
8static void __cpuinit init_rise(struct cpuinfo_x86 *c)
9{
10	printk("CPU: Rise iDragon");
11	if (c->x86_model > 2)
12		printk(" II");
13	printk("\n");
14
15	/* Unhide possibly hidden capability flags
16	   The mp6 iDragon family don't have MSRs.
17	   We switch on extra features with this cpuid weirdness: */
18	__asm__ (
19		"movl $0x6363452a, %%eax\n\t"
20		"movl $0x3231206c, %%ecx\n\t"
21		"movl $0x2a32313a, %%edx\n\t"
22		"cpuid\n\t"
23		"movl $0x63634523, %%eax\n\t"
24		"movl $0x32315f6c, %%ecx\n\t"
25		"movl $0x2333313a, %%edx\n\t"
26		"cpuid\n\t" : : : "eax", "ebx", "ecx", "edx"
27	);
28	set_bit(X86_FEATURE_CX8, c->x86_capability);
29}
30
31static struct cpu_dev rise_cpu_dev __cpuinitdata = {
32	.c_vendor	= "Rise",
33	.c_ident	= { "RiseRiseRise" },
34	.c_models = {
35		{ .vendor = X86_VENDOR_RISE, .family = 5, .model_names =
36		  {
37			  [0] = "iDragon",
38			  [2] = "iDragon",
39			  [8] = "iDragon II",
40			  [9] = "iDragon II"
41		  }
42		},
43	},
44	.c_init		= init_rise,
45};
46
47int __init rise_init_cpu(void)
48{
49	cpu_devs[X86_VENDOR_RISE] = &rise_cpu_dev;
50	return 0;
51}
52