1/* 2 * (c) 2003-2006 Advanced Micro Devices, Inc. 3 * Your use of this code is subject to the terms and conditions of the 4 * GNU general public license version 2. See "COPYING" or 5 * http://www.gnu.org/licenses/gpl.html 6 */ 7 8struct powernow_k8_data { 9 unsigned int cpu; 10 11 u32 numps; /* number of p-states */ 12 u32 batps; /* number of p-states supported on battery */ 13 14 /* these values are constant when the PSB is used to determine 15 * vid/fid pairings, but are modified during the ->target() call 16 * when ACPI is used */ 17 u32 rvo; /* ramp voltage offset */ 18 u32 irt; /* isochronous relief time */ 19 u32 vidmvs; /* usable value calculated from mvs */ 20 u32 vstable; /* voltage stabilization time, units 20 us */ 21 u32 plllock; /* pll lock time, units 1 us */ 22 u32 exttype; /* extended interface = 1 */ 23 24 /* keep track of the current fid / vid or did */ 25 u32 currvid, currfid, currdid; 26 27 /* the powernow_table includes all frequency and vid/fid pairings: 28 * fid are the lower 8 bits of the index, vid are the upper 8 bits. 29 * frequency is in kHz */ 30 struct cpufreq_frequency_table *powernow_table; 31 32#ifdef CONFIG_X86_POWERNOW_K8_ACPI 33 /* the acpi table needs to be kept. it's only available if ACPI was 34 * used to determine valid frequency/vid/fid states */ 35 struct acpi_processor_performance acpi_data; 36#endif 37 /* we need to keep track of associated cores, but let cpufreq 38 * handle hotplug events - so just point at cpufreq pol->cpus 39 * structure */ 40 cpumask_t *available_cores; 41}; 42 43 44/* processor's cpuid instruction support */ 45#define CPUID_PROCESSOR_SIGNATURE 1 /* function 1 */ 46#define CPUID_XFAM 0x0ff00000 /* extended family */ 47#define CPUID_XFAM_K8 0 48#define CPUID_XMOD 0x000f0000 /* extended model */ 49#define CPUID_XMOD_REV_MASK 0x00080000 50#define CPUID_XFAM_10H 0x00100000 /* family 0x10 */ 51#define CPUID_USE_XFAM_XMOD 0x00000f00 52#define CPUID_GET_MAX_CAPABILITIES 0x80000000 53#define CPUID_FREQ_VOLT_CAPABILITIES 0x80000007 54#define P_STATE_TRANSITION_CAPABLE 6 55 56/* Model Specific Registers for p-state transitions. MSRs are 64-bit. For */ 57/* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and */ 58/* the value to write is placed in edx:eax. For reads (rdmsr - opcode 0f 32), */ 59/* the register number is placed in ecx, and the data is returned in edx:eax. */ 60 61#define MSR_FIDVID_CTL 0xc0010041 62#define MSR_FIDVID_STATUS 0xc0010042 63 64/* Field definitions within the FID VID Low Control MSR : */ 65#define MSR_C_LO_INIT_FID_VID 0x00010000 66#define MSR_C_LO_NEW_VID 0x00003f00 67#define MSR_C_LO_NEW_FID 0x0000003f 68#define MSR_C_LO_VID_SHIFT 8 69 70/* Field definitions within the FID VID High Control MSR : */ 71#define MSR_C_HI_STP_GNT_TO 0x000fffff 72 73/* Field definitions within the FID VID Low Status MSR : */ 74#define MSR_S_LO_CHANGE_PENDING 0x80000000 /* cleared when completed */ 75#define MSR_S_LO_MAX_RAMP_VID 0x3f000000 76#define MSR_S_LO_MAX_FID 0x003f0000 77#define MSR_S_LO_START_FID 0x00003f00 78#define MSR_S_LO_CURRENT_FID 0x0000003f 79 80/* Field definitions within the FID VID High Status MSR : */ 81#define MSR_S_HI_MIN_WORKING_VID 0x3f000000 82#define MSR_S_HI_MAX_WORKING_VID 0x003f0000 83#define MSR_S_HI_START_VID 0x00003f00 84#define MSR_S_HI_CURRENT_VID 0x0000003f 85#define MSR_C_HI_STP_GNT_BENIGN 0x00000001 86 87 88/* Hardware Pstate _PSS and MSR definitions */ 89#define USE_HW_PSTATE 0x00000080 90#define HW_PSTATE_FID_MASK 0x0000003f 91#define HW_PSTATE_DID_MASK 0x000001c0 92#define HW_PSTATE_DID_SHIFT 6 93#define HW_PSTATE_MASK 0x00000007 94#define HW_PSTATE_VALID_MASK 0x80000000 95#define HW_FID_INDEX_SHIFT 8 96#define HW_FID_INDEX_MASK 0x0000ff00 97#define HW_DID_INDEX_SHIFT 16 98#define HW_DID_INDEX_MASK 0x00ff0000 99#define HW_WATTS_MASK 0xff 100#define HW_PWR_DVR_MASK 0x300 101#define HW_PWR_DVR_SHIFT 8 102#define HW_PWR_MAX_MULT 3 103#define MAX_HW_PSTATE 8 /* hw pstate supports up to 8 */ 104#define MSR_PSTATE_DEF_BASE 0xc0010064 /* base of Pstate MSRs */ 105#define MSR_PSTATE_STATUS 0xc0010063 /* Pstate Status MSR */ 106#define MSR_PSTATE_CTRL 0xc0010062 /* Pstate control MSR */ 107 108/* define the two driver architectures */ 109#define CPU_OPTERON 0 110#define CPU_HW_PSTATE 1 111 112 113/* 114 * There are restrictions frequencies have to follow: 115 * - only 1 entry in the low fid table ( <=1.4GHz ) 116 * - lowest entry in the high fid table must be >= 2 * the entry in the 117 * low fid table 118 * - lowest entry in the high fid table must be a <= 200MHz + 2 * the entry 119 * in the low fid table 120 * - the parts can only step at <= 200 MHz intervals, odd fid values are 121 * supported in revision G and later revisions. 122 * - lowest frequency must be >= interprocessor hypertransport link speed 123 * (only applies to MP systems obviously) 124 */ 125 126/* fids (frequency identifiers) are arranged in 2 tables - lo and hi */ 127#define LO_FID_TABLE_TOP 7 /* fid values marking the boundary */ 128#define HI_FID_TABLE_BOTTOM 8 /* between the low and high tables */ 129 130#define LO_VCOFREQ_TABLE_TOP 1400 /* corresponding vco frequency values */ 131#define HI_VCOFREQ_TABLE_BOTTOM 1600 132 133#define MIN_FREQ_RESOLUTION 200 /* fids jump by 2 matching freq jumps by 200 */ 134 135#define MAX_FID 0x2a /* Spec only gives FID values as far as 5 GHz */ 136#define LEAST_VID 0x3e /* Lowest (numerically highest) useful vid value */ 137 138#define MIN_FREQ 800 /* Min and max freqs, per spec */ 139#define MAX_FREQ 5000 140 141#define INVALID_FID_MASK 0xffffffc0 /* not a valid fid if these bits are set */ 142#define INVALID_VID_MASK 0xffffffc0 /* not a valid vid if these bits are set */ 143 144#define VID_OFF 0x3f 145 146#define STOP_GRANT_5NS 1 /* min poss memory access latency for voltage change */ 147 148#define PLL_LOCK_CONVERSION (1000/5) /* ms to ns, then divide by clock period */ 149 150#define MAXIMUM_VID_STEPS 1 /* Current cpus only allow a single step of 25mV */ 151#define VST_UNITS_20US 20 /* Voltage Stabalization Time is in units of 20us */ 152 153/* 154 * Most values of interest are enocoded in a single field of the _PSS 155 * entries: the "control" value. 156 */ 157 158#define IRT_SHIFT 30 159#define RVO_SHIFT 28 160#define EXT_TYPE_SHIFT 27 161#define PLL_L_SHIFT 20 162#define MVS_SHIFT 18 163#define VST_SHIFT 11 164#define VID_SHIFT 6 165#define IRT_MASK 3 166#define RVO_MASK 3 167#define EXT_TYPE_MASK 1 168#define PLL_L_MASK 0x7f 169#define MVS_MASK 3 170#define VST_MASK 0x7f 171#define VID_MASK 0x1f 172#define FID_MASK 0x1f 173#define EXT_VID_MASK 0x3f 174#define EXT_FID_MASK 0x3f 175 176 177/* 178 * Version 1.4 of the PSB table. This table is constructed by BIOS and is 179 * to tell the OS's power management driver which VIDs and FIDs are 180 * supported by this particular processor. 181 * If the data in the PSB / PST is wrong, then this driver will program the 182 * wrong values into hardware, which is very likely to lead to a crash. 183 */ 184 185#define PSB_ID_STRING "AMDK7PNOW!" 186#define PSB_ID_STRING_LEN 10 187 188#define PSB_VERSION_1_4 0x14 189 190struct psb_s { 191 u8 signature[10]; 192 u8 tableversion; 193 u8 flags1; 194 u16 vstable; 195 u8 flags2; 196 u8 num_tables; 197 u32 cpuid; 198 u8 plllocktime; 199 u8 maxfid; 200 u8 maxvid; 201 u8 numps; 202}; 203 204/* Pairs of fid/vid values are appended to the version 1.4 PSB table. */ 205struct pst_s { 206 u8 fid; 207 u8 vid; 208}; 209 210#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "powernow-k8", msg) 211 212static int core_voltage_pre_transition(struct powernow_k8_data *data, u32 reqvid); 213static int core_voltage_post_transition(struct powernow_k8_data *data, u32 reqvid); 214static int core_frequency_transition(struct powernow_k8_data *data, u32 reqfid); 215 216static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned int index); 217 218#ifdef CONFIG_X86_POWERNOW_K8_ACPI 219static int fill_powernow_table_pstate(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table); 220static int fill_powernow_table_fidvid(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table); 221#endif 222 223#ifdef CONFIG_SMP 224static inline void define_siblings(int cpu, cpumask_t cpu_sharedcore_mask[]) 225{ 226} 227#else 228static inline void define_siblings(int cpu, cpumask_t cpu_sharedcore_mask[]) 229{ 230 cpu_set(0, cpu_sharedcore_mask[0]); 231} 232#endif 233