1/* $Id: dram_init.S,v 1.1.1.1 2007-08-03 18:51:42 $
2 *
3 * DRAM/SDRAM initialization - alter with care
4 * This file is intended to be included from other assembler files
5 *
6 * Note: This file may not modify r8 or r9 because they are used to
7 * carry information from the decompresser to the kernel
8 *
9 * Copyright (C) 2000-2003 Axis Communications AB
10 *
11 * Authors:  Mikael Starvik (starvik@axis.com)
12 */
13
14/* Just to be certain the config file is included, we include it here
15 * explicitely instead of depending on it being included in the file that
16 * uses this code.
17 */
18
19#include <asm/arch/hwregs/asm/reg_map_asm.h>
20#include <asm/arch/hwregs/asm/bif_core_defs_asm.h>
21
22	;; WARNING! The registers r8 and r9 are used as parameters carrying
23	;; information from the decompressor (if the kernel was compressed).
24	;; They should not be used in the code below.
25
26	; Refer to BIF MDS for a description of SDRAM initialization
27
28	; Bank configuration
29	move.d   REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp0), $r0
30	move.d   CONFIG_ETRAX_SDRAM_GRP0_CONFIG, $r1
31	move.d   $r1, [$r0]
32	move.d   REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp1), $r0
33	move.d   CONFIG_ETRAX_SDRAM_GRP1_CONFIG, $r1
34	move.d   $r1, [$r0]
35
36	; Calculate value of mrs_data
37	; CAS latency = 2 && bus_width = 32 => 0x40
38	; CAS latency = 3 && bus_width = 32 => 0x60
39	; CAS latency = 2 && bus_width = 16 => 0x20
40	; CAS latency = 3 && bus_width = 16 => 0x30
41
42	; Check if value is already supplied in kernel config
43	move.d   CONFIG_ETRAX_SDRAM_COMMAND, $r2
44	bne	 _set_timing
45	nop
46
47	move.d   0x40, $r4       ; Assume 32 bits and CAS latency = 2
48	move.d   CONFIG_ETRAX_SDRAM_TIMING, $r1
49 	and.d    0x07, $r1       ; Get CAS latency
50	cmpq	 2, $r1		 ; CL = 2 ?
51	beq	 _bw_check
52	nop
53	move.d   0x60, $r4
54
55_bw_check:
56	; Assume that group 0 width is equal to group 1. This assumption
57	; is wrong for a group 1 only hardware (such as the grand old
58	; StorPoint+).
59	move.d   CONFIG_ETRAX_SDRAM_GRP0_CONFIG, $r1
60	and.d    0x200, $r1	; DRAM width is bit 9
61	beq      _set_timing
62	lslq	 2, $r4		;  mrs_data starts at bit 2
63	lsrq     1, $r4		;  16 bits. Shift down value.
64
65	; Set timing parameters (refresh off to avoid Guinness TR 83)
66_set_timing:
67	move.d   CONFIG_ETRAX_SDRAM_TIMING, $r1
68	and.d    ~(3 << reg_bif_core_rw_sdram_timing___ref___lsb), $r1
69	move.d   REG_ADDR(bif_core, regi_bif_core, rw_sdram_timing), $r0
70	move.d   $r1, [$r0]
71
72	; Issue NOP command
73	move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_cmd), $r5
74	moveq regk_bif_core_nop, $r1
75	move.d $r1, [$r5]
76
77	; Wait 200us
78	move.d   10000, $r2
791:	bne      1b
80	subq     1, $r2
81
82	; Issue initialization command sequence
83	move.d   _sdram_commands_start, $r2
84	and.d    0x000fffff, $r2 ; Make sure commands are read from flash
85	move.d   _sdram_commands_end,  $r3
86	and.d    0x000fffff, $r3
871:	clear.d  $r6
88	move.b   [$r2+], $r6 	; Load command
89	or.d     $r4, $r6	; Add calculated mrs
90	move.d   $r6, [$r5]	; Write rw_sdram_cmd
91	; Wait 80 ns between each command
92	move.d	 4000, $r7
932:	bne	 2b
94	subq	 1, $r7
95	cmp.d    $r2, $r3	; Last command?
96	bne      1b
97	nop
98
99	; Start refresh
100	move.d   CONFIG_ETRAX_SDRAM_TIMING, $r1
101	move.d   REG_ADDR(bif_core, regi_bif_core, rw_sdram_timing), $r0
102	move.d   $r1, [$r0]
103
104	; Initialization finished
105	ba       _sdram_commands_end
106	nop
107
108_sdram_commands_start:
109	.byte   regk_bif_core_pre ; Precharge
110	.byte   regk_bif_core_ref ; refresh
111	.byte   regk_bif_core_ref ; refresh
112	.byte   regk_bif_core_ref ; refresh
113	.byte   regk_bif_core_ref ; refresh
114	.byte   regk_bif_core_ref ; refresh
115	.byte   regk_bif_core_ref ; refresh
116	.byte   regk_bif_core_ref ; refresh
117	.byte   regk_bif_core_ref ; refresh
118	.byte   regk_bif_core_mrs ; mrs
119_sdram_commands_end:
120