1#include <asm/delay.h> 2#include <asm/arch/irq.h> 3#include <asm/arch/hwregs/intr_vect.h> 4#include <asm/arch/hwregs/intr_vect_defs.h> 5#include <asm/tlbflush.h> 6#include <asm/mmu_context.h> 7#include <asm/arch/hwregs/mmu_defs_asm.h> 8#include <asm/arch/hwregs/supp_reg.h> 9#include <asm/atomic.h> 10 11#include <linux/err.h> 12#include <linux/init.h> 13#include <linux/timex.h> 14#include <linux/sched.h> 15#include <linux/kernel.h> 16#include <linux/cpumask.h> 17#include <linux/interrupt.h> 18#include <linux/module.h> 19 20#define IPI_SCHEDULE 1 21#define IPI_CALL 2 22#define IPI_FLUSH_TLB 4 23 24#define FLUSH_ALL (void*)0xffffffff 25 26/* Vector of locks used for various atomic operations */ 27spinlock_t cris_atomic_locks[] = { [0 ... LOCK_COUNT - 1] = SPIN_LOCK_UNLOCKED}; 28 29/* CPU masks */ 30cpumask_t cpu_online_map = CPU_MASK_NONE; 31EXPORT_SYMBOL(cpu_online_map); 32cpumask_t phys_cpu_present_map = CPU_MASK_NONE; 33EXPORT_SYMBOL(phys_cpu_present_map); 34 35/* Variables used during SMP boot */ 36volatile int cpu_now_booting = 0; 37volatile struct thread_info *smp_init_current_idle_thread; 38 39/* Variables used during IPI */ 40static DEFINE_SPINLOCK(call_lock); 41static DEFINE_SPINLOCK(tlbstate_lock); 42 43struct call_data_struct { 44 void (*func) (void *info); 45 void *info; 46 int wait; 47}; 48 49static struct call_data_struct * call_data; 50 51static struct mm_struct* flush_mm; 52static struct vm_area_struct* flush_vma; 53static unsigned long flush_addr; 54 55extern int setup_irq(int, struct irqaction *); 56 57/* Mode registers */ 58static unsigned long irq_regs[NR_CPUS] = 59{ 60 regi_irq, 61 regi_irq2 62}; 63 64static irqreturn_t crisv32_ipi_interrupt(int irq, void *dev_id, struct pt_regs *regs); 65static int send_ipi(int vector, int wait, cpumask_t cpu_mask); 66static struct irqaction irq_ipi = { crisv32_ipi_interrupt, IRQF_DISABLED, 67 CPU_MASK_NONE, "ipi", NULL, NULL}; 68 69extern void cris_mmu_init(void); 70extern void cris_timer_init(void); 71 72/* SMP initialization */ 73void __init smp_prepare_cpus(unsigned int max_cpus) 74{ 75 int i; 76 77 /* From now on we can expect IPIs so set them up */ 78 setup_irq(IPI_INTR_VECT, &irq_ipi); 79 80 /* Mark all possible CPUs as present */ 81 for (i = 0; i < max_cpus; i++) 82 cpu_set(i, phys_cpu_present_map); 83} 84 85void __devinit smp_prepare_boot_cpu(void) 86{ 87 /* PGD pointer has moved after per_cpu initialization so 88 * update the MMU. 89 */ 90 pgd_t **pgd; 91 pgd = (pgd_t**)&per_cpu(current_pgd, smp_processor_id()); 92 93 SUPP_BANK_SEL(1); 94 SUPP_REG_WR(RW_MM_TLB_PGD, pgd); 95 SUPP_BANK_SEL(2); 96 SUPP_REG_WR(RW_MM_TLB_PGD, pgd); 97 98 cpu_set(0, cpu_online_map); 99 cpu_set(0, phys_cpu_present_map); 100} 101 102void __init smp_cpus_done(unsigned int max_cpus) 103{ 104} 105 106/* Bring one cpu online.*/ 107static int __init 108smp_boot_one_cpu(int cpuid) 109{ 110 unsigned timeout; 111 struct task_struct *idle; 112 113 idle = fork_idle(cpuid); 114 if (IS_ERR(idle)) 115 panic("SMP: fork failed for CPU:%d", cpuid); 116 117 task_thread_info(idle)->cpu = cpuid; 118 119 /* Information to the CPU that is about to boot */ 120 smp_init_current_idle_thread = task_thread_info(idle); 121 cpu_now_booting = cpuid; 122 123 /* Wait for CPU to come online */ 124 for (timeout = 0; timeout < 10000; timeout++) { 125 if(cpu_online(cpuid)) { 126 cpu_now_booting = 0; 127 smp_init_current_idle_thread = NULL; 128 return 0; /* CPU online */ 129 } 130 udelay(100); 131 barrier(); 132 } 133 134 put_task_struct(idle); 135 idle = NULL; 136 137 printk(KERN_CRIT "SMP: CPU:%d is stuck.\n", cpuid); 138 return -1; 139} 140 141/* Secondary CPUs starts uing C here. Here we need to setup CPU 142 * specific stuff such as the local timer and the MMU. */ 143void __init smp_callin(void) 144{ 145 extern void cpu_idle(void); 146 147 int cpu = cpu_now_booting; 148 reg_intr_vect_rw_mask vect_mask = {0}; 149 150 /* Initialise the idle task for this CPU */ 151 atomic_inc(&init_mm.mm_count); 152 current->active_mm = &init_mm; 153 154 /* Set up MMU */ 155 cris_mmu_init(); 156 __flush_tlb_all(); 157 158 /* Setup local timer. */ 159 cris_timer_init(); 160 161 /* Enable IRQ and idle */ 162 REG_WR(intr_vect, irq_regs[cpu], rw_mask, vect_mask); 163 unmask_irq(IPI_INTR_VECT); 164 unmask_irq(TIMER_INTR_VECT); 165 preempt_disable(); 166 local_irq_enable(); 167 168 cpu_set(cpu, cpu_online_map); 169 cpu_idle(); 170} 171 172/* Stop execution on this CPU.*/ 173void stop_this_cpu(void* dummy) 174{ 175 local_irq_disable(); 176 asm volatile("halt"); 177} 178 179/* Other calls */ 180void smp_send_stop(void) 181{ 182 smp_call_function(stop_this_cpu, NULL, 1, 0); 183} 184 185int setup_profiling_timer(unsigned int multiplier) 186{ 187 return -EINVAL; 188} 189 190 191/* cache_decay_ticks is used by the scheduler to decide if a process 192 * is "hot" on one CPU. A higher value means a higher penalty to move 193 * a process to another CPU. Our cache is rather small so we report 194 * 1 tick. 195 */ 196unsigned long cache_decay_ticks = 1; 197 198int __cpuinit __cpu_up(unsigned int cpu) 199{ 200 smp_boot_one_cpu(cpu); 201 return cpu_online(cpu) ? 0 : -ENOSYS; 202} 203 204void smp_send_reschedule(int cpu) 205{ 206 cpumask_t cpu_mask = CPU_MASK_NONE; 207 cpu_set(cpu, cpu_mask); 208 send_ipi(IPI_SCHEDULE, 0, cpu_mask); 209} 210 211/* TLB flushing 212 * 213 * Flush needs to be done on the local CPU and on any other CPU that 214 * may have the same mapping. The mm->cpu_vm_mask is used to keep track 215 * of which CPUs that a specific process has been executed on. 216 */ 217void flush_tlb_common(struct mm_struct* mm, struct vm_area_struct* vma, unsigned long addr) 218{ 219 unsigned long flags; 220 cpumask_t cpu_mask; 221 222 spin_lock_irqsave(&tlbstate_lock, flags); 223 cpu_mask = (mm == FLUSH_ALL ? CPU_MASK_ALL : mm->cpu_vm_mask); 224 cpu_clear(smp_processor_id(), cpu_mask); 225 flush_mm = mm; 226 flush_vma = vma; 227 flush_addr = addr; 228 send_ipi(IPI_FLUSH_TLB, 1, cpu_mask); 229 spin_unlock_irqrestore(&tlbstate_lock, flags); 230} 231 232void flush_tlb_all(void) 233{ 234 __flush_tlb_all(); 235 flush_tlb_common(FLUSH_ALL, FLUSH_ALL, 0); 236} 237 238void flush_tlb_mm(struct mm_struct *mm) 239{ 240 __flush_tlb_mm(mm); 241 flush_tlb_common(mm, FLUSH_ALL, 0); 242 /* No more mappings in other CPUs */ 243 cpus_clear(mm->cpu_vm_mask); 244 cpu_set(smp_processor_id(), mm->cpu_vm_mask); 245} 246 247void flush_tlb_page(struct vm_area_struct *vma, 248 unsigned long addr) 249{ 250 __flush_tlb_page(vma, addr); 251 flush_tlb_common(vma->vm_mm, vma, addr); 252} 253 254/* Inter processor interrupts 255 * 256 * The IPIs are used for: 257 * * Force a schedule on a CPU 258 * * FLush TLB on other CPUs 259 * * Call a function on other CPUs 260 */ 261 262int send_ipi(int vector, int wait, cpumask_t cpu_mask) 263{ 264 int i = 0; 265 reg_intr_vect_rw_ipi ipi = REG_RD(intr_vect, irq_regs[i], rw_ipi); 266 int ret = 0; 267 268 /* Calculate CPUs to send to. */ 269 cpus_and(cpu_mask, cpu_mask, cpu_online_map); 270 271 /* Send the IPI. */ 272 for_each_cpu_mask(i, cpu_mask) 273 { 274 ipi.vector |= vector; 275 REG_WR(intr_vect, irq_regs[i], rw_ipi, ipi); 276 } 277 278 /* Wait for IPI to finish on other CPUS */ 279 if (wait) { 280 for_each_cpu_mask(i, cpu_mask) { 281 int j; 282 for (j = 0 ; j < 1000; j++) { 283 ipi = REG_RD(intr_vect, irq_regs[i], rw_ipi); 284 if (!ipi.vector) 285 break; 286 udelay(100); 287 } 288 289 /* Timeout? */ 290 if (ipi.vector) { 291 printk("SMP call timeout from %d to %d\n", smp_processor_id(), i); 292 ret = -ETIMEDOUT; 293 dump_stack(); 294 } 295 } 296 } 297 return ret; 298} 299 300/* 301 * You must not call this function with disabled interrupts or from a 302 * hardware interrupt handler or from a bottom half handler. 303 */ 304int smp_call_function(void (*func)(void *info), void *info, 305 int nonatomic, int wait) 306{ 307 cpumask_t cpu_mask = CPU_MASK_ALL; 308 struct call_data_struct data; 309 int ret; 310 311 cpu_clear(smp_processor_id(), cpu_mask); 312 313 WARN_ON(irqs_disabled()); 314 315 data.func = func; 316 data.info = info; 317 data.wait = wait; 318 319 spin_lock(&call_lock); 320 call_data = &data; 321 ret = send_ipi(IPI_CALL, wait, cpu_mask); 322 spin_unlock(&call_lock); 323 324 return ret; 325} 326 327irqreturn_t crisv32_ipi_interrupt(int irq, void *dev_id, struct pt_regs *regs) 328{ 329 void (*func) (void *info) = call_data->func; 330 void *info = call_data->info; 331 reg_intr_vect_rw_ipi ipi; 332 333 ipi = REG_RD(intr_vect, irq_regs[smp_processor_id()], rw_ipi); 334 335 if (ipi.vector & IPI_CALL) { 336 func(info); 337 } 338 if (ipi.vector & IPI_FLUSH_TLB) { 339 if (flush_mm == FLUSH_ALL) 340 __flush_tlb_all(); 341 else if (flush_vma == FLUSH_ALL) 342 __flush_tlb_mm(flush_mm); 343 else 344 __flush_tlb_page(flush_vma, flush_addr); 345 } 346 347 ipi.vector = 0; 348 REG_WR(intr_vect, irq_regs[smp_processor_id()], rw_ipi, ipi); 349 350 return IRQ_HANDLED; 351} 352