1/*
2 * Copyright (C) 2005-2006 Atmel Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8#include <linux/clk.h>
9#include <linux/fb.h>
10#include <linux/init.h>
11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h>
13#include <linux/spi/spi.h>
14
15#include <asm/io.h>
16
17#include <asm/arch/at32ap7000.h>
18#include <asm/arch/board.h>
19#include <asm/arch/portmux.h>
20#include <asm/arch/sm.h>
21
22#include <video/atmel_lcdc.h>
23
24#include "clock.h"
25#include "hmatrix.h"
26#include "pio.h"
27#include "sm.h"
28
29#define PBMEM(base)					\
30	{						\
31		.start		= base,			\
32		.end		= base + 0x3ff,		\
33		.flags		= IORESOURCE_MEM,	\
34	}
35#define IRQ(num)					\
36	{						\
37		.start		= num,			\
38		.end		= num,			\
39		.flags		= IORESOURCE_IRQ,	\
40	}
41#define NAMED_IRQ(num, _name)				\
42	{						\
43		.start		= num,			\
44		.end		= num,			\
45		.name		= _name,		\
46		.flags		= IORESOURCE_IRQ,	\
47	}
48
49/* REVISIT these assume *every* device supports DMA, but several
50 * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
51 */
52#define DEFINE_DEV(_name, _id)					\
53static u64 _name##_id##_dma_mask = DMA_32BIT_MASK;		\
54static struct platform_device _name##_id##_device = {		\
55	.name		= #_name,				\
56	.id		= _id,					\
57	.dev		= {					\
58		.dma_mask = &_name##_id##_dma_mask,		\
59		.coherent_dma_mask = DMA_32BIT_MASK,		\
60	},							\
61	.resource	= _name##_id##_resource,		\
62	.num_resources	= ARRAY_SIZE(_name##_id##_resource),	\
63}
64#define DEFINE_DEV_DATA(_name, _id)				\
65static u64 _name##_id##_dma_mask = DMA_32BIT_MASK;		\
66static struct platform_device _name##_id##_device = {		\
67	.name		= #_name,				\
68	.id		= _id,					\
69	.dev		= {					\
70		.dma_mask = &_name##_id##_dma_mask,		\
71		.platform_data	= &_name##_id##_data,		\
72		.coherent_dma_mask = DMA_32BIT_MASK,		\
73	},							\
74	.resource	= _name##_id##_resource,		\
75	.num_resources	= ARRAY_SIZE(_name##_id##_resource),	\
76}
77
78#define select_peripheral(pin, periph, flags)			\
79	at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
80
81#define DEV_CLK(_name, devname, bus, _index)			\
82static struct clk devname##_##_name = {				\
83	.name		= #_name,				\
84	.dev		= &devname##_device.dev,		\
85	.parent		= &bus##_clk,				\
86	.mode		= bus##_clk_mode,			\
87	.get_rate	= bus##_clk_get_rate,			\
88	.index		= _index,				\
89}
90
91unsigned long at32ap7000_osc_rates[3] = {
92	[0] = 32768,
93	[1] = 20000000,
94	[2] = 12000000,
95};
96
97static unsigned long osc_get_rate(struct clk *clk)
98{
99	return at32ap7000_osc_rates[clk->index];
100}
101
102static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
103{
104	unsigned long div, mul, rate;
105
106	if (!(control & SM_BIT(PLLEN)))
107		return 0;
108
109	div = SM_BFEXT(PLLDIV, control) + 1;
110	mul = SM_BFEXT(PLLMUL, control) + 1;
111
112	rate = clk->parent->get_rate(clk->parent);
113	rate = (rate + div / 2) / div;
114	rate *= mul;
115
116	return rate;
117}
118
119static unsigned long pll0_get_rate(struct clk *clk)
120{
121	u32 control;
122
123	control = sm_readl(&system_manager, PM_PLL0);
124
125	return pll_get_rate(clk, control);
126}
127
128static unsigned long pll1_get_rate(struct clk *clk)
129{
130	u32 control;
131
132	control = sm_readl(&system_manager, PM_PLL1);
133
134	return pll_get_rate(clk, control);
135}
136
137/*
138 * The AT32AP7000 has five primary clock sources: One 32kHz
139 * oscillator, two crystal oscillators and two PLLs.
140 */
141static struct clk osc32k = {
142	.name		= "osc32k",
143	.get_rate	= osc_get_rate,
144	.users		= 1,
145	.index		= 0,
146};
147static struct clk osc0 = {
148	.name		= "osc0",
149	.get_rate	= osc_get_rate,
150	.users		= 1,
151	.index		= 1,
152};
153static struct clk osc1 = {
154	.name		= "osc1",
155	.get_rate	= osc_get_rate,
156	.index		= 2,
157};
158static struct clk pll0 = {
159	.name		= "pll0",
160	.get_rate	= pll0_get_rate,
161	.parent		= &osc0,
162};
163static struct clk pll1 = {
164	.name		= "pll1",
165	.get_rate	= pll1_get_rate,
166	.parent		= &osc0,
167};
168
169/*
170 * The main clock can be either osc0 or pll0.  The boot loader may
171 * have chosen one for us, so we don't really know which one until we
172 * have a look at the SM.
173 */
174static struct clk *main_clock;
175
176/*
177 * Synchronous clocks are generated from the main clock. The clocks
178 * must satisfy the constraint
179 *   fCPU >= fHSB >= fPB
180 * i.e. each clock must not be faster than its parent.
181 */
182static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
183{
184	return main_clock->get_rate(main_clock) >> shift;
185};
186
187static void cpu_clk_mode(struct clk *clk, int enabled)
188{
189	struct at32_sm *sm = &system_manager;
190	unsigned long flags;
191	u32 mask;
192
193	spin_lock_irqsave(&sm->lock, flags);
194	mask = sm_readl(sm, PM_CPU_MASK);
195	if (enabled)
196		mask |= 1 << clk->index;
197	else
198		mask &= ~(1 << clk->index);
199	sm_writel(sm, PM_CPU_MASK, mask);
200	spin_unlock_irqrestore(&sm->lock, flags);
201}
202
203static unsigned long cpu_clk_get_rate(struct clk *clk)
204{
205	unsigned long cksel, shift = 0;
206
207	cksel = sm_readl(&system_manager, PM_CKSEL);
208	if (cksel & SM_BIT(CPUDIV))
209		shift = SM_BFEXT(CPUSEL, cksel) + 1;
210
211	return bus_clk_get_rate(clk, shift);
212}
213
214static void hsb_clk_mode(struct clk *clk, int enabled)
215{
216	struct at32_sm *sm = &system_manager;
217	unsigned long flags;
218	u32 mask;
219
220	spin_lock_irqsave(&sm->lock, flags);
221	mask = sm_readl(sm, PM_HSB_MASK);
222	if (enabled)
223		mask |= 1 << clk->index;
224	else
225		mask &= ~(1 << clk->index);
226	sm_writel(sm, PM_HSB_MASK, mask);
227	spin_unlock_irqrestore(&sm->lock, flags);
228}
229
230static unsigned long hsb_clk_get_rate(struct clk *clk)
231{
232	unsigned long cksel, shift = 0;
233
234	cksel = sm_readl(&system_manager, PM_CKSEL);
235	if (cksel & SM_BIT(HSBDIV))
236		shift = SM_BFEXT(HSBSEL, cksel) + 1;
237
238	return bus_clk_get_rate(clk, shift);
239}
240
241static void pba_clk_mode(struct clk *clk, int enabled)
242{
243	struct at32_sm *sm = &system_manager;
244	unsigned long flags;
245	u32 mask;
246
247	spin_lock_irqsave(&sm->lock, flags);
248	mask = sm_readl(sm, PM_PBA_MASK);
249	if (enabled)
250		mask |= 1 << clk->index;
251	else
252		mask &= ~(1 << clk->index);
253	sm_writel(sm, PM_PBA_MASK, mask);
254	spin_unlock_irqrestore(&sm->lock, flags);
255}
256
257static unsigned long pba_clk_get_rate(struct clk *clk)
258{
259	unsigned long cksel, shift = 0;
260
261	cksel = sm_readl(&system_manager, PM_CKSEL);
262	if (cksel & SM_BIT(PBADIV))
263		shift = SM_BFEXT(PBASEL, cksel) + 1;
264
265	return bus_clk_get_rate(clk, shift);
266}
267
268static void pbb_clk_mode(struct clk *clk, int enabled)
269{
270	struct at32_sm *sm = &system_manager;
271	unsigned long flags;
272	u32 mask;
273
274	spin_lock_irqsave(&sm->lock, flags);
275	mask = sm_readl(sm, PM_PBB_MASK);
276	if (enabled)
277		mask |= 1 << clk->index;
278	else
279		mask &= ~(1 << clk->index);
280	sm_writel(sm, PM_PBB_MASK, mask);
281	spin_unlock_irqrestore(&sm->lock, flags);
282}
283
284static unsigned long pbb_clk_get_rate(struct clk *clk)
285{
286	unsigned long cksel, shift = 0;
287
288	cksel = sm_readl(&system_manager, PM_CKSEL);
289	if (cksel & SM_BIT(PBBDIV))
290		shift = SM_BFEXT(PBBSEL, cksel) + 1;
291
292	return bus_clk_get_rate(clk, shift);
293}
294
295static struct clk cpu_clk = {
296	.name		= "cpu",
297	.get_rate	= cpu_clk_get_rate,
298	.users		= 1,
299};
300static struct clk hsb_clk = {
301	.name		= "hsb",
302	.parent		= &cpu_clk,
303	.get_rate	= hsb_clk_get_rate,
304};
305static struct clk pba_clk = {
306	.name		= "pba",
307	.parent		= &hsb_clk,
308	.mode		= hsb_clk_mode,
309	.get_rate	= pba_clk_get_rate,
310	.index		= 1,
311};
312static struct clk pbb_clk = {
313	.name		= "pbb",
314	.parent		= &hsb_clk,
315	.mode		= hsb_clk_mode,
316	.get_rate	= pbb_clk_get_rate,
317	.users		= 1,
318	.index		= 2,
319};
320
321/* --------------------------------------------------------------------
322 *  Generic Clock operations
323 * -------------------------------------------------------------------- */
324
325static void genclk_mode(struct clk *clk, int enabled)
326{
327	u32 control;
328
329	control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
330	if (enabled)
331		control |= SM_BIT(CEN);
332	else
333		control &= ~SM_BIT(CEN);
334	sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index, control);
335}
336
337static unsigned long genclk_get_rate(struct clk *clk)
338{
339	u32 control;
340	unsigned long div = 1;
341
342	control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
343	if (control & SM_BIT(DIVEN))
344		div = 2 * (SM_BFEXT(DIV, control) + 1);
345
346	return clk->parent->get_rate(clk->parent) / div;
347}
348
349static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
350{
351	u32 control;
352	unsigned long parent_rate, actual_rate, div;
353
354	parent_rate = clk->parent->get_rate(clk->parent);
355	control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
356
357	if (rate > 3 * parent_rate / 4) {
358		actual_rate = parent_rate;
359		control &= ~SM_BIT(DIVEN);
360	} else {
361		div = (parent_rate + rate) / (2 * rate) - 1;
362		control = SM_BFINS(DIV, div, control) | SM_BIT(DIVEN);
363		actual_rate = parent_rate / (2 * (div + 1));
364	}
365
366	printk("clk %s: new rate %lu (actual rate %lu)\n",
367	       clk->name, rate, actual_rate);
368
369	if (apply)
370		sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index,
371			  control);
372
373	return actual_rate;
374}
375
376int genclk_set_parent(struct clk *clk, struct clk *parent)
377{
378	u32 control;
379
380	printk("clk %s: new parent %s (was %s)\n",
381	       clk->name, parent->name, clk->parent->name);
382
383	control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
384
385	if (parent == &osc1 || parent == &pll1)
386		control |= SM_BIT(OSCSEL);
387	else if (parent == &osc0 || parent == &pll0)
388		control &= ~SM_BIT(OSCSEL);
389	else
390		return -EINVAL;
391
392	if (parent == &pll0 || parent == &pll1)
393		control |= SM_BIT(PLLSEL);
394	else
395		control &= ~SM_BIT(PLLSEL);
396
397	sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index, control);
398	clk->parent = parent;
399
400	return 0;
401}
402
403static void __init genclk_init_parent(struct clk *clk)
404{
405	u32 control;
406	struct clk *parent;
407
408	BUG_ON(clk->index > 7);
409
410	control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
411	if (control & SM_BIT(OSCSEL))
412		parent = (control & SM_BIT(PLLSEL)) ? &pll1 : &osc1;
413	else
414		parent = (control & SM_BIT(PLLSEL)) ? &pll0 : &osc0;
415
416	clk->parent = parent;
417}
418
419/* --------------------------------------------------------------------
420 *  System peripherals
421 * -------------------------------------------------------------------- */
422static struct resource sm_resource[] = {
423	PBMEM(0xfff00000),
424	NAMED_IRQ(19, "eim"),
425	NAMED_IRQ(20, "pm"),
426	NAMED_IRQ(21, "rtc"),
427};
428struct platform_device at32_sm_device = {
429	.name		= "sm",
430	.id		= 0,
431	.resource	= sm_resource,
432	.num_resources	= ARRAY_SIZE(sm_resource),
433};
434static struct clk at32_sm_pclk = {
435	.name		= "pclk",
436	.dev		= &at32_sm_device.dev,
437	.parent		= &pbb_clk,
438	.mode		= pbb_clk_mode,
439	.get_rate	= pbb_clk_get_rate,
440	.users		= 1,
441	.index		= 0,
442};
443
444static struct resource intc0_resource[] = {
445	PBMEM(0xfff00400),
446};
447struct platform_device at32_intc0_device = {
448	.name		= "intc",
449	.id		= 0,
450	.resource	= intc0_resource,
451	.num_resources	= ARRAY_SIZE(intc0_resource),
452};
453DEV_CLK(pclk, at32_intc0, pbb, 1);
454
455static struct clk ebi_clk = {
456	.name		= "ebi",
457	.parent		= &hsb_clk,
458	.mode		= hsb_clk_mode,
459	.get_rate	= hsb_clk_get_rate,
460	.users		= 1,
461};
462static struct clk hramc_clk = {
463	.name		= "hramc",
464	.parent		= &hsb_clk,
465	.mode		= hsb_clk_mode,
466	.get_rate	= hsb_clk_get_rate,
467	.users		= 1,
468	.index		= 3,
469};
470
471static struct resource smc0_resource[] = {
472	PBMEM(0xfff03400),
473};
474DEFINE_DEV(smc, 0);
475DEV_CLK(pclk, smc0, pbb, 13);
476DEV_CLK(mck, smc0, hsb, 0);
477
478static struct platform_device pdc_device = {
479	.name		= "pdc",
480	.id		= 0,
481};
482DEV_CLK(hclk, pdc, hsb, 4);
483DEV_CLK(pclk, pdc, pba, 16);
484
485static struct clk pico_clk = {
486	.name		= "pico",
487	.parent		= &cpu_clk,
488	.mode		= cpu_clk_mode,
489	.get_rate	= cpu_clk_get_rate,
490	.users		= 1,
491};
492
493/* --------------------------------------------------------------------
494 * HMATRIX
495 * -------------------------------------------------------------------- */
496
497static struct clk hmatrix_clk = {
498	.name		= "hmatrix_clk",
499	.parent		= &pbb_clk,
500	.mode		= pbb_clk_mode,
501	.get_rate	= pbb_clk_get_rate,
502	.index		= 2,
503	.users		= 1,
504};
505#define HMATRIX_BASE	((void __iomem *)0xfff00800)
506
507#define hmatrix_readl(reg)					\
508	__raw_readl((HMATRIX_BASE) + HMATRIX_##reg)
509#define hmatrix_writel(reg,value)				\
510	__raw_writel((value), (HMATRIX_BASE) + HMATRIX_##reg)
511
512/*
513 * Set bits in the HMATRIX Special Function Register (SFR) used by the
514 * External Bus Interface (EBI). This can be used to enable special
515 * features like CompactFlash support, NAND Flash support, etc. on
516 * certain chipselects.
517 */
518static inline void set_ebi_sfr_bits(u32 mask)
519{
520	u32 sfr;
521
522	clk_enable(&hmatrix_clk);
523	sfr = hmatrix_readl(SFR4);
524	sfr |= mask;
525	hmatrix_writel(SFR4, sfr);
526	clk_disable(&hmatrix_clk);
527}
528
529/* --------------------------------------------------------------------
530 *  System Timer/Counter (TC)
531 * -------------------------------------------------------------------- */
532static struct resource at32_systc0_resource[] = {
533	PBMEM(0xfff00c00),
534	IRQ(22),
535};
536struct platform_device at32_systc0_device = {
537	.name		= "systc",
538	.id		= 0,
539	.resource	= at32_systc0_resource,
540	.num_resources	= ARRAY_SIZE(at32_systc0_resource),
541};
542DEV_CLK(pclk, at32_systc0, pbb, 3);
543
544/* --------------------------------------------------------------------
545 *  PIO
546 * -------------------------------------------------------------------- */
547
548static struct resource pio0_resource[] = {
549	PBMEM(0xffe02800),
550	IRQ(13),
551};
552DEFINE_DEV(pio, 0);
553DEV_CLK(mck, pio0, pba, 10);
554
555static struct resource pio1_resource[] = {
556	PBMEM(0xffe02c00),
557	IRQ(14),
558};
559DEFINE_DEV(pio, 1);
560DEV_CLK(mck, pio1, pba, 11);
561
562static struct resource pio2_resource[] = {
563	PBMEM(0xffe03000),
564	IRQ(15),
565};
566DEFINE_DEV(pio, 2);
567DEV_CLK(mck, pio2, pba, 12);
568
569static struct resource pio3_resource[] = {
570	PBMEM(0xffe03400),
571	IRQ(16),
572};
573DEFINE_DEV(pio, 3);
574DEV_CLK(mck, pio3, pba, 13);
575
576static struct resource pio4_resource[] = {
577	PBMEM(0xffe03800),
578	IRQ(17),
579};
580DEFINE_DEV(pio, 4);
581DEV_CLK(mck, pio4, pba, 14);
582
583void __init at32_add_system_devices(void)
584{
585	system_manager.eim_first_irq = EIM_IRQ_BASE;
586
587	platform_device_register(&at32_sm_device);
588	platform_device_register(&at32_intc0_device);
589	platform_device_register(&smc0_device);
590	platform_device_register(&pdc_device);
591
592	platform_device_register(&at32_systc0_device);
593
594	platform_device_register(&pio0_device);
595	platform_device_register(&pio1_device);
596	platform_device_register(&pio2_device);
597	platform_device_register(&pio3_device);
598	platform_device_register(&pio4_device);
599}
600
601/* --------------------------------------------------------------------
602 *  USART
603 * -------------------------------------------------------------------- */
604
605static struct atmel_uart_data atmel_usart0_data = {
606	.use_dma_tx	= 1,
607	.use_dma_rx	= 1,
608};
609static struct resource atmel_usart0_resource[] = {
610	PBMEM(0xffe00c00),
611	IRQ(6),
612};
613DEFINE_DEV_DATA(atmel_usart, 0);
614DEV_CLK(usart, atmel_usart0, pba, 4);
615
616static struct atmel_uart_data atmel_usart1_data = {
617	.use_dma_tx	= 1,
618	.use_dma_rx	= 1,
619};
620static struct resource atmel_usart1_resource[] = {
621	PBMEM(0xffe01000),
622	IRQ(7),
623};
624DEFINE_DEV_DATA(atmel_usart, 1);
625DEV_CLK(usart, atmel_usart1, pba, 4);
626
627static struct atmel_uart_data atmel_usart2_data = {
628	.use_dma_tx	= 1,
629	.use_dma_rx	= 1,
630};
631static struct resource atmel_usart2_resource[] = {
632	PBMEM(0xffe01400),
633	IRQ(8),
634};
635DEFINE_DEV_DATA(atmel_usart, 2);
636DEV_CLK(usart, atmel_usart2, pba, 5);
637
638static struct atmel_uart_data atmel_usart3_data = {
639	.use_dma_tx	= 1,
640	.use_dma_rx	= 1,
641};
642static struct resource atmel_usart3_resource[] = {
643	PBMEM(0xffe01800),
644	IRQ(9),
645};
646DEFINE_DEV_DATA(atmel_usart, 3);
647DEV_CLK(usart, atmel_usart3, pba, 6);
648
649static inline void configure_usart0_pins(void)
650{
651	select_peripheral(PA(8),  PERIPH_B, 0);	/* RXD	*/
652	select_peripheral(PA(9),  PERIPH_B, 0);	/* TXD	*/
653}
654
655static inline void configure_usart1_pins(void)
656{
657	select_peripheral(PA(17), PERIPH_A, 0);	/* RXD	*/
658	select_peripheral(PA(18), PERIPH_A, 0);	/* TXD	*/
659}
660
661static inline void configure_usart2_pins(void)
662{
663	select_peripheral(PB(26), PERIPH_B, 0);	/* RXD	*/
664	select_peripheral(PB(27), PERIPH_B, 0);	/* TXD	*/
665}
666
667static inline void configure_usart3_pins(void)
668{
669	select_peripheral(PB(18), PERIPH_B, 0);	/* RXD	*/
670	select_peripheral(PB(17), PERIPH_B, 0);	/* TXD	*/
671}
672
673static struct platform_device *__initdata at32_usarts[4];
674
675void __init at32_map_usart(unsigned int hw_id, unsigned int line)
676{
677	struct platform_device *pdev;
678
679	switch (hw_id) {
680	case 0:
681		pdev = &atmel_usart0_device;
682		configure_usart0_pins();
683		break;
684	case 1:
685		pdev = &atmel_usart1_device;
686		configure_usart1_pins();
687		break;
688	case 2:
689		pdev = &atmel_usart2_device;
690		configure_usart2_pins();
691		break;
692	case 3:
693		pdev = &atmel_usart3_device;
694		configure_usart3_pins();
695		break;
696	default:
697		return;
698	}
699
700	if (PXSEG(pdev->resource[0].start) == P4SEG) {
701		/* Addresses in the P4 segment are permanently mapped 1:1 */
702		struct atmel_uart_data *data = pdev->dev.platform_data;
703		data->regs = (void __iomem *)pdev->resource[0].start;
704	}
705
706	pdev->id = line;
707	at32_usarts[line] = pdev;
708}
709
710struct platform_device *__init at32_add_device_usart(unsigned int id)
711{
712	platform_device_register(at32_usarts[id]);
713	return at32_usarts[id];
714}
715
716struct platform_device *atmel_default_console_device;
717
718void __init at32_setup_serial_console(unsigned int usart_id)
719{
720	atmel_default_console_device = at32_usarts[usart_id];
721}
722
723/* --------------------------------------------------------------------
724 *  Ethernet
725 * -------------------------------------------------------------------- */
726
727static struct eth_platform_data macb0_data;
728static struct resource macb0_resource[] = {
729	PBMEM(0xfff01800),
730	IRQ(25),
731};
732DEFINE_DEV_DATA(macb, 0);
733DEV_CLK(hclk, macb0, hsb, 8);
734DEV_CLK(pclk, macb0, pbb, 6);
735
736static struct eth_platform_data macb1_data;
737static struct resource macb1_resource[] = {
738	PBMEM(0xfff01c00),
739	IRQ(26),
740};
741DEFINE_DEV_DATA(macb, 1);
742DEV_CLK(hclk, macb1, hsb, 9);
743DEV_CLK(pclk, macb1, pbb, 7);
744
745struct platform_device *__init
746at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
747{
748	struct platform_device *pdev;
749
750	switch (id) {
751	case 0:
752		pdev = &macb0_device;
753
754		select_peripheral(PC(3),  PERIPH_A, 0);	/* TXD0	*/
755		select_peripheral(PC(4),  PERIPH_A, 0);	/* TXD1	*/
756		select_peripheral(PC(7),  PERIPH_A, 0);	/* TXEN	*/
757		select_peripheral(PC(8),  PERIPH_A, 0);	/* TXCK */
758		select_peripheral(PC(9),  PERIPH_A, 0);	/* RXD0	*/
759		select_peripheral(PC(10), PERIPH_A, 0);	/* RXD1	*/
760		select_peripheral(PC(13), PERIPH_A, 0);	/* RXER	*/
761		select_peripheral(PC(15), PERIPH_A, 0);	/* RXDV	*/
762		select_peripheral(PC(16), PERIPH_A, 0);	/* MDC	*/
763		select_peripheral(PC(17), PERIPH_A, 0);	/* MDIO	*/
764
765		if (!data->is_rmii) {
766			select_peripheral(PC(0),  PERIPH_A, 0);	/* COL	*/
767			select_peripheral(PC(1),  PERIPH_A, 0);	/* CRS	*/
768			select_peripheral(PC(2),  PERIPH_A, 0);	/* TXER	*/
769			select_peripheral(PC(5),  PERIPH_A, 0);	/* TXD2	*/
770			select_peripheral(PC(6),  PERIPH_A, 0);	/* TXD3 */
771			select_peripheral(PC(11), PERIPH_A, 0);	/* RXD2	*/
772			select_peripheral(PC(12), PERIPH_A, 0);	/* RXD3	*/
773			select_peripheral(PC(14), PERIPH_A, 0);	/* RXCK	*/
774			select_peripheral(PC(18), PERIPH_A, 0);	/* SPD	*/
775		}
776		break;
777
778	case 1:
779		pdev = &macb1_device;
780
781		select_peripheral(PD(13), PERIPH_B, 0);		/* TXD0	*/
782		select_peripheral(PD(14), PERIPH_B, 0);		/* TXD1	*/
783		select_peripheral(PD(11), PERIPH_B, 0);		/* TXEN	*/
784		select_peripheral(PD(12), PERIPH_B, 0);		/* TXCK */
785		select_peripheral(PD(10), PERIPH_B, 0);		/* RXD0	*/
786		select_peripheral(PD(6),  PERIPH_B, 0);		/* RXD1	*/
787		select_peripheral(PD(5),  PERIPH_B, 0);		/* RXER	*/
788		select_peripheral(PD(4),  PERIPH_B, 0);		/* RXDV	*/
789		select_peripheral(PD(3),  PERIPH_B, 0);		/* MDC	*/
790		select_peripheral(PD(2),  PERIPH_B, 0);		/* MDIO	*/
791
792		if (!data->is_rmii) {
793			select_peripheral(PC(19), PERIPH_B, 0);	/* COL	*/
794			select_peripheral(PC(23), PERIPH_B, 0);	/* CRS	*/
795			select_peripheral(PC(26), PERIPH_B, 0);	/* TXER	*/
796			select_peripheral(PC(27), PERIPH_B, 0);	/* TXD2	*/
797			select_peripheral(PC(28), PERIPH_B, 0);	/* TXD3 */
798			select_peripheral(PC(29), PERIPH_B, 0);	/* RXD2	*/
799			select_peripheral(PC(30), PERIPH_B, 0);	/* RXD3	*/
800			select_peripheral(PC(24), PERIPH_B, 0);	/* RXCK	*/
801			select_peripheral(PD(15), PERIPH_B, 0);	/* SPD	*/
802		}
803		break;
804
805	default:
806		return NULL;
807	}
808
809	memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
810	platform_device_register(pdev);
811
812	return pdev;
813}
814
815/* --------------------------------------------------------------------
816 *  SPI
817 * -------------------------------------------------------------------- */
818static struct resource atmel_spi0_resource[] = {
819	PBMEM(0xffe00000),
820	IRQ(3),
821};
822DEFINE_DEV(atmel_spi, 0);
823DEV_CLK(spi_clk, atmel_spi0, pba, 0);
824
825static struct resource atmel_spi1_resource[] = {
826	PBMEM(0xffe00400),
827	IRQ(4),
828};
829DEFINE_DEV(atmel_spi, 1);
830DEV_CLK(spi_clk, atmel_spi1, pba, 1);
831
832static void __init
833at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
834		      unsigned int n, const u8 *pins)
835{
836	unsigned int pin, mode;
837
838	for (; n; n--, b++) {
839		b->bus_num = bus_num;
840		if (b->chip_select >= 4)
841			continue;
842		pin = (unsigned)b->controller_data;
843		if (!pin) {
844			pin = pins[b->chip_select];
845			b->controller_data = (void *)pin;
846		}
847		mode = AT32_GPIOF_OUTPUT;
848		if (!(b->mode & SPI_CS_HIGH))
849			mode |= AT32_GPIOF_HIGH;
850		at32_select_gpio(pin, mode);
851	}
852}
853
854struct platform_device *__init
855at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
856{
857	/*
858	 * Manage the chipselects as GPIOs, normally using the same pins
859	 * the SPI controller expects; but boards can use other pins.
860	 */
861	static u8 __initdata spi0_pins[] =
862		{ GPIO_PIN_PA(3), GPIO_PIN_PA(4),
863		  GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
864	static u8 __initdata spi1_pins[] =
865		{ GPIO_PIN_PB(2), GPIO_PIN_PB(3),
866		  GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
867	struct platform_device *pdev;
868
869	switch (id) {
870	case 0:
871		pdev = &atmel_spi0_device;
872		select_peripheral(PA(0),  PERIPH_A, 0);	/* MISO	 */
873		select_peripheral(PA(1),  PERIPH_A, 0);	/* MOSI	 */
874		select_peripheral(PA(2),  PERIPH_A, 0);	/* SCK	 */
875		at32_spi_setup_slaves(0, b, n, spi0_pins);
876		break;
877
878	case 1:
879		pdev = &atmel_spi1_device;
880		select_peripheral(PB(0),  PERIPH_B, 0);	/* MISO  */
881		select_peripheral(PB(1),  PERIPH_B, 0);	/* MOSI  */
882		select_peripheral(PB(5),  PERIPH_B, 0);	/* SCK   */
883		at32_spi_setup_slaves(1, b, n, spi1_pins);
884		break;
885
886	default:
887		return NULL;
888	}
889
890	spi_register_board_info(b, n);
891	platform_device_register(pdev);
892	return pdev;
893}
894
895/* --------------------------------------------------------------------
896 *  LCDC
897 * -------------------------------------------------------------------- */
898static struct atmel_lcdfb_info atmel_lcdfb0_data;
899static struct resource atmel_lcdfb0_resource[] = {
900	{
901		.start		= 0xff000000,
902		.end		= 0xff000fff,
903		.flags		= IORESOURCE_MEM,
904	},
905	IRQ(1),
906	{
907		/* Placeholder for pre-allocated fb memory */
908		.start		= 0x00000000,
909		.end		= 0x00000000,
910		.flags		= 0,
911	},
912};
913DEFINE_DEV_DATA(atmel_lcdfb, 0);
914DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
915static struct clk atmel_lcdfb0_pixclk = {
916	.name		= "lcdc_clk",
917	.dev		= &atmel_lcdfb0_device.dev,
918	.mode		= genclk_mode,
919	.get_rate	= genclk_get_rate,
920	.set_rate	= genclk_set_rate,
921	.set_parent	= genclk_set_parent,
922	.index		= 7,
923};
924
925struct platform_device *__init
926at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
927		     unsigned long fbmem_start, unsigned long fbmem_len)
928{
929	struct platform_device *pdev;
930	struct atmel_lcdfb_info *info;
931	struct fb_monspecs *monspecs;
932	struct fb_videomode *modedb;
933	unsigned int modedb_size;
934
935	/*
936	 * Do a deep copy of the fb data, monspecs and modedb. Make
937	 * sure all allocations are done before setting up the
938	 * portmux.
939	 */
940	monspecs = kmemdup(data->default_monspecs,
941			   sizeof(struct fb_monspecs), GFP_KERNEL);
942	if (!monspecs)
943		return NULL;
944
945	modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
946	modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
947	if (!modedb)
948		goto err_dup_modedb;
949	monspecs->modedb = modedb;
950
951	switch (id) {
952	case 0:
953		pdev = &atmel_lcdfb0_device;
954		select_peripheral(PC(19), PERIPH_A, 0);	/* CC	  */
955		select_peripheral(PC(20), PERIPH_A, 0);	/* HSYNC  */
956		select_peripheral(PC(21), PERIPH_A, 0);	/* PCLK	  */
957		select_peripheral(PC(22), PERIPH_A, 0);	/* VSYNC  */
958		select_peripheral(PC(23), PERIPH_A, 0);	/* DVAL	  */
959		select_peripheral(PC(24), PERIPH_A, 0);	/* MODE	  */
960		select_peripheral(PC(25), PERIPH_A, 0);	/* PWR	  */
961		select_peripheral(PC(26), PERIPH_A, 0);	/* DATA0  */
962		select_peripheral(PC(27), PERIPH_A, 0);	/* DATA1  */
963		select_peripheral(PC(28), PERIPH_A, 0);	/* DATA2  */
964		select_peripheral(PC(29), PERIPH_A, 0);	/* DATA3  */
965		select_peripheral(PC(30), PERIPH_A, 0);	/* DATA4  */
966		select_peripheral(PC(31), PERIPH_A, 0);	/* DATA5  */
967		select_peripheral(PD(0),  PERIPH_A, 0);	/* DATA6  */
968		select_peripheral(PD(1),  PERIPH_A, 0);	/* DATA7  */
969		select_peripheral(PD(2),  PERIPH_A, 0);	/* DATA8  */
970		select_peripheral(PD(3),  PERIPH_A, 0);	/* DATA9  */
971		select_peripheral(PD(4),  PERIPH_A, 0);	/* DATA10 */
972		select_peripheral(PD(5),  PERIPH_A, 0);	/* DATA11 */
973		select_peripheral(PD(6),  PERIPH_A, 0);	/* DATA12 */
974		select_peripheral(PD(7),  PERIPH_A, 0);	/* DATA13 */
975		select_peripheral(PD(8),  PERIPH_A, 0);	/* DATA14 */
976		select_peripheral(PD(9),  PERIPH_A, 0);	/* DATA15 */
977		select_peripheral(PD(10), PERIPH_A, 0);	/* DATA16 */
978		select_peripheral(PD(11), PERIPH_A, 0);	/* DATA17 */
979		select_peripheral(PD(12), PERIPH_A, 0);	/* DATA18 */
980		select_peripheral(PD(13), PERIPH_A, 0);	/* DATA19 */
981		select_peripheral(PD(14), PERIPH_A, 0);	/* DATA20 */
982		select_peripheral(PD(15), PERIPH_A, 0);	/* DATA21 */
983		select_peripheral(PD(16), PERIPH_A, 0);	/* DATA22 */
984		select_peripheral(PD(17), PERIPH_A, 0);	/* DATA23 */
985
986		clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
987		clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
988		break;
989
990	default:
991		goto err_invalid_id;
992	}
993
994	if (fbmem_len) {
995		pdev->resource[2].start = fbmem_start;
996		pdev->resource[2].end = fbmem_start + fbmem_len - 1;
997		pdev->resource[2].flags = IORESOURCE_MEM;
998	}
999
1000	info = pdev->dev.platform_data;
1001	memcpy(info, data, sizeof(struct atmel_lcdfb_info));
1002	info->default_monspecs = monspecs;
1003
1004	platform_device_register(pdev);
1005	return pdev;
1006
1007err_invalid_id:
1008	kfree(modedb);
1009err_dup_modedb:
1010	kfree(monspecs);
1011	return NULL;
1012}
1013
1014/* --------------------------------------------------------------------
1015 *  GCLK
1016 * -------------------------------------------------------------------- */
1017static struct clk gclk0 = {
1018	.name		= "gclk0",
1019	.mode		= genclk_mode,
1020	.get_rate	= genclk_get_rate,
1021	.set_rate	= genclk_set_rate,
1022	.set_parent	= genclk_set_parent,
1023	.index		= 0,
1024};
1025static struct clk gclk1 = {
1026	.name		= "gclk1",
1027	.mode		= genclk_mode,
1028	.get_rate	= genclk_get_rate,
1029	.set_rate	= genclk_set_rate,
1030	.set_parent	= genclk_set_parent,
1031	.index		= 1,
1032};
1033static struct clk gclk2 = {
1034	.name		= "gclk2",
1035	.mode		= genclk_mode,
1036	.get_rate	= genclk_get_rate,
1037	.set_rate	= genclk_set_rate,
1038	.set_parent	= genclk_set_parent,
1039	.index		= 2,
1040};
1041static struct clk gclk3 = {
1042	.name		= "gclk3",
1043	.mode		= genclk_mode,
1044	.get_rate	= genclk_get_rate,
1045	.set_rate	= genclk_set_rate,
1046	.set_parent	= genclk_set_parent,
1047	.index		= 3,
1048};
1049static struct clk gclk4 = {
1050	.name		= "gclk4",
1051	.mode		= genclk_mode,
1052	.get_rate	= genclk_get_rate,
1053	.set_rate	= genclk_set_rate,
1054	.set_parent	= genclk_set_parent,
1055	.index		= 4,
1056};
1057
1058struct clk *at32_clock_list[] = {
1059	&osc32k,
1060	&osc0,
1061	&osc1,
1062	&pll0,
1063	&pll1,
1064	&cpu_clk,
1065	&hsb_clk,
1066	&pba_clk,
1067	&pbb_clk,
1068	&at32_sm_pclk,
1069	&at32_intc0_pclk,
1070	&hmatrix_clk,
1071	&ebi_clk,
1072	&hramc_clk,
1073	&smc0_pclk,
1074	&smc0_mck,
1075	&pdc_hclk,
1076	&pdc_pclk,
1077	&pico_clk,
1078	&pio0_mck,
1079	&pio1_mck,
1080	&pio2_mck,
1081	&pio3_mck,
1082	&pio4_mck,
1083	&at32_systc0_pclk,
1084	&atmel_usart0_usart,
1085	&atmel_usart1_usart,
1086	&atmel_usart2_usart,
1087	&atmel_usart3_usart,
1088	&macb0_hclk,
1089	&macb0_pclk,
1090	&macb1_hclk,
1091	&macb1_pclk,
1092	&atmel_spi0_spi_clk,
1093	&atmel_spi1_spi_clk,
1094	&atmel_lcdfb0_hck1,
1095	&atmel_lcdfb0_pixclk,
1096	&gclk0,
1097	&gclk1,
1098	&gclk2,
1099	&gclk3,
1100	&gclk4,
1101};
1102unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
1103
1104void __init at32_portmux_init(void)
1105{
1106	at32_init_pio(&pio0_device);
1107	at32_init_pio(&pio1_device);
1108	at32_init_pio(&pio2_device);
1109	at32_init_pio(&pio3_device);
1110	at32_init_pio(&pio4_device);
1111}
1112
1113void __init at32_clock_init(void)
1114{
1115	struct at32_sm *sm = &system_manager;
1116	u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
1117	int i;
1118
1119	if (sm_readl(sm, PM_MCCTRL) & SM_BIT(PLLSEL))
1120		main_clock = &pll0;
1121	else
1122		main_clock = &osc0;
1123
1124	if (sm_readl(sm, PM_PLL0) & SM_BIT(PLLOSC))
1125		pll0.parent = &osc1;
1126	if (sm_readl(sm, PM_PLL1) & SM_BIT(PLLOSC))
1127		pll1.parent = &osc1;
1128
1129	genclk_init_parent(&gclk0);
1130	genclk_init_parent(&gclk1);
1131	genclk_init_parent(&gclk2);
1132	genclk_init_parent(&gclk3);
1133	genclk_init_parent(&gclk4);
1134	genclk_init_parent(&atmel_lcdfb0_pixclk);
1135
1136	/*
1137	 * Turn on all clocks that have at least one user already, and
1138	 * turn off everything else. We only do this for module
1139	 * clocks, and even though it isn't particularly pretty to
1140	 * check the address of the mode function, it should do the
1141	 * trick...
1142	 */
1143	for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
1144		struct clk *clk = at32_clock_list[i];
1145
1146		if (clk->users == 0)
1147			continue;
1148
1149		if (clk->mode == &cpu_clk_mode)
1150			cpu_mask |= 1 << clk->index;
1151		else if (clk->mode == &hsb_clk_mode)
1152			hsb_mask |= 1 << clk->index;
1153		else if (clk->mode == &pba_clk_mode)
1154			pba_mask |= 1 << clk->index;
1155		else if (clk->mode == &pbb_clk_mode)
1156			pbb_mask |= 1 << clk->index;
1157	}
1158
1159	sm_writel(sm, PM_CPU_MASK, cpu_mask);
1160	sm_writel(sm, PM_HSB_MASK, hsb_mask);
1161	sm_writel(sm, PM_PBA_MASK, pba_mask);
1162	sm_writel(sm, PM_PBB_MASK, pbb_mask);
1163}
1164