1/*
2 *  linux/arch/arm/lib/copypage-armv4mc.S
3 *
4 *  Copyright (C) 1995-2005 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This handles the mini data cache, as found on SA11x0 and XScale
11 * processors.  When we copy a user page page, we map it in such a way
12 * that accesses to this page will not touch the main data cache, but
13 * will be cached in the mini data cache.  This prevents us thrashing
14 * the main data cache on page faults.
15 */
16#include <linux/init.h>
17#include <linux/mm.h>
18
19#include <asm/page.h>
20#include <asm/pgtable.h>
21#include <asm/tlbflush.h>
22#include <asm/cacheflush.h>
23
24#include "mm.h"
25
26/*
27 * 0xffff8000 to 0xffffffff is reserved for any ARM architecture
28 * specific hacks for copying pages efficiently.
29 */
30#define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \
31				  L_PTE_CACHEABLE)
32
33static DEFINE_SPINLOCK(minicache_lock);
34
35/*
36 * ARMv4 mini-dcache optimised copy_user_page
37 *
38 * We flush the destination cache lines just before we write the data into the
39 * corresponding address.  Since the Dcache is read-allocate, this removes the
40 * Dcache aliasing issue.  The writes will be forwarded to the write buffer,
41 * and merged as appropriate.
42 *
43 * Note: We rely on all ARMv4 processors implementing the "invalidate D line"
44 * instruction.  If your processor does not supply this, you have to write your
45 * own copy_user_page that does the right thing.
46 */
47static void __attribute__((naked))
48mc_copy_user_page(void *from, void *to)
49{
50	asm volatile(
51	"stmfd	sp!, {r4, lr}			@ 2\n\
52	mov	r4, %2				@ 1\n\
53	ldmia	%0!, {r2, r3, ip, lr}		@ 4\n\
541:	mcr	p15, 0, %1, c7, c6, 1		@ 1   invalidate D line\n\
55	stmia	%1!, {r2, r3, ip, lr}		@ 4\n\
56	ldmia	%0!, {r2, r3, ip, lr}		@ 4+1\n\
57	stmia	%1!, {r2, r3, ip, lr}		@ 4\n\
58	ldmia	%0!, {r2, r3, ip, lr}		@ 4\n\
59	mcr	p15, 0, %1, c7, c6, 1		@ 1   invalidate D line\n\
60	stmia	%1!, {r2, r3, ip, lr}		@ 4\n\
61	ldmia	%0!, {r2, r3, ip, lr}		@ 4\n\
62	subs	r4, r4, #1			@ 1\n\
63	stmia	%1!, {r2, r3, ip, lr}		@ 4\n\
64	ldmneia	%0!, {r2, r3, ip, lr}		@ 4\n\
65	bne	1b				@ 1\n\
66	ldmfd	sp!, {r4, pc}			@ 3"
67	:
68	: "r" (from), "r" (to), "I" (PAGE_SIZE / 64));
69}
70
71void v4_mc_copy_user_page(void *kto, const void *kfrom, unsigned long vaddr)
72{
73	struct page *page = virt_to_page(kfrom);
74
75	if (test_and_clear_bit(PG_dcache_dirty, &page->flags))
76		__flush_dcache_page(page_mapping(page), page);
77
78	spin_lock(&minicache_lock);
79
80	set_pte_ext(TOP_PTE(0xffff8000), pfn_pte(__pa(kfrom) >> PAGE_SHIFT, minicache_pgprot), 0);
81	flush_tlb_kernel_page(0xffff8000);
82
83	mc_copy_user_page((void *)0xffff8000, kto);
84
85	spin_unlock(&minicache_lock);
86}
87
88/*
89 * ARMv4 optimised clear_user_page
90 */
91void __attribute__((naked))
92v4_mc_clear_user_page(void *kaddr, unsigned long vaddr)
93{
94	asm volatile(
95	"str	lr, [sp, #-4]!\n\
96	mov	r1, %0				@ 1\n\
97	mov	r2, #0				@ 1\n\
98	mov	r3, #0				@ 1\n\
99	mov	ip, #0				@ 1\n\
100	mov	lr, #0				@ 1\n\
1011:	mcr	p15, 0, r0, c7, c6, 1		@ 1   invalidate D line\n\
102	stmia	r0!, {r2, r3, ip, lr}		@ 4\n\
103	stmia	r0!, {r2, r3, ip, lr}		@ 4\n\
104	mcr	p15, 0, r0, c7, c6, 1		@ 1   invalidate D line\n\
105	stmia	r0!, {r2, r3, ip, lr}		@ 4\n\
106	stmia	r0!, {r2, r3, ip, lr}		@ 4\n\
107	subs	r1, r1, #1			@ 1\n\
108	bne	1b				@ 1\n\
109	ldr	pc, [sp], #4"
110	:
111	: "I" (PAGE_SIZE / 64));
112}
113
114struct cpu_user_fns v4_mc_user_fns __initdata = {
115	.cpu_clear_user_page	= v4_mc_clear_user_page,
116	.cpu_copy_user_page	= v4_mc_copy_user_page,
117};
118