1/* 2 * cpu-sa1100.c: clock scaling for the SA1100 3 * 4 * Copyright (C) 2000 2001, The Delft University of Technology 5 * 6 * Authors: 7 * - Johan Pouwelse (J.A.Pouwelse@its.tudelft.nl): initial version 8 * - Erik Mouw (J.A.K.Mouw@its.tudelft.nl): 9 * - major rewrite for linux-2.3.99 10 * - rewritten for the more generic power management scheme in 11 * linux-2.4.5-rmk1 12 * 13 * This software has been developed while working on the LART 14 * computing board (http://www.lartmaker.nl/), which is 15 * sponsored by the Mobile Multi-media Communications 16 * (http://www.mmc.tudelft.nl/) and Ubiquitous Communications 17 * (http://www.ubicom.tudelft.nl/) projects. 18 * 19 * The authors can be reached at: 20 * 21 * Erik Mouw 22 * Information and Communication Theory Group 23 * Faculty of Information Technology and Systems 24 * Delft University of Technology 25 * P.O. Box 5031 26 * 2600 GA Delft 27 * The Netherlands 28 * 29 * 30 * This program is free software; you can redistribute it and/or modify 31 * it under the terms of the GNU General Public License as published by 32 * the Free Software Foundation; either version 2 of the License, or 33 * (at your option) any later version. 34 * 35 * This program is distributed in the hope that it will be useful, 36 * but WITHOUT ANY WARRANTY; without even the implied warranty of 37 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 38 * GNU General Public License for more details. 39 * 40 * You should have received a copy of the GNU General Public License 41 * along with this program; if not, write to the Free Software 42 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 43 * 44 * 45 * Theory of operations 46 * ==================== 47 * 48 * Clock scaling can be used to lower the power consumption of the CPU 49 * core. This will give you a somewhat longer running time. 50 * 51 * The SA-1100 has a single register to change the core clock speed: 52 * 53 * PPCR 0x90020014 PLL config 54 * 55 * However, the DRAM timings are closely related to the core clock 56 * speed, so we need to change these, too. The used registers are: 57 * 58 * MDCNFG 0xA0000000 DRAM config 59 * MDCAS0 0xA0000004 Access waveform 60 * MDCAS1 0xA0000008 Access waveform 61 * MDCAS2 0xA000000C Access waveform 62 * 63 * Care must be taken to change the DRAM parameters the correct way, 64 * because otherwise the DRAM becomes unusable and the kernel will 65 * crash. 66 * 67 * The simple solution to avoid a kernel crash is to put the actual 68 * clock change in ROM and jump to that code from the kernel. The main 69 * disadvantage is that the ROM has to be modified, which is not 70 * possible on all SA-1100 platforms. Another disadvantage is that 71 * jumping to ROM makes clock switching unecessary complicated. 72 * 73 * The idea behind this driver is that the memory configuration can be 74 * changed while running from DRAM (even with interrupts turned on!) 75 * as long as all re-configuration steps yield a valid DRAM 76 * configuration. The advantages are clear: it will run on all SA-1100 77 * platforms, and the code is very simple. 78 * 79 * If you really want to understand what is going on in 80 * sa1100_update_dram_timings(), you'll have to read sections 8.2, 81 * 9.5.7.3, and 10.2 from the "Intel StrongARM SA-1100 Microprocessor 82 * Developers Manual" (available for free from Intel). 83 * 84 */ 85 86#include <linux/kernel.h> 87#include <linux/types.h> 88#include <linux/init.h> 89#include <linux/cpufreq.h> 90 91#include <asm/hardware.h> 92 93#include "generic.h" 94 95typedef struct { 96 int speed; 97 u32 mdcnfg; 98 u32 mdcas0; 99 u32 mdcas1; 100 u32 mdcas2; 101} sa1100_dram_regs_t; 102 103 104static struct cpufreq_driver sa1100_driver; 105 106static sa1100_dram_regs_t sa1100_dram_settings[] = 107{ 108 /* speed, mdcnfg, mdcas0, mdcas1, mdcas2 clock frequency */ 109 { 59000, 0x00dc88a3, 0xcccccccf, 0xfffffffc, 0xffffffff }, /* 59.0 MHz */ 110 { 73700, 0x011490a3, 0xcccccccf, 0xfffffffc, 0xffffffff }, /* 73.7 MHz */ 111 { 88500, 0x014e90a3, 0xcccccccf, 0xfffffffc, 0xffffffff }, /* 88.5 MHz */ 112 { 103200, 0x01889923, 0xcccccccf, 0xfffffffc, 0xffffffff }, /* 103.2 MHz */ 113 { 118000, 0x01c29923, 0x9999998f, 0xfffffff9, 0xffffffff }, /* 118.0 MHz */ 114 { 132700, 0x01fb2123, 0x9999998f, 0xfffffff9, 0xffffffff }, /* 132.7 MHz */ 115 { 147500, 0x02352123, 0x3333330f, 0xfffffff3, 0xffffffff }, /* 147.5 MHz */ 116 { 162200, 0x026b29a3, 0x38e38e1f, 0xfff8e38e, 0xffffffff }, /* 162.2 MHz */ 117 { 176900, 0x02a329a3, 0x71c71c1f, 0xfff1c71c, 0xffffffff }, /* 176.9 MHz */ 118 { 191700, 0x02dd31a3, 0xe38e383f, 0xffe38e38, 0xffffffff }, /* 191.7 MHz */ 119 { 206400, 0x03153223, 0xc71c703f, 0xffc71c71, 0xffffffff }, /* 206.4 MHz */ 120 { 221200, 0x034fba23, 0xc71c703f, 0xffc71c71, 0xffffffff }, /* 221.2 MHz */ 121 { 235900, 0x03853a23, 0xe1e1e07f, 0xe1e1e1e1, 0xffffffe1 }, /* 235.9 MHz */ 122 { 250700, 0x03bf3aa3, 0xc3c3c07f, 0xc3c3c3c3, 0xffffffc3 }, /* 250.7 MHz */ 123 { 265400, 0x03f7c2a3, 0xc3c3c07f, 0xc3c3c3c3, 0xffffffc3 }, /* 265.4 MHz */ 124 { 280200, 0x0431c2a3, 0x878780ff, 0x87878787, 0xffffff87 }, /* 280.2 MHz */ 125 { 0, 0, 0, 0, 0 } /* last entry */ 126}; 127 128static void sa1100_update_dram_timings(int current_speed, int new_speed) 129{ 130 sa1100_dram_regs_t *settings = sa1100_dram_settings; 131 132 /* find speed */ 133 while (settings->speed != 0) { 134 if(new_speed == settings->speed) 135 break; 136 137 settings++; 138 } 139 140 if (settings->speed == 0) { 141 panic("%s: couldn't find dram setting for speed %d\n", 142 __FUNCTION__, new_speed); 143 } 144 145 /* No risk, no fun: run with interrupts on! */ 146 if (new_speed > current_speed) { 147 /* We're going FASTER, so first relax the memory 148 * timings before changing the core frequency 149 */ 150 151 /* Half the memory access clock */ 152 MDCNFG |= MDCNFG_CDB2; 153 154 /* The order of these statements IS important, keep 8 155 * pulses!! 156 */ 157 MDCAS2 = settings->mdcas2; 158 MDCAS1 = settings->mdcas1; 159 MDCAS0 = settings->mdcas0; 160 MDCNFG = settings->mdcnfg; 161 } else { 162 /* We're going SLOWER: first decrease the core 163 * frequency and then tighten the memory settings. 164 */ 165 166 /* Half the memory access clock */ 167 MDCNFG |= MDCNFG_CDB2; 168 169 /* The order of these statements IS important, keep 8 170 * pulses!! 171 */ 172 MDCAS0 = settings->mdcas0; 173 MDCAS1 = settings->mdcas1; 174 MDCAS2 = settings->mdcas2; 175 MDCNFG = settings->mdcnfg; 176 } 177} 178 179static int sa1100_target(struct cpufreq_policy *policy, 180 unsigned int target_freq, 181 unsigned int relation) 182{ 183 unsigned int cur = sa11x0_getspeed(0); 184 unsigned int new_ppcr; 185 186 struct cpufreq_freqs freqs; 187 switch(relation){ 188 case CPUFREQ_RELATION_L: 189 new_ppcr = sa11x0_freq_to_ppcr(target_freq); 190 if (sa11x0_ppcr_to_freq(new_ppcr) > policy->max) 191 new_ppcr--; 192 break; 193 case CPUFREQ_RELATION_H: 194 new_ppcr = sa11x0_freq_to_ppcr(target_freq); 195 if ((sa11x0_ppcr_to_freq(new_ppcr) > target_freq) && 196 (sa11x0_ppcr_to_freq(new_ppcr - 1) >= policy->min)) 197 new_ppcr--; 198 break; 199 } 200 201 freqs.old = cur; 202 freqs.new = sa11x0_ppcr_to_freq(new_ppcr); 203 freqs.cpu = 0; 204 205 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); 206 207 if (freqs.new > cur) 208 sa1100_update_dram_timings(cur, freqs.new); 209 210 PPCR = new_ppcr; 211 212 if (freqs.new < cur) 213 sa1100_update_dram_timings(cur, freqs.new); 214 215 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); 216 217 return 0; 218} 219 220static int __init sa1100_cpu_init(struct cpufreq_policy *policy) 221{ 222 if (policy->cpu != 0) 223 return -EINVAL; 224 policy->cur = policy->min = policy->max = sa11x0_getspeed(0); 225 policy->governor = CPUFREQ_DEFAULT_GOVERNOR; 226 policy->cpuinfo.min_freq = 59000; 227 policy->cpuinfo.max_freq = 287000; 228 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; 229 return 0; 230} 231 232static struct cpufreq_driver sa1100_driver = { 233 .flags = CPUFREQ_STICKY, 234 .verify = sa11x0_verify_speed, 235 .target = sa1100_target, 236 .get = sa11x0_getspeed, 237 .init = sa1100_cpu_init, 238 .name = "sa1100", 239}; 240 241static int __init sa1100_dram_init(void) 242{ 243 if ((processor_id & CPU_SA1100_MASK) == CPU_SA1100_ID) 244 return cpufreq_register_driver(&sa1100_driver); 245 else 246 return -ENODEV; 247} 248 249arch_initcall(sa1100_dram_init); 250