1/*
2 * linux/arch/arm/mach-omap2/irq.c
3 *
4 * Interrupt handler for OMAP2 boards.
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/interrupt.h>
16#include <asm/hardware.h>
17#include <asm/mach/irq.h>
18#include <asm/irq.h>
19#include <asm/io.h>
20
21#define INTC_REVISION	0x0000
22#define INTC_SYSCONFIG	0x0010
23#define INTC_SYSSTATUS	0x0014
24#define INTC_CONTROL	0x0048
25#define INTC_MIR_CLEAR0	0x0088
26#define INTC_MIR_SET0	0x008c
27
28/*
29 * OMAP2 has a number of different interrupt controllers, each interrupt
30 * controller is identified as its own "bank". Register definitions are
31 * fairly consistent for each bank, but not all registers are implemented
32 * for each bank.. when in doubt, consult the TRM.
33 */
34static struct omap_irq_bank {
35	unsigned long base_reg;
36	unsigned int nr_irqs;
37} __attribute__ ((aligned(4))) irq_banks[] = {
38	{
39		/* MPU INTC */
40		.base_reg	= OMAP24XX_IC_BASE,
41		.nr_irqs	= 96,
42	}, {
43	}
44};
45
46static void omap_ack_irq(unsigned int irq)
47{
48	omap_writel(0x1, irq_banks[0].base_reg + INTC_CONTROL);
49}
50
51static void omap_mask_irq(unsigned int irq)
52{
53	int offset = (irq >> 5) << 5;
54
55	if (irq >= 64) {
56		irq %= 64;
57	} else if (irq >= 32) {
58		irq %= 32;
59	}
60
61	omap_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_SET0 + offset);
62}
63
64static void omap_unmask_irq(unsigned int irq)
65{
66	int offset = (irq >> 5) << 5;
67
68	if (irq >= 64) {
69		irq %= 64;
70	} else if (irq >= 32) {
71		irq %= 32;
72	}
73
74	omap_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_CLEAR0 + offset);
75}
76
77static void omap_mask_ack_irq(unsigned int irq)
78{
79	omap_mask_irq(irq);
80	omap_ack_irq(irq);
81}
82
83static struct irq_chip omap_irq_chip = {
84	.name	= "INTC",
85	.ack	= omap_mask_ack_irq,
86	.mask	= omap_mask_irq,
87	.unmask	= omap_unmask_irq,
88};
89
90static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
91{
92	unsigned long tmp;
93
94	tmp = omap_readl(bank->base_reg + INTC_REVISION) & 0xff;
95	printk(KERN_INFO "IRQ: Found an INTC at 0x%08lx "
96			 "(revision %ld.%ld) with %d interrupts\n",
97			 bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
98
99	tmp = omap_readl(bank->base_reg + INTC_SYSCONFIG);
100	tmp |= 1 << 1;	/* soft reset */
101	omap_writel(tmp, bank->base_reg + INTC_SYSCONFIG);
102
103	while (!(omap_readl(bank->base_reg + INTC_SYSSTATUS) & 0x1))
104		/* Wait for reset to complete */;
105}
106
107void __init omap_init_irq(void)
108{
109	unsigned long nr_irqs = 0;
110	unsigned int nr_banks = 0;
111	int i;
112
113	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
114		struct omap_irq_bank *bank = irq_banks + i;
115
116		if (!bank->base_reg)
117			continue;
118
119		omap_irq_bank_init_one(bank);
120
121		nr_irqs += bank->nr_irqs;
122		nr_banks++;
123	}
124
125	printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
126	       nr_irqs, nr_banks, nr_banks > 1 ? "s" : "");
127
128	for (i = 0; i < nr_irqs; i++) {
129		set_irq_chip(i, &omap_irq_chip);
130		set_irq_handler(i, handle_level_irq);
131		set_irq_flags(i, IRQF_VALID);
132	}
133}
134