1/* 2 * iop13xx PCI support 3 * Copyright (c) 2005-2006, Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple 16 * Place - Suite 330, Boston, MA 02111-1307 USA. 17 * 18 */ 19 20#include <linux/pci.h> 21#include <linux/delay.h> 22#include <linux/jiffies.h> 23#include <asm/irq.h> 24#include <asm/hardware.h> 25#include <asm/sizes.h> 26#include <asm/signal.h> 27#include <asm/mach/pci.h> 28#include <asm/arch/pci.h> 29 30#define IOP13XX_PCI_DEBUG 0 31#define PRINTK(x...) ((void)(IOP13XX_PCI_DEBUG && printk(x))) 32 33u32 iop13xx_atux_pmmr_offset; /* This offset can change based on strapping */ 34u32 iop13xx_atue_pmmr_offset; /* This offset can change based on strapping */ 35static struct pci_bus *pci_bus_atux = 0; 36static struct pci_bus *pci_bus_atue = 0; 37u32 iop13xx_atue_mem_base; 38u32 iop13xx_atux_mem_base; 39size_t iop13xx_atue_mem_size; 40size_t iop13xx_atux_mem_size; 41unsigned long iop13xx_pcibios_min_io = 0; 42unsigned long iop13xx_pcibios_min_mem = 0; 43 44EXPORT_SYMBOL(iop13xx_atue_mem_base); 45EXPORT_SYMBOL(iop13xx_atux_mem_base); 46EXPORT_SYMBOL(iop13xx_atue_mem_size); 47EXPORT_SYMBOL(iop13xx_atux_mem_size); 48 49int init_atu = 0; /* Flag to select which ATU(s) to initialize / disable */ 50static unsigned long atux_trhfa_timeout = 0; /* Trhfa = RST# high to first 51 access */ 52 53/* Scan the initialized busses and ioremap the requested memory range 54 */ 55void iop13xx_map_pci_memory(void) 56{ 57 int atu; 58 struct pci_bus *bus; 59 struct pci_dev *dev; 60 resource_size_t end = 0; 61 62 for (atu = 0; atu < 2; atu++) { 63 bus = atu ? pci_bus_atue : pci_bus_atux; 64 if (bus) { 65 list_for_each_entry(dev, &bus->devices, bus_list) { 66 int i; 67 int max = 7; 68 69 if (dev->subordinate) 70 max = DEVICE_COUNT_RESOURCE; 71 72 for (i = 0; i < max; i++) { 73 struct resource *res = &dev->resource[i]; 74 if (res->flags & IORESOURCE_MEM) 75 end = max(res->end, end); 76 } 77 } 78 79 switch(atu) { 80 case 0: 81 iop13xx_atux_mem_size = 82 (end - IOP13XX_PCIX_LOWER_MEM_RA) + 1; 83 84 /* 16MB align the request */ 85 if (iop13xx_atux_mem_size & (SZ_16M - 1)) { 86 iop13xx_atux_mem_size &= ~(SZ_16M - 1); 87 iop13xx_atux_mem_size += SZ_16M; 88 } 89 90 if (end) { 91 iop13xx_atux_mem_base = 92 (u32) __arm_ioremap_pfn( 93 __phys_to_pfn(IOP13XX_PCIX_LOWER_MEM_PA) 94 , 0, iop13xx_atux_mem_size, MT_DEVICE); 95 if (!iop13xx_atux_mem_base) { 96 printk("%s: atux allocation " 97 "failed\n", __FUNCTION__); 98 BUG(); 99 } 100 } else 101 iop13xx_atux_mem_size = 0; 102 PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n", 103 __FUNCTION__, atu, iop13xx_atux_mem_size, 104 iop13xx_atux_mem_base); 105 break; 106 case 1: 107 iop13xx_atue_mem_size = 108 (end - IOP13XX_PCIE_LOWER_MEM_RA) + 1; 109 110 /* 16MB align the request */ 111 if (iop13xx_atue_mem_size & (SZ_16M - 1)) { 112 iop13xx_atue_mem_size &= ~(SZ_16M - 1); 113 iop13xx_atue_mem_size += SZ_16M; 114 } 115 116 if (end) { 117 iop13xx_atue_mem_base = 118 (u32) __arm_ioremap_pfn( 119 __phys_to_pfn(IOP13XX_PCIE_LOWER_MEM_PA) 120 , 0, iop13xx_atue_mem_size, MT_DEVICE); 121 if (!iop13xx_atue_mem_base) { 122 printk("%s: atue allocation " 123 "failed\n", __FUNCTION__); 124 BUG(); 125 } 126 } else 127 iop13xx_atue_mem_size = 0; 128 PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n", 129 __FUNCTION__, atu, iop13xx_atue_mem_size, 130 iop13xx_atue_mem_base); 131 break; 132 } 133 134 printk("%s: Initialized (%uM @ resource/virtual: %08lx/%08x)\n", 135 atu ? "ATUE" : "ATUX", 136 (atu ? iop13xx_atue_mem_size : iop13xx_atux_mem_size) / 137 SZ_1M, 138 atu ? IOP13XX_PCIE_LOWER_MEM_RA : 139 IOP13XX_PCIX_LOWER_MEM_RA, 140 atu ? iop13xx_atue_mem_base : 141 iop13xx_atux_mem_base); 142 end = 0; 143 } 144 145 } 146} 147 148static int iop13xx_atu_function(int atu) 149{ 150 int func = 0; 151 /* the function number depends on the value of the 152 * IOP13XX_INTERFACE_SEL_PCIX reset strap 153 * see C-Spec section 3.17 154 */ 155 switch(atu) { 156 case IOP13XX_INIT_ATU_ATUX: 157 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX) 158 func = 5; 159 else 160 func = 0; 161 break; 162 case IOP13XX_INIT_ATU_ATUE: 163 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX) 164 func = 0; 165 else 166 func = 5; 167 break; 168 default: 169 BUG(); 170 } 171 172 return func; 173} 174 175/* iop13xx_atux_cfg_address - format a configuration address for atux 176 * @bus: Target bus to access 177 * @devfn: Combined device number and function number 178 * @where: Desired register's address offset 179 * 180 * Convert the parameters to a configuration address formatted 181 * according the PCI-X 2.0 specification 182 */ 183static u32 iop13xx_atux_cfg_address(struct pci_bus *bus, int devfn, int where) 184{ 185 struct pci_sys_data *sys = bus->sysdata; 186 u32 addr; 187 188 if (sys->busnr == bus->number) 189 addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11); 190 else 191 addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1; 192 193 addr |= PCI_FUNC(devfn) << 8 | ((where & 0xff) & ~3); 194 addr |= ((where & 0xf00) >> 8) << 24; /* upper register number */ 195 196 return addr; 197} 198 199/* iop13xx_atue_cfg_address - format a configuration address for atue 200 * @bus: Target bus to access 201 * @devfn: Combined device number and function number 202 * @where: Desired register's address offset 203 * 204 * Convert the parameters to an address usable by the ATUE_OCCAR 205 */ 206static u32 iop13xx_atue_cfg_address(struct pci_bus *bus, int devfn, int where) 207{ 208 struct pci_sys_data *sys = bus->sysdata; 209 u32 addr; 210 211 PRINTK("iop13xx_atue_cfg_address: bus: %d dev: %d func: %d", 212 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn)); 213 addr = ((u32) bus->number) << IOP13XX_ATUE_OCCAR_BUS_NUM | 214 ((u32) PCI_SLOT(devfn)) << IOP13XX_ATUE_OCCAR_DEV_NUM | 215 ((u32) PCI_FUNC(devfn)) << IOP13XX_ATUE_OCCAR_FUNC_NUM | 216 (where & ~0x3); 217 218 if (sys->busnr != bus->number) 219 addr |= 1; /* type 1 access */ 220 221 return addr; 222} 223 224/* This routine checks the status of the last configuration cycle. If an error 225 * was detected it returns >0, else it returns a 0. The errors being checked 226 * are parity, master abort, target abort (master and target). These types of 227 * errors occure during a config cycle where there is no device, like during 228 * the discovery stage. 229 */ 230static int iop13xx_atux_pci_status(int clear) 231{ 232 unsigned int status; 233 int err = 0; 234 235 /* 236 * Check the status registers. 237 */ 238 status = __raw_readw(IOP13XX_ATUX_ATUSR); 239 if (status & IOP_PCI_STATUS_ERROR) 240 { 241 PRINTK("\t\t\tPCI error: ATUSR %#08x", status); 242 if(clear) 243 __raw_writew(status & IOP_PCI_STATUS_ERROR, 244 IOP13XX_ATUX_ATUSR); 245 err = 1; 246 } 247 status = __raw_readl(IOP13XX_ATUX_ATUISR); 248 if (status & IOP13XX_ATUX_ATUISR_ERROR) 249 { 250 PRINTK("\t\t\tPCI error interrupt: ATUISR %#08x", status); 251 if(clear) 252 __raw_writel(status & IOP13XX_ATUX_ATUISR_ERROR, 253 IOP13XX_ATUX_ATUISR); 254 err = 1; 255 } 256 return err; 257} 258 259/* Simply write the address register and read the configuration 260 * data. Note that the data dependency on %0 encourages an abort 261 * to be detected before we return. 262 */ 263static u32 iop13xx_atux_read(unsigned long addr) 264{ 265 u32 val; 266 267 __asm__ __volatile__( 268 "str %1, [%2]\n\t" 269 "ldr %0, [%3]\n\t" 270 "mov %0, %0\n\t" 271 : "=r" (val) 272 : "r" (addr), "r" (IOP13XX_ATUX_OCCAR), "r" (IOP13XX_ATUX_OCCDR)); 273 274 return val; 275} 276 277/* The read routines must check the error status of the last configuration 278 * cycle. If there was an error, the routine returns all hex f's. 279 */ 280static int 281iop13xx_atux_read_config(struct pci_bus *bus, unsigned int devfn, int where, 282 int size, u32 *value) 283{ 284 unsigned long addr = iop13xx_atux_cfg_address(bus, devfn, where); 285 u32 val = iop13xx_atux_read(addr) >> ((where & 3) * 8); 286 287 if (iop13xx_atux_pci_status(1) || is_atux_occdr_error()) { 288 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, 289 IOP13XX_XBG_BECSR); 290 val = 0xffffffff; 291 } 292 293 *value = val; 294 295 return PCIBIOS_SUCCESSFUL; 296} 297 298static int 299iop13xx_atux_write_config(struct pci_bus *bus, unsigned int devfn, int where, 300 int size, u32 value) 301{ 302 unsigned long addr = iop13xx_atux_cfg_address(bus, devfn, where); 303 u32 val; 304 305 if (size != 4) { 306 val = iop13xx_atux_read(addr); 307 if (!iop13xx_atux_pci_status(1) == 0) 308 return PCIBIOS_SUCCESSFUL; 309 310 where = (where & 3) * 8; 311 312 if (size == 1) 313 val &= ~(0xff << where); 314 else 315 val &= ~(0xffff << where); 316 317 __raw_writel(val | value << where, IOP13XX_ATUX_OCCDR); 318 } else { 319 __raw_writel(addr, IOP13XX_ATUX_OCCAR); 320 __raw_writel(value, IOP13XX_ATUX_OCCDR); 321 } 322 323 return PCIBIOS_SUCCESSFUL; 324} 325 326static struct pci_ops iop13xx_atux_ops = { 327 .read = iop13xx_atux_read_config, 328 .write = iop13xx_atux_write_config, 329}; 330 331/* This routine checks the status of the last configuration cycle. If an error 332 * was detected it returns >0, else it returns a 0. The errors being checked 333 * are parity, master abort, target abort (master and target). These types of 334 * errors occure during a config cycle where there is no device, like during 335 * the discovery stage. 336 */ 337static int iop13xx_atue_pci_status(int clear) 338{ 339 unsigned int status; 340 int err = 0; 341 342 /* 343 * Check the status registers. 344 */ 345 346 /* standard pci status register */ 347 status = __raw_readw(IOP13XX_ATUE_ATUSR); 348 if (status & IOP_PCI_STATUS_ERROR) { 349 PRINTK("\t\t\tPCI error: ATUSR %#08x", status); 350 if(clear) 351 __raw_writew(status & IOP_PCI_STATUS_ERROR, 352 IOP13XX_ATUE_ATUSR); 353 err++; 354 } 355 356 /* check the normal status bits in the ATUISR */ 357 status = __raw_readl(IOP13XX_ATUE_ATUISR); 358 if (status & IOP13XX_ATUE_ATUISR_ERROR) { 359 PRINTK("\t\t\tPCI error: ATUISR %#08x", status); 360 if (clear) 361 __raw_writew(status & IOP13XX_ATUE_ATUISR_ERROR, 362 IOP13XX_ATUE_ATUISR); 363 err++; 364 365 /* check the PCI-E status if the ATUISR reports an interface error */ 366 if (status & IOP13XX_ATUE_STAT_PCI_IFACE_ERR) { 367 /* get the unmasked errors */ 368 status = __raw_readl(IOP13XX_ATUE_PIE_STS) & 369 ~(__raw_readl(IOP13XX_ATUE_PIE_MSK)); 370 371 if (status) { 372 PRINTK("\t\t\tPCI-E error: ATUE_PIE_STS %#08x", 373 __raw_readl(IOP13XX_ATUE_PIE_STS)); 374 err++; 375 } else { 376 PRINTK("\t\t\tPCI-E error: ATUE_PIE_STS %#08x", 377 __raw_readl(IOP13XX_ATUE_PIE_STS)); 378 PRINTK("\t\t\tPCI-E error: ATUE_PIE_MSK %#08x", 379 __raw_readl(IOP13XX_ATUE_PIE_MSK)); 380 BUG(); 381 } 382 383 if(clear) 384 __raw_writel(status, IOP13XX_ATUE_PIE_STS); 385 } 386 } 387 388 return err; 389} 390 391static int 392iop13xx_pcie_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) 393{ 394 WARN_ON(idsel != 0); 395 396 switch (pin) { 397 case 1: return ATUE_INTA; 398 case 2: return ATUE_INTB; 399 case 3: return ATUE_INTC; 400 case 4: return ATUE_INTD; 401 default: return -1; 402 } 403} 404 405static u32 iop13xx_atue_read(unsigned long addr) 406{ 407 u32 val; 408 409 __raw_writel(addr, IOP13XX_ATUE_OCCAR); 410 val = __raw_readl(IOP13XX_ATUE_OCCDR); 411 412 rmb(); 413 414 return val; 415} 416 417/* The read routines must check the error status of the last configuration 418 * cycle. If there was an error, the routine returns all hex f's. 419 */ 420static int 421iop13xx_atue_read_config(struct pci_bus *bus, unsigned int devfn, int where, 422 int size, u32 *value) 423{ 424 u32 val; 425 unsigned long addr = iop13xx_atue_cfg_address(bus, devfn, where); 426 427 /* Hide device numbers > 0 on the local PCI-E bus (Type 0 access) */ 428 if (!PCI_SLOT(devfn) || (addr & 1)) { 429 val = iop13xx_atue_read(addr) >> ((where & 3) * 8); 430 if( iop13xx_atue_pci_status(1) || is_atue_occdr_error() ) { 431 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, 432 IOP13XX_XBG_BECSR); 433 val = 0xffffffff; 434 } 435 436 PRINTK("addr=%#0lx, val=%#010x", addr, val); 437 } else 438 val = 0xffffffff; 439 440 *value = val; 441 442 return PCIBIOS_SUCCESSFUL; 443} 444 445static int 446iop13xx_atue_write_config(struct pci_bus *bus, unsigned int devfn, int where, 447 int size, u32 value) 448{ 449 unsigned long addr = iop13xx_atue_cfg_address(bus, devfn, where); 450 u32 val; 451 452 if (size != 4) { 453 val = iop13xx_atue_read(addr); 454 if (!iop13xx_atue_pci_status(1) == 0) 455 return PCIBIOS_SUCCESSFUL; 456 457 where = (where & 3) * 8; 458 459 if (size == 1) 460 val &= ~(0xff << where); 461 else 462 val &= ~(0xffff << where); 463 464 __raw_writel(val | value << where, IOP13XX_ATUE_OCCDR); 465 } else { 466 __raw_writel(addr, IOP13XX_ATUE_OCCAR); 467 __raw_writel(value, IOP13XX_ATUE_OCCDR); 468 } 469 470 return PCIBIOS_SUCCESSFUL; 471} 472 473static struct pci_ops iop13xx_atue_ops = { 474 .read = iop13xx_atue_read_config, 475 .write = iop13xx_atue_write_config, 476}; 477 478/* When a PCI device does not exist during config cycles, the XScale gets a 479 * bus error instead of returning 0xffffffff. We can't rely on the ATU status 480 * bits to tell us that it was indeed a configuration cycle that caused this 481 * error especially in the case when the ATUE link is down. Instead we rely 482 * on data from the south XSI bridge to validate the abort 483 */ 484int 485iop13xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs) 486{ 487 PRINTK("Data abort: address = 0x%08lx " 488 "fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx", 489 addr, fsr, regs->ARM_pc, regs->ARM_lr); 490 491 PRINTK("IOP13XX_XBG_BECSR: %#10x", __raw_readl(IOP13XX_XBG_BECSR)); 492 PRINTK("IOP13XX_XBG_BERAR: %#10x", __raw_readl(IOP13XX_XBG_BERAR)); 493 PRINTK("IOP13XX_XBG_BERUAR: %#10x", __raw_readl(IOP13XX_XBG_BERUAR)); 494 495 /* If it was an imprecise abort, then we need to correct the 496 * return address to be _after_ the instruction. 497 */ 498 if (fsr & (1 << 10)) 499 regs->ARM_pc += 4; 500 501 if (is_atue_occdr_error() || is_atux_occdr_error()) 502 return 0; 503 else 504 return 1; 505} 506 507/* Scan an IOP13XX PCI bus. nr selects which ATU we use. 508 */ 509struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *sys) 510{ 511 int which_atu; 512 struct pci_bus *bus = NULL; 513 514 switch (init_atu) { 515 case IOP13XX_INIT_ATU_ATUX: 516 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUX; 517 break; 518 case IOP13XX_INIT_ATU_ATUE: 519 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUE; 520 break; 521 case (IOP13XX_INIT_ATU_ATUX | IOP13XX_INIT_ATU_ATUE): 522 which_atu = nr ? IOP13XX_INIT_ATU_ATUE : IOP13XX_INIT_ATU_ATUX; 523 break; 524 default: 525 which_atu = 0; 526 } 527 528 if (!which_atu) { 529 BUG(); 530 return NULL; 531 } 532 533 switch (which_atu) { 534 case IOP13XX_INIT_ATU_ATUX: 535 if (time_after_eq(jiffies + msecs_to_jiffies(1000), 536 atux_trhfa_timeout)) /* ensure not wrap */ 537 while(time_before(jiffies, atux_trhfa_timeout)) 538 udelay(100); 539 540 bus = pci_bus_atux = pci_scan_bus(sys->busnr, 541 &iop13xx_atux_ops, 542 sys); 543 break; 544 case IOP13XX_INIT_ATU_ATUE: 545 bus = pci_bus_atue = pci_scan_bus(sys->busnr, 546 &iop13xx_atue_ops, 547 sys); 548 break; 549 } 550 551 return bus; 552} 553 554/* This function is called from iop13xx_pci_init() after assigning valid 555 * values to iop13xx_atue_pmmr_offset. This is the location for common 556 * setup of ATUE for all IOP13XX implementations. 557 */ 558void __init iop13xx_atue_setup(void) 559{ 560 int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUE); 561 u32 reg_val; 562 563#ifdef CONFIG_PCI_MSI 564 /* BAR 0 (inbound msi window) */ 565 __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_MU_MUBAR); 566 __raw_writel(~(IOP13XX_MU_WINDOW_SIZE - 1), IOP13XX_ATUE_IALR0); 567 __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_ATUE_IATVR0); 568 __raw_writel(IOP13XX_MU_BASE_PCI, IOP13XX_ATUE_IABAR0); 569#endif 570 571 /* BAR 1 (1:1 mapping with Physical RAM) */ 572 /* Set limit and enable */ 573 __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1, 574 IOP13XX_ATUE_IALR1); 575 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1); 576 577 /* Set base at the top of the reserved address space */ 578 __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 | 579 PCI_BASE_ADDRESS_MEM_PREFETCH, IOP13XX_ATUE_IABAR1); 580 581 /* 1:1 mapping with physical ram 582 * (leave big endian byte swap disabled) 583 */ 584 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1); 585 __raw_writel(PHYS_OFFSET, IOP13XX_ATUE_IATVR1); 586 587 /* Outbound window 1 (PCIX/PCIE memory window) */ 588 /* 32 bit Address Space */ 589 __raw_writel(0x0, IOP13XX_ATUE_OUMWTVR1); 590 /* PA[35:32] */ 591 __raw_writel(IOP13XX_ATUE_OUMBAR_ENABLE | 592 (IOP13XX_PCIE_MEM_PHYS_OFFSET >> 32), 593 IOP13XX_ATUE_OUMBAR1); 594 595 /* Setup the I/O Bar 596 * A[35-16] in 31-12 597 */ 598 __raw_writel(((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000), 599 IOP13XX_ATUE_OIOBAR); 600 __raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR); 601 602 /* clear startup errors */ 603 iop13xx_atue_pci_status(1); 604 605 /* OIOBAR function number 606 */ 607 reg_val = __raw_readl(IOP13XX_ATUE_OIOBAR); 608 reg_val &= ~0x7; 609 reg_val |= func; 610 __raw_writel(reg_val, IOP13XX_ATUE_OIOBAR); 611 612 /* OUMBAR function numbers 613 */ 614 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0); 615 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK << 616 IOP13XX_ATU_OUMBAR_FUNC_NUM); 617 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM; 618 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0); 619 620 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1); 621 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK << 622 IOP13XX_ATU_OUMBAR_FUNC_NUM); 623 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM; 624 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1); 625 626 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2); 627 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK << 628 IOP13XX_ATU_OUMBAR_FUNC_NUM); 629 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM; 630 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2); 631 632 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3); 633 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK << 634 IOP13XX_ATU_OUMBAR_FUNC_NUM); 635 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM; 636 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3); 637 638 /* Enable inbound and outbound cycles 639 */ 640 reg_val = __raw_readw(IOP13XX_ATUE_ATUCMD); 641 reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 642 PCI_COMMAND_PARITY | PCI_COMMAND_SERR; 643 __raw_writew(reg_val, IOP13XX_ATUE_ATUCMD); 644 645 reg_val = __raw_readl(IOP13XX_ATUE_ATUCR); 646 reg_val |= IOP13XX_ATUE_ATUCR_OUT_EN | 647 IOP13XX_ATUE_ATUCR_IVM; 648 __raw_writel(reg_val, IOP13XX_ATUE_ATUCR); 649} 650 651void __init iop13xx_atue_disable(void) 652{ 653 u32 reg_val; 654 655 __raw_writew(0x0, IOP13XX_ATUE_ATUCMD); 656 __raw_writel(IOP13XX_ATUE_ATUCR_IVM, IOP13XX_ATUE_ATUCR); 657 658 /* wait for cycles to quiesce */ 659 while (__raw_readl(IOP13XX_ATUE_PCSR) & (IOP13XX_ATUE_PCSR_OUT_Q_BUSY | 660 IOP13XX_ATUE_PCSR_IN_Q_BUSY | 661 IOP13XX_ATUE_PCSR_LLRB_BUSY)) 662 cpu_relax(); 663 664 /* BAR 0 ( Disabled ) */ 665 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR0); 666 __raw_writel(0x0, IOP13XX_ATUE_IABAR0); 667 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR0); 668 __raw_writel(0x0, IOP13XX_ATUE_IATVR0); 669 __raw_writel(0x0, IOP13XX_ATUE_IALR0); 670 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0); 671 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE; 672 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0); 673 674 /* BAR 1 ( Disabled ) */ 675 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1); 676 __raw_writel(0x0, IOP13XX_ATUE_IABAR1); 677 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1); 678 __raw_writel(0x0, IOP13XX_ATUE_IATVR1); 679 __raw_writel(0x0, IOP13XX_ATUE_IALR1); 680 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1); 681 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE; 682 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1); 683 684 /* BAR 2 ( Disabled ) */ 685 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR2); 686 __raw_writel(0x0, IOP13XX_ATUE_IABAR2); 687 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR2); 688 __raw_writel(0x0, IOP13XX_ATUE_IATVR2); 689 __raw_writel(0x0, IOP13XX_ATUE_IALR2); 690 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2); 691 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE; 692 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2); 693 694 /* BAR 3 ( Disabled ) */ 695 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3); 696 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE; 697 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3); 698 699 /* Setup the I/O Bar 700 * A[35-16] in 31-12 701 */ 702 __raw_writel((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000, 703 IOP13XX_ATUE_OIOBAR); 704 __raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR); 705} 706 707/* This function is called from iop13xx_pci_init() after assigning valid 708 * values to iop13xx_atux_pmmr_offset. This is the location for common 709 * setup of ATUX for all IOP13XX implementations. 710 */ 711void __init iop13xx_atux_setup(void) 712{ 713 u32 reg_val; 714 int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUX); 715 716 /* Take PCI-X bus out of reset if bootloader hasn't already. 717 * According to spec, we should wait for 2^25 PCI clocks to meet 718 * the PCI timing parameter Trhfa (RST# high to first access). 719 * This is rarely necessary and often ignored. 720 */ 721 reg_val = __raw_readl(IOP13XX_ATUX_PCSR); 722 if (reg_val & IOP13XX_ATUX_PCSR_P_RSTOUT) { 723 int msec = (reg_val >> IOP13XX_ATUX_PCSR_FREQ_OFFSET) & 0x7; 724 msec = 1000 / (8-msec); /* bits 100=133MHz, 111=>33MHz */ 725 __raw_writel(reg_val & ~IOP13XX_ATUX_PCSR_P_RSTOUT, 726 IOP13XX_ATUX_PCSR); 727 atux_trhfa_timeout = jiffies + msecs_to_jiffies(msec); 728 } 729 else 730 atux_trhfa_timeout = jiffies; 731 732#ifdef CONFIG_PCI_MSI 733 /* BAR 0 (inbound msi window) */ 734 __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_MU_MUBAR); 735 __raw_writel(~(IOP13XX_MU_WINDOW_SIZE - 1), IOP13XX_ATUX_IALR0); 736 __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_ATUX_IATVR0); 737 __raw_writel(IOP13XX_MU_BASE_PCI, IOP13XX_ATUX_IABAR0); 738#endif 739 740 /* BAR 1 (1:1 mapping with Physical RAM) */ 741 /* Set limit and enable */ 742 __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1, 743 IOP13XX_ATUX_IALR1); 744 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1); 745 746 /* Set base at the top of the reserved address space */ 747 __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 | 748 PCI_BASE_ADDRESS_MEM_PREFETCH, IOP13XX_ATUX_IABAR1); 749 750 /* 1:1 mapping with physical ram 751 * (leave big endian byte swap disabled) 752 */ 753 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1); 754 __raw_writel(PHYS_OFFSET, IOP13XX_ATUX_IATVR1); 755 756 /* Outbound window 1 (PCIX/PCIE memory window) */ 757 /* 32 bit Address Space */ 758 __raw_writel(0x0, IOP13XX_ATUX_OUMWTVR1); 759 /* PA[35:32] */ 760 __raw_writel(IOP13XX_ATUX_OUMBAR_ENABLE | 761 IOP13XX_PCIX_MEM_PHYS_OFFSET >> 32, 762 IOP13XX_ATUX_OUMBAR1); 763 764 /* Setup the I/O Bar 765 * A[35-16] in 31-12 766 */ 767 __raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000, 768 IOP13XX_ATUX_OIOBAR); 769 __raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR); 770 771 /* clear startup errors */ 772 iop13xx_atux_pci_status(1); 773 774 /* OIOBAR function number 775 */ 776 reg_val = __raw_readl(IOP13XX_ATUX_OIOBAR); 777 reg_val &= ~0x7; 778 reg_val |= func; 779 __raw_writel(reg_val, IOP13XX_ATUX_OIOBAR); 780 781 /* OUMBAR function numbers 782 */ 783 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0); 784 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK << 785 IOP13XX_ATU_OUMBAR_FUNC_NUM); 786 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM; 787 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0); 788 789 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1); 790 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK << 791 IOP13XX_ATU_OUMBAR_FUNC_NUM); 792 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM; 793 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1); 794 795 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2); 796 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK << 797 IOP13XX_ATU_OUMBAR_FUNC_NUM); 798 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM; 799 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2); 800 801 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3); 802 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK << 803 IOP13XX_ATU_OUMBAR_FUNC_NUM); 804 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM; 805 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3); 806 807 /* Enable inbound and outbound cycles 808 */ 809 reg_val = __raw_readw(IOP13XX_ATUX_ATUCMD); 810 reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 811 PCI_COMMAND_PARITY | PCI_COMMAND_SERR; 812 __raw_writew(reg_val, IOP13XX_ATUX_ATUCMD); 813 814 reg_val = __raw_readl(IOP13XX_ATUX_ATUCR); 815 reg_val |= IOP13XX_ATUX_ATUCR_OUT_EN; 816 __raw_writel(reg_val, IOP13XX_ATUX_ATUCR); 817} 818 819void __init iop13xx_atux_disable(void) 820{ 821 u32 reg_val; 822 823 __raw_writew(0x0, IOP13XX_ATUX_ATUCMD); 824 __raw_writel(0x0, IOP13XX_ATUX_ATUCR); 825 826 /* wait for cycles to quiesce */ 827 while (__raw_readl(IOP13XX_ATUX_PCSR) & (IOP13XX_ATUX_PCSR_OUT_Q_BUSY | 828 IOP13XX_ATUX_PCSR_IN_Q_BUSY)) 829 cpu_relax(); 830 831 /* BAR 0 ( Disabled ) */ 832 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR0); 833 __raw_writel(0x0, IOP13XX_ATUX_IABAR0); 834 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR0); 835 __raw_writel(0x0, IOP13XX_ATUX_IATVR0); 836 __raw_writel(0x0, IOP13XX_ATUX_IALR0); 837 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0); 838 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE; 839 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0); 840 841 /* BAR 1 ( Disabled ) */ 842 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1); 843 __raw_writel(0x0, IOP13XX_ATUX_IABAR1); 844 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1); 845 __raw_writel(0x0, IOP13XX_ATUX_IATVR1); 846 __raw_writel(0x0, IOP13XX_ATUX_IALR1); 847 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1); 848 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE; 849 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1); 850 851 /* BAR 2 ( Disabled ) */ 852 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR2); 853 __raw_writel(0x0, IOP13XX_ATUX_IABAR2); 854 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR2); 855 __raw_writel(0x0, IOP13XX_ATUX_IATVR2); 856 __raw_writel(0x0, IOP13XX_ATUX_IALR2); 857 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2); 858 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE; 859 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2); 860 861 /* BAR 3 ( Disabled ) */ 862 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR3); 863 __raw_writel(0x0, IOP13XX_ATUX_IABAR3); 864 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR3); 865 __raw_writel(0x0, IOP13XX_ATUX_IATVR3); 866 __raw_writel(0x0, IOP13XX_ATUX_IALR3); 867 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3); 868 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE; 869 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3); 870 871 /* Setup the I/O Bar 872 * A[35-16] in 31-12 873 */ 874 __raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000, 875 IOP13XX_ATUX_OIOBAR); 876 __raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR); 877} 878 879void __init iop13xx_set_atu_mmr_bases(void) 880{ 881 /* Based on ESSR0, determine the ATU X/E offsets */ 882 switch(__raw_readl(IOP13XX_ESSR0) & 883 (IOP13XX_CONTROLLER_ONLY | IOP13XX_INTERFACE_SEL_PCIX)) { 884 /* both asserted */ 885 case 0: 886 iop13xx_atux_pmmr_offset = IOP13XX_ATU1_PMMR_OFFSET; 887 iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET; 888 break; 889 /* IOP13XX_CONTROLLER_ONLY = deasserted 890 * IOP13XX_INTERFACE_SEL_PCIX = asserted 891 */ 892 case IOP13XX_CONTROLLER_ONLY: 893 iop13xx_atux_pmmr_offset = IOP13XX_ATU0_PMMR_OFFSET; 894 iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET; 895 break; 896 /* IOP13XX_CONTROLLER_ONLY = asserted 897 * IOP13XX_INTERFACE_SEL_PCIX = deasserted 898 */ 899 case IOP13XX_INTERFACE_SEL_PCIX: 900 iop13xx_atux_pmmr_offset = IOP13XX_ATU1_PMMR_OFFSET; 901 iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET; 902 break; 903 /* both deasserted */ 904 case IOP13XX_CONTROLLER_ONLY | IOP13XX_INTERFACE_SEL_PCIX: 905 iop13xx_atux_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET; 906 iop13xx_atue_pmmr_offset = IOP13XX_ATU0_PMMR_OFFSET; 907 break; 908 default: 909 BUG(); 910 } 911} 912 913void __init iop13xx_atu_select(struct hw_pci *plat_pci) 914{ 915 int i; 916 917 /* set system defaults 918 * note: if "iop13xx_init_atu=" is specified this autodetect 919 * sequence will be bypassed 920 */ 921 if (init_atu == IOP13XX_INIT_ATU_DEFAULT) { 922 /* check for single/dual interface */ 923 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX) { 924 /* ATUE must be present check the device id 925 * to see if ATUX is present. 926 */ 927 init_atu |= IOP13XX_INIT_ATU_ATUE; 928 switch (__raw_readw(IOP13XX_ATUE_DID) & 0xf0) { 929 case 0x70: 930 case 0x80: 931 case 0xc0: 932 init_atu |= IOP13XX_INIT_ATU_ATUX; 933 break; 934 } 935 } else { 936 /* ATUX must be present check the device id 937 * to see if ATUE is present. 938 */ 939 init_atu |= IOP13XX_INIT_ATU_ATUX; 940 switch (__raw_readw(IOP13XX_ATUX_DID) & 0xf0) { 941 case 0x70: 942 case 0x80: 943 case 0xc0: 944 init_atu |= IOP13XX_INIT_ATU_ATUE; 945 break; 946 } 947 } 948 949 /* check central resource and root complex capability */ 950 if (init_atu & IOP13XX_INIT_ATU_ATUX) 951 if (!(__raw_readl(IOP13XX_ATUX_PCSR) & 952 IOP13XX_ATUX_PCSR_CENTRAL_RES)) 953 init_atu &= ~IOP13XX_INIT_ATU_ATUX; 954 955 if (init_atu & IOP13XX_INIT_ATU_ATUE) 956 if (__raw_readl(IOP13XX_ATUE_PCSR) & 957 IOP13XX_ATUE_PCSR_END_POINT) 958 init_atu &= ~IOP13XX_INIT_ATU_ATUE; 959 } 960 961 for (i = 0; i < 2; i++) { 962 if((init_atu & (1 << i)) == (1 << i)) 963 plat_pci->nr_controllers++; 964 } 965} 966 967void __init iop13xx_pci_init(void) 968{ 969 /* clear pre-existing south bridge errors */ 970 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR); 971 972 /* Setup the Min Address for PCI memory... */ 973 iop13xx_pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA; 974 975 /* if Linux is given control of an ATU 976 * clear out its prior configuration, 977 * otherwise do not touch the registers 978 */ 979 if (init_atu & IOP13XX_INIT_ATU_ATUE) { 980 iop13xx_atue_disable(); 981 iop13xx_atue_setup(); 982 } 983 984 if (init_atu & IOP13XX_INIT_ATU_ATUX) { 985 iop13xx_atux_disable(); 986 iop13xx_atux_setup(); 987 } 988 989 hook_fault_code(16+6, iop13xx_pci_abort, SIGBUS, 990 "imprecise external abort"); 991} 992 993/* initialize the pci memory space. handle any combination of 994 * atue and atux enabled/disabled 995 */ 996int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) 997{ 998 struct resource *res; 999 int which_atu; 1000 u32 pcixsr, pcsr; 1001 1002 if (nr > 1) 1003 return 0; 1004 1005 res = kmalloc(sizeof(struct resource) * 2, GFP_KERNEL); 1006 if (!res) 1007 panic("PCI: unable to alloc resources"); 1008 1009 memset(res, 0, sizeof(struct resource) * 2); 1010 1011 /* 'nr' assumptions: 1012 * ATUX is always 0 1013 * ATUE is 1 when ATUX is also enabled 1014 * ATUE is 0 when ATUX is disabled 1015 */ 1016 switch(init_atu) { 1017 case IOP13XX_INIT_ATU_ATUX: 1018 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUX; 1019 break; 1020 case IOP13XX_INIT_ATU_ATUE: 1021 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUE; 1022 break; 1023 case (IOP13XX_INIT_ATU_ATUX | IOP13XX_INIT_ATU_ATUE): 1024 which_atu = nr ? IOP13XX_INIT_ATU_ATUE : IOP13XX_INIT_ATU_ATUX; 1025 break; 1026 default: 1027 which_atu = 0; 1028 } 1029 1030 if (!which_atu) 1031 return 0; 1032 1033 switch(which_atu) { 1034 case IOP13XX_INIT_ATU_ATUX: 1035 pcixsr = __raw_readl(IOP13XX_ATUX_PCIXSR); 1036 pcixsr &= ~0xffff; 1037 pcixsr |= sys->busnr << IOP13XX_ATUX_PCIXSR_BUS_NUM | 1038 0 << IOP13XX_ATUX_PCIXSR_DEV_NUM | 1039 iop13xx_atu_function(IOP13XX_INIT_ATU_ATUX) 1040 << IOP13XX_ATUX_PCIXSR_FUNC_NUM; 1041 __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR); 1042 1043 res[0].start = IOP13XX_PCIX_LOWER_IO_PA + IOP13XX_PCIX_IO_BUS_OFFSET; 1044 res[0].end = IOP13XX_PCIX_UPPER_IO_PA; 1045 res[0].name = "IQ81340 ATUX PCI I/O Space"; 1046 res[0].flags = IORESOURCE_IO; 1047 1048 res[1].start = IOP13XX_PCIX_LOWER_MEM_RA; 1049 res[1].end = IOP13XX_PCIX_UPPER_MEM_RA; 1050 res[1].name = "IQ81340 ATUX PCI Memory Space"; 1051 res[1].flags = IORESOURCE_MEM; 1052 sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET; 1053 sys->io_offset = IOP13XX_PCIX_LOWER_IO_PA; 1054 break; 1055 case IOP13XX_INIT_ATU_ATUE: 1056 /* Note: the function number field in the PCSR is ro */ 1057 pcsr = __raw_readl(IOP13XX_ATUE_PCSR); 1058 pcsr &= ~(0xfff8 << 16); 1059 pcsr |= sys->busnr << IOP13XX_ATUE_PCSR_BUS_NUM | 1060 0 << IOP13XX_ATUE_PCSR_DEV_NUM; 1061 1062 __raw_writel(pcsr, IOP13XX_ATUE_PCSR); 1063 1064 res[0].start = IOP13XX_PCIE_LOWER_IO_PA + IOP13XX_PCIE_IO_BUS_OFFSET; 1065 res[0].end = IOP13XX_PCIE_UPPER_IO_PA; 1066 res[0].name = "IQ81340 ATUE PCI I/O Space"; 1067 res[0].flags = IORESOURCE_IO; 1068 1069 res[1].start = IOP13XX_PCIE_LOWER_MEM_RA; 1070 res[1].end = IOP13XX_PCIE_UPPER_MEM_RA; 1071 res[1].name = "IQ81340 ATUE PCI Memory Space"; 1072 res[1].flags = IORESOURCE_MEM; 1073 sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET; 1074 sys->io_offset = IOP13XX_PCIE_LOWER_IO_PA; 1075 sys->map_irq = iop13xx_pcie_map_irq; 1076 break; 1077 default: 1078 return 0; 1079 } 1080 1081 request_resource(&ioport_resource, &res[0]); 1082 request_resource(&iomem_resource, &res[1]); 1083 1084 sys->resource[0] = &res[0]; 1085 sys->resource[1] = &res[1]; 1086 sys->resource[2] = NULL; 1087 1088 return 1; 1089} 1090 1091u16 iop13xx_dev_id(void) 1092{ 1093 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX) 1094 return __raw_readw(IOP13XX_ATUE_DID); 1095 else 1096 return __raw_readw(IOP13XX_ATUX_DID); 1097} 1098 1099static int __init iop13xx_init_atu_setup(char *str) 1100{ 1101 init_atu = IOP13XX_INIT_ATU_NONE; 1102 if (str) { 1103 while (*str != '\0') { 1104 switch (*str) { 1105 case 'x': 1106 case 'X': 1107 init_atu |= IOP13XX_INIT_ATU_ATUX; 1108 init_atu &= ~IOP13XX_INIT_ATU_NONE; 1109 break; 1110 case 'e': 1111 case 'E': 1112 init_atu |= IOP13XX_INIT_ATU_ATUE; 1113 init_atu &= ~IOP13XX_INIT_ATU_NONE; 1114 break; 1115 case ',': 1116 case '=': 1117 break; 1118 default: 1119 PRINTK("\"iop13xx_init_atu\" malformed at " 1120 "character: \'%c\'", *str); 1121 *(str + 1) = '\0'; 1122 init_atu = IOP13XX_INIT_ATU_DEFAULT; 1123 } 1124 str++; 1125 } 1126 } 1127 return 1; 1128} 1129 1130__setup("iop13xx_init_atu", iop13xx_init_atu_setup); 1131