1/* 2 * arch/arm/mach-at91/at91rm9200_devices.c 3 * 4 * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org> 5 * Copyright (C) 2005 David Brownell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 */ 13#include <asm/mach/arch.h> 14#include <asm/mach/map.h> 15 16#include <linux/platform_device.h> 17 18#include <asm/arch/board.h> 19#include <asm/arch/gpio.h> 20#include <asm/arch/at91rm9200.h> 21#include <asm/arch/at91rm9200_mc.h> 22 23#include "generic.h" 24 25 26/* -------------------------------------------------------------------- 27 * USB Host 28 * -------------------------------------------------------------------- */ 29 30#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) 31static u64 ohci_dmamask = 0xffffffffUL; 32static struct at91_usbh_data usbh_data; 33 34static struct resource usbh_resources[] = { 35 [0] = { 36 .start = AT91RM9200_UHP_BASE, 37 .end = AT91RM9200_UHP_BASE + SZ_1M - 1, 38 .flags = IORESOURCE_MEM, 39 }, 40 [1] = { 41 .start = AT91RM9200_ID_UHP, 42 .end = AT91RM9200_ID_UHP, 43 .flags = IORESOURCE_IRQ, 44 }, 45}; 46 47static struct platform_device at91rm9200_usbh_device = { 48 .name = "at91_ohci", 49 .id = -1, 50 .dev = { 51 .dma_mask = &ohci_dmamask, 52 .coherent_dma_mask = 0xffffffff, 53 .platform_data = &usbh_data, 54 }, 55 .resource = usbh_resources, 56 .num_resources = ARRAY_SIZE(usbh_resources), 57}; 58 59void __init at91_add_device_usbh(struct at91_usbh_data *data) 60{ 61 if (!data) 62 return; 63 64 usbh_data = *data; 65 platform_device_register(&at91rm9200_usbh_device); 66} 67#else 68void __init at91_add_device_usbh(struct at91_usbh_data *data) {} 69#endif 70 71 72/* -------------------------------------------------------------------- 73 * USB Device (Gadget) 74 * -------------------------------------------------------------------- */ 75 76#ifdef CONFIG_USB_GADGET_AT91 77static struct at91_udc_data udc_data; 78 79static struct resource udc_resources[] = { 80 [0] = { 81 .start = AT91RM9200_BASE_UDP, 82 .end = AT91RM9200_BASE_UDP + SZ_16K - 1, 83 .flags = IORESOURCE_MEM, 84 }, 85 [1] = { 86 .start = AT91RM9200_ID_UDP, 87 .end = AT91RM9200_ID_UDP, 88 .flags = IORESOURCE_IRQ, 89 }, 90}; 91 92static struct platform_device at91rm9200_udc_device = { 93 .name = "at91_udc", 94 .id = -1, 95 .dev = { 96 .platform_data = &udc_data, 97 }, 98 .resource = udc_resources, 99 .num_resources = ARRAY_SIZE(udc_resources), 100}; 101 102void __init at91_add_device_udc(struct at91_udc_data *data) 103{ 104 if (!data) 105 return; 106 107 if (data->vbus_pin) { 108 at91_set_gpio_input(data->vbus_pin, 0); 109 at91_set_deglitch(data->vbus_pin, 1); 110 } 111 if (data->pullup_pin) 112 at91_set_gpio_output(data->pullup_pin, 0); 113 114 udc_data = *data; 115 platform_device_register(&at91rm9200_udc_device); 116} 117#else 118void __init at91_add_device_udc(struct at91_udc_data *data) {} 119#endif 120 121 122/* -------------------------------------------------------------------- 123 * Ethernet 124 * -------------------------------------------------------------------- */ 125 126#if defined(CONFIG_ARM_AT91_ETHER) || defined(CONFIG_ARM_AT91_ETHER_MODULE) 127static u64 eth_dmamask = 0xffffffffUL; 128static struct at91_eth_data eth_data; 129 130static struct resource eth_resources[] = { 131 [0] = { 132 .start = AT91_VA_BASE_EMAC, 133 .end = AT91_VA_BASE_EMAC + SZ_16K - 1, 134 .flags = IORESOURCE_MEM, 135 }, 136 [1] = { 137 .start = AT91RM9200_ID_EMAC, 138 .end = AT91RM9200_ID_EMAC, 139 .flags = IORESOURCE_IRQ, 140 }, 141}; 142 143static struct platform_device at91rm9200_eth_device = { 144 .name = "at91_ether", 145 .id = -1, 146 .dev = { 147 .dma_mask = ð_dmamask, 148 .coherent_dma_mask = 0xffffffff, 149 .platform_data = ð_data, 150 }, 151 .resource = eth_resources, 152 .num_resources = ARRAY_SIZE(eth_resources), 153}; 154 155void __init at91_add_device_eth(struct at91_eth_data *data) 156{ 157 if (!data) 158 return; 159 160 if (data->phy_irq_pin) { 161 at91_set_gpio_input(data->phy_irq_pin, 0); 162 at91_set_deglitch(data->phy_irq_pin, 1); 163 } 164 165 /* Pins used for MII and RMII */ 166 at91_set_A_periph(AT91_PIN_PA16, 0); /* EMDIO */ 167 at91_set_A_periph(AT91_PIN_PA15, 0); /* EMDC */ 168 at91_set_A_periph(AT91_PIN_PA14, 0); /* ERXER */ 169 at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */ 170 at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */ 171 at91_set_A_periph(AT91_PIN_PA11, 0); /* ECRS_ECRSDV */ 172 at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX1 */ 173 at91_set_A_periph(AT91_PIN_PA9, 0); /* ETX0 */ 174 at91_set_A_periph(AT91_PIN_PA8, 0); /* ETXEN */ 175 at91_set_A_periph(AT91_PIN_PA7, 0); /* ETXCK_EREFCK */ 176 177 if (!data->is_rmii) { 178 at91_set_B_periph(AT91_PIN_PB19, 0); /* ERXCK */ 179 at91_set_B_periph(AT91_PIN_PB18, 0); /* ECOL */ 180 at91_set_B_periph(AT91_PIN_PB17, 0); /* ERXDV */ 181 at91_set_B_periph(AT91_PIN_PB16, 0); /* ERX3 */ 182 at91_set_B_periph(AT91_PIN_PB15, 0); /* ERX2 */ 183 at91_set_B_periph(AT91_PIN_PB14, 0); /* ETXER */ 184 at91_set_B_periph(AT91_PIN_PB13, 0); /* ETX3 */ 185 at91_set_B_periph(AT91_PIN_PB12, 0); /* ETX2 */ 186 } 187 188 eth_data = *data; 189 platform_device_register(&at91rm9200_eth_device); 190} 191#else 192void __init at91_add_device_eth(struct at91_eth_data *data) {} 193#endif 194 195 196/* -------------------------------------------------------------------- 197 * Compact Flash / PCMCIA 198 * -------------------------------------------------------------------- */ 199 200#if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE) 201static struct at91_cf_data cf_data; 202 203#define CF_BASE AT91_CHIPSELECT_4 204 205static struct resource cf_resources[] = { 206 [0] = { 207 .start = CF_BASE, 208 /* ties up CS4, CS5 and CS6 */ 209 .end = CF_BASE + (0x30000000 - 1), 210 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT, 211 }, 212}; 213 214static struct platform_device at91rm9200_cf_device = { 215 .name = "at91_cf", 216 .id = -1, 217 .dev = { 218 .platform_data = &cf_data, 219 }, 220 .resource = cf_resources, 221 .num_resources = ARRAY_SIZE(cf_resources), 222}; 223 224void __init at91_add_device_cf(struct at91_cf_data *data) 225{ 226 unsigned int csa; 227 228 if (!data) 229 return; 230 231 data->chipselect = 4; /* can only use EBI ChipSelect 4 */ 232 233 /* CF takes over CS4, CS5, CS6 */ 234 csa = at91_sys_read(AT91_EBI_CSA); 235 at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH); 236 237 /* 238 * Static memory controller timing adjustments. 239 * REVISIT: these timings are in terms of MCK cycles, so 240 * when MCK changes (cpufreq etc) so must these values... 241 */ 242 at91_sys_write(AT91_SMC_CSR(4), 243 AT91_SMC_ACSS_STD 244 | AT91_SMC_DBW_16 245 | AT91_SMC_BAT 246 | AT91_SMC_WSEN 247 | AT91_SMC_NWS_(32) /* wait states */ 248 | AT91_SMC_RWSETUP_(6) /* setup time */ 249 | AT91_SMC_RWHOLD_(4) /* hold time */ 250 ); 251 252 /* input/irq */ 253 if (data->irq_pin) { 254 at91_set_gpio_input(data->irq_pin, 1); 255 at91_set_deglitch(data->irq_pin, 1); 256 } 257 at91_set_gpio_input(data->det_pin, 1); 258 at91_set_deglitch(data->det_pin, 1); 259 260 /* outputs, initially off */ 261 if (data->vcc_pin) 262 at91_set_gpio_output(data->vcc_pin, 0); 263 at91_set_gpio_output(data->rst_pin, 0); 264 265 /* force poweron defaults for these pins ... */ 266 at91_set_A_periph(AT91_PIN_PC9, 0); /* A25/CFRNW */ 267 at91_set_A_periph(AT91_PIN_PC10, 0); /* NCS4/CFCS */ 268 at91_set_A_periph(AT91_PIN_PC11, 0); /* NCS5/CFCE1 */ 269 at91_set_A_periph(AT91_PIN_PC12, 0); /* NCS6/CFCE2 */ 270 271 /* nWAIT is _not_ a default setting */ 272 at91_set_A_periph(AT91_PIN_PC6, 1); /* nWAIT */ 273 274 cf_data = *data; 275 platform_device_register(&at91rm9200_cf_device); 276} 277#else 278void __init at91_add_device_cf(struct at91_cf_data *data) {} 279#endif 280 281 282/* -------------------------------------------------------------------- 283 * MMC / SD 284 * -------------------------------------------------------------------- */ 285 286#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE) 287static u64 mmc_dmamask = 0xffffffffUL; 288static struct at91_mmc_data mmc_data; 289 290static struct resource mmc_resources[] = { 291 [0] = { 292 .start = AT91RM9200_BASE_MCI, 293 .end = AT91RM9200_BASE_MCI + SZ_16K - 1, 294 .flags = IORESOURCE_MEM, 295 }, 296 [1] = { 297 .start = AT91RM9200_ID_MCI, 298 .end = AT91RM9200_ID_MCI, 299 .flags = IORESOURCE_IRQ, 300 }, 301}; 302 303static struct platform_device at91rm9200_mmc_device = { 304 .name = "at91_mci", 305 .id = -1, 306 .dev = { 307 .dma_mask = &mmc_dmamask, 308 .coherent_dma_mask = 0xffffffff, 309 .platform_data = &mmc_data, 310 }, 311 .resource = mmc_resources, 312 .num_resources = ARRAY_SIZE(mmc_resources), 313}; 314 315void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) 316{ 317 if (!data) 318 return; 319 320 /* input/irq */ 321 if (data->det_pin) { 322 at91_set_gpio_input(data->det_pin, 1); 323 at91_set_deglitch(data->det_pin, 1); 324 } 325 if (data->wp_pin) 326 at91_set_gpio_input(data->wp_pin, 1); 327 if (data->vcc_pin) 328 at91_set_gpio_output(data->vcc_pin, 0); 329 330 /* CLK */ 331 at91_set_A_periph(AT91_PIN_PA27, 0); 332 333 if (data->slot_b) { 334 /* CMD */ 335 at91_set_B_periph(AT91_PIN_PA8, 1); 336 337 /* DAT0, maybe DAT1..DAT3 */ 338 at91_set_B_periph(AT91_PIN_PA9, 1); 339 if (data->wire4) { 340 at91_set_B_periph(AT91_PIN_PA10, 1); 341 at91_set_B_periph(AT91_PIN_PA11, 1); 342 at91_set_B_periph(AT91_PIN_PA12, 1); 343 } 344 } else { 345 /* CMD */ 346 at91_set_A_periph(AT91_PIN_PA28, 1); 347 348 /* DAT0, maybe DAT1..DAT3 */ 349 at91_set_A_periph(AT91_PIN_PA29, 1); 350 if (data->wire4) { 351 at91_set_B_periph(AT91_PIN_PB3, 1); 352 at91_set_B_periph(AT91_PIN_PB4, 1); 353 at91_set_B_periph(AT91_PIN_PB5, 1); 354 } 355 } 356 357 mmc_data = *data; 358 platform_device_register(&at91rm9200_mmc_device); 359} 360#else 361void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {} 362#endif 363 364 365/* -------------------------------------------------------------------- 366 * NAND / SmartMedia 367 * -------------------------------------------------------------------- */ 368 369#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE) 370static struct at91_nand_data nand_data; 371 372#define NAND_BASE AT91_CHIPSELECT_3 373 374static struct resource nand_resources[] = { 375 { 376 .start = NAND_BASE, 377 .end = NAND_BASE + SZ_8M - 1, 378 .flags = IORESOURCE_MEM, 379 } 380}; 381 382static struct platform_device at91rm9200_nand_device = { 383 .name = "at91_nand", 384 .id = -1, 385 .dev = { 386 .platform_data = &nand_data, 387 }, 388 .resource = nand_resources, 389 .num_resources = ARRAY_SIZE(nand_resources), 390}; 391 392void __init at91_add_device_nand(struct at91_nand_data *data) 393{ 394 unsigned int csa; 395 396 if (!data) 397 return; 398 399 /* enable the address range of CS3 */ 400 csa = at91_sys_read(AT91_EBI_CSA); 401 at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA); 402 403 /* set the bus interface characteristics */ 404 at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN 405 | AT91_SMC_NWS_(5) 406 | AT91_SMC_TDF_(1) 407 | AT91_SMC_RWSETUP_(0) /* tDS Data Set up Time 30 - ns */ 408 | AT91_SMC_RWHOLD_(1) /* tDH Data Hold Time 20 - ns */ 409 ); 410 411 /* enable pin */ 412 if (data->enable_pin) 413 at91_set_gpio_output(data->enable_pin, 1); 414 415 /* ready/busy pin */ 416 if (data->rdy_pin) 417 at91_set_gpio_input(data->rdy_pin, 1); 418 419 /* card detect pin */ 420 if (data->det_pin) 421 at91_set_gpio_input(data->det_pin, 1); 422 423 at91_set_A_periph(AT91_PIN_PC1, 0); /* SMOE */ 424 at91_set_A_periph(AT91_PIN_PC3, 0); /* SMWE */ 425 426 nand_data = *data; 427 platform_device_register(&at91rm9200_nand_device); 428} 429#else 430void __init at91_add_device_nand(struct at91_nand_data *data) {} 431#endif 432 433 434/* -------------------------------------------------------------------- 435 * TWI (i2c) 436 * -------------------------------------------------------------------- */ 437 438#if defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE) 439 440static struct resource twi_resources[] = { 441 [0] = { 442 .start = AT91RM9200_BASE_TWI, 443 .end = AT91RM9200_BASE_TWI + SZ_16K - 1, 444 .flags = IORESOURCE_MEM, 445 }, 446 [1] = { 447 .start = AT91RM9200_ID_TWI, 448 .end = AT91RM9200_ID_TWI, 449 .flags = IORESOURCE_IRQ, 450 }, 451}; 452 453static struct platform_device at91rm9200_twi_device = { 454 .name = "at91_i2c", 455 .id = -1, 456 .resource = twi_resources, 457 .num_resources = ARRAY_SIZE(twi_resources), 458}; 459 460void __init at91_add_device_i2c(void) 461{ 462 /* pins used for TWI interface */ 463 at91_set_A_periph(AT91_PIN_PA25, 0); /* TWD */ 464 at91_set_multi_drive(AT91_PIN_PA25, 1); 465 466 at91_set_A_periph(AT91_PIN_PA26, 0); /* TWCK */ 467 at91_set_multi_drive(AT91_PIN_PA26, 1); 468 469 platform_device_register(&at91rm9200_twi_device); 470} 471#else 472void __init at91_add_device_i2c(void) {} 473#endif 474 475 476/* -------------------------------------------------------------------- 477 * SPI 478 * -------------------------------------------------------------------- */ 479 480#if defined(CONFIG_SPI_AT91) || defined(CONFIG_SPI_AT91_MODULE) || \ 481 defined(CONFIG_AT91_SPI) || defined(CONFIG_AT91_SPI_MODULE) 482static u64 spi_dmamask = 0xffffffffUL; 483 484static struct resource spi_resources[] = { 485 [0] = { 486 .start = AT91RM9200_BASE_SPI, 487 .end = AT91RM9200_BASE_SPI + SZ_16K - 1, 488 .flags = IORESOURCE_MEM, 489 }, 490 [1] = { 491 .start = AT91RM9200_ID_SPI, 492 .end = AT91RM9200_ID_SPI, 493 .flags = IORESOURCE_IRQ, 494 }, 495}; 496 497static struct platform_device at91rm9200_spi_device = { 498 .name = "at91_spi", 499 .id = 0, 500 .dev = { 501 .dma_mask = &spi_dmamask, 502 .coherent_dma_mask = 0xffffffff, 503 }, 504 .resource = spi_resources, 505 .num_resources = ARRAY_SIZE(spi_resources), 506}; 507 508static const unsigned spi_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 }; 509 510void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) 511{ 512 int i; 513 unsigned long cs_pin; 514 515 at91_set_A_periph(AT91_PIN_PA0, 0); /* MISO */ 516 at91_set_A_periph(AT91_PIN_PA1, 0); /* MOSI */ 517 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPCK */ 518 519 /* Enable SPI chip-selects */ 520 for (i = 0; i < nr_devices; i++) { 521 if (devices[i].controller_data) 522 cs_pin = (unsigned long) devices[i].controller_data; 523 else 524 cs_pin = spi_standard_cs[devices[i].chip_select]; 525 526#ifdef CONFIG_SPI_AT91_MANUAL_CS 527 at91_set_gpio_output(cs_pin, 1); 528#else 529 at91_set_A_periph(cs_pin, 0); 530#endif 531 532 /* pass chip-select pin to driver */ 533 devices[i].controller_data = (void *) cs_pin; 534 } 535 536 spi_register_board_info(devices, nr_devices); 537 at91_clock_associate("spi_clk", &at91rm9200_spi_device.dev, "spi"); 538 platform_device_register(&at91rm9200_spi_device); 539} 540#else 541void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {} 542#endif 543 544 545/* -------------------------------------------------------------------- 546 * RTC 547 * -------------------------------------------------------------------- */ 548 549#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE) 550static struct platform_device at91rm9200_rtc_device = { 551 .name = "at91_rtc", 552 .id = -1, 553 .num_resources = 0, 554}; 555 556static void __init at91_add_device_rtc(void) 557{ 558 platform_device_register(&at91rm9200_rtc_device); 559} 560#else 561static void __init at91_add_device_rtc(void) {} 562#endif 563 564 565/* -------------------------------------------------------------------- 566 * Watchdog 567 * -------------------------------------------------------------------- */ 568 569#if defined(CONFIG_AT91RM9200_WATCHDOG) || defined(CONFIG_AT91RM9200_WATCHDOG_MODULE) 570static struct platform_device at91rm9200_wdt_device = { 571 .name = "at91_wdt", 572 .id = -1, 573 .num_resources = 0, 574}; 575 576static void __init at91_add_device_watchdog(void) 577{ 578 platform_device_register(&at91rm9200_wdt_device); 579} 580#else 581static void __init at91_add_device_watchdog(void) {} 582#endif 583 584 585/* -------------------------------------------------------------------- 586 * LEDs 587 * -------------------------------------------------------------------- */ 588 589#if defined(CONFIG_LEDS) 590u8 at91_leds_cpu; 591u8 at91_leds_timer; 592 593void __init at91_init_leds(u8 cpu_led, u8 timer_led) 594{ 595 /* Enable GPIO to access the LEDs */ 596 at91_set_gpio_output(cpu_led, 1); 597 at91_set_gpio_output(timer_led, 1); 598 599 at91_leds_cpu = cpu_led; 600 at91_leds_timer = timer_led; 601} 602#else 603void __init at91_init_leds(u8 cpu_led, u8 timer_led) {} 604#endif 605 606 607/* -------------------------------------------------------------------- 608 * UART 609 * -------------------------------------------------------------------- */ 610 611#if defined(CONFIG_SERIAL_ATMEL) 612static struct resource dbgu_resources[] = { 613 [0] = { 614 .start = AT91_VA_BASE_SYS + AT91_DBGU, 615 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1, 616 .flags = IORESOURCE_MEM, 617 }, 618 [1] = { 619 .start = AT91_ID_SYS, 620 .end = AT91_ID_SYS, 621 .flags = IORESOURCE_IRQ, 622 }, 623}; 624 625static struct atmel_uart_data dbgu_data = { 626 .use_dma_tx = 0, 627 .use_dma_rx = 0, /* DBGU not capable of receive DMA */ 628 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU), 629}; 630 631static struct platform_device at91rm9200_dbgu_device = { 632 .name = "atmel_usart", 633 .id = 0, 634 .dev = { 635 .platform_data = &dbgu_data, 636 .coherent_dma_mask = 0xffffffff, 637 }, 638 .resource = dbgu_resources, 639 .num_resources = ARRAY_SIZE(dbgu_resources), 640}; 641 642static inline void configure_dbgu_pins(void) 643{ 644 at91_set_A_periph(AT91_PIN_PA30, 0); /* DRXD */ 645 at91_set_A_periph(AT91_PIN_PA31, 1); /* DTXD */ 646} 647 648static struct resource uart0_resources[] = { 649 [0] = { 650 .start = AT91RM9200_BASE_US0, 651 .end = AT91RM9200_BASE_US0 + SZ_16K - 1, 652 .flags = IORESOURCE_MEM, 653 }, 654 [1] = { 655 .start = AT91RM9200_ID_US0, 656 .end = AT91RM9200_ID_US0, 657 .flags = IORESOURCE_IRQ, 658 }, 659}; 660 661static struct atmel_uart_data uart0_data = { 662 .use_dma_tx = 1, 663 .use_dma_rx = 1, 664}; 665 666static struct platform_device at91rm9200_uart0_device = { 667 .name = "atmel_usart", 668 .id = 1, 669 .dev = { 670 .platform_data = &uart0_data, 671 .coherent_dma_mask = 0xffffffff, 672 }, 673 .resource = uart0_resources, 674 .num_resources = ARRAY_SIZE(uart0_resources), 675}; 676 677static inline void configure_usart0_pins(void) 678{ 679 at91_set_A_periph(AT91_PIN_PA17, 1); /* TXD0 */ 680 at91_set_A_periph(AT91_PIN_PA18, 0); /* RXD0 */ 681 at91_set_A_periph(AT91_PIN_PA20, 0); /* CTS0 */ 682 683 /* 684 * AT91RM9200 Errata #39 - RTS0 is not internally connected to PA21. 685 * We need to drive the pin manually. Default is off (RTS is active low). 686 */ 687 at91_set_gpio_output(AT91_PIN_PA21, 1); 688} 689 690static struct resource uart1_resources[] = { 691 [0] = { 692 .start = AT91RM9200_BASE_US1, 693 .end = AT91RM9200_BASE_US1 + SZ_16K - 1, 694 .flags = IORESOURCE_MEM, 695 }, 696 [1] = { 697 .start = AT91RM9200_ID_US1, 698 .end = AT91RM9200_ID_US1, 699 .flags = IORESOURCE_IRQ, 700 }, 701}; 702 703static struct atmel_uart_data uart1_data = { 704 .use_dma_tx = 1, 705 .use_dma_rx = 1, 706}; 707 708static struct platform_device at91rm9200_uart1_device = { 709 .name = "atmel_usart", 710 .id = 2, 711 .dev = { 712 .platform_data = &uart1_data, 713 .coherent_dma_mask = 0xffffffff, 714 }, 715 .resource = uart1_resources, 716 .num_resources = ARRAY_SIZE(uart1_resources), 717}; 718 719static inline void configure_usart1_pins(void) 720{ 721 at91_set_A_periph(AT91_PIN_PB18, 0); /* RI1 */ 722 at91_set_A_periph(AT91_PIN_PB19, 0); /* DTR1 */ 723 at91_set_A_periph(AT91_PIN_PB20, 1); /* TXD1 */ 724 at91_set_A_periph(AT91_PIN_PB21, 0); /* RXD1 */ 725 at91_set_A_periph(AT91_PIN_PB23, 0); /* DCD1 */ 726 at91_set_A_periph(AT91_PIN_PB24, 0); /* CTS1 */ 727 at91_set_A_periph(AT91_PIN_PB25, 0); /* DSR1 */ 728 at91_set_A_periph(AT91_PIN_PB26, 0); /* RTS1 */ 729} 730 731static struct resource uart2_resources[] = { 732 [0] = { 733 .start = AT91RM9200_BASE_US2, 734 .end = AT91RM9200_BASE_US2 + SZ_16K - 1, 735 .flags = IORESOURCE_MEM, 736 }, 737 [1] = { 738 .start = AT91RM9200_ID_US2, 739 .end = AT91RM9200_ID_US2, 740 .flags = IORESOURCE_IRQ, 741 }, 742}; 743 744static struct atmel_uart_data uart2_data = { 745 .use_dma_tx = 1, 746 .use_dma_rx = 1, 747}; 748 749static struct platform_device at91rm9200_uart2_device = { 750 .name = "atmel_usart", 751 .id = 3, 752 .dev = { 753 .platform_data = &uart2_data, 754 .coherent_dma_mask = 0xffffffff, 755 }, 756 .resource = uart2_resources, 757 .num_resources = ARRAY_SIZE(uart2_resources), 758}; 759 760static inline void configure_usart2_pins(void) 761{ 762 at91_set_A_periph(AT91_PIN_PA22, 0); /* RXD2 */ 763 at91_set_A_periph(AT91_PIN_PA23, 1); /* TXD2 */ 764} 765 766static struct resource uart3_resources[] = { 767 [0] = { 768 .start = AT91RM9200_BASE_US3, 769 .end = AT91RM9200_BASE_US3 + SZ_16K - 1, 770 .flags = IORESOURCE_MEM, 771 }, 772 [1] = { 773 .start = AT91RM9200_ID_US3, 774 .end = AT91RM9200_ID_US3, 775 .flags = IORESOURCE_IRQ, 776 }, 777}; 778 779static struct atmel_uart_data uart3_data = { 780 .use_dma_tx = 1, 781 .use_dma_rx = 1, 782}; 783 784static struct platform_device at91rm9200_uart3_device = { 785 .name = "atmel_usart", 786 .id = 4, 787 .dev = { 788 .platform_data = &uart3_data, 789 .coherent_dma_mask = 0xffffffff, 790 }, 791 .resource = uart3_resources, 792 .num_resources = ARRAY_SIZE(uart3_resources), 793}; 794 795static inline void configure_usart3_pins(void) 796{ 797 at91_set_B_periph(AT91_PIN_PA5, 1); /* TXD3 */ 798 at91_set_B_periph(AT91_PIN_PA6, 0); /* RXD3 */ 799} 800 801struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ 802struct platform_device *atmel_default_console_device; /* the serial console device */ 803 804void __init at91_init_serial(struct at91_uart_config *config) 805{ 806 int i; 807 808 /* Fill in list of supported UARTs */ 809 for (i = 0; i < config->nr_tty; i++) { 810 switch (config->tty_map[i]) { 811 case 0: 812 configure_usart0_pins(); 813 at91_uarts[i] = &at91rm9200_uart0_device; 814 at91_clock_associate("usart0_clk", &at91rm9200_uart0_device.dev, "usart"); 815 break; 816 case 1: 817 configure_usart1_pins(); 818 at91_uarts[i] = &at91rm9200_uart1_device; 819 at91_clock_associate("usart1_clk", &at91rm9200_uart1_device.dev, "usart"); 820 break; 821 case 2: 822 configure_usart2_pins(); 823 at91_uarts[i] = &at91rm9200_uart2_device; 824 at91_clock_associate("usart2_clk", &at91rm9200_uart2_device.dev, "usart"); 825 break; 826 case 3: 827 configure_usart3_pins(); 828 at91_uarts[i] = &at91rm9200_uart3_device; 829 at91_clock_associate("usart3_clk", &at91rm9200_uart3_device.dev, "usart"); 830 break; 831 case 4: 832 configure_dbgu_pins(); 833 at91_uarts[i] = &at91rm9200_dbgu_device; 834 at91_clock_associate("mck", &at91rm9200_dbgu_device.dev, "usart"); 835 break; 836 default: 837 continue; 838 } 839 at91_uarts[i]->id = i; /* update ID number to mapped ID */ 840 } 841 842 /* Set serial console device */ 843 if (config->console_tty < ATMEL_MAX_UART) 844 atmel_default_console_device = at91_uarts[config->console_tty]; 845 if (!atmel_default_console_device) 846 printk(KERN_INFO "AT91: No default serial console defined.\n"); 847} 848 849void __init at91_add_device_serial(void) 850{ 851 int i; 852 853 for (i = 0; i < ATMEL_MAX_UART; i++) { 854 if (at91_uarts[i]) 855 platform_device_register(at91_uarts[i]); 856 } 857} 858#else 859void __init at91_init_serial(struct at91_uart_config *config) {} 860void __init at91_add_device_serial(void) {} 861#endif 862 863 864/* -------------------------------------------------------------------- */ 865 866/* 867 * These devices are always present and don't need any board-specific 868 * setup. 869 */ 870static int __init at91_add_standard_devices(void) 871{ 872 at91_add_device_rtc(); 873 at91_add_device_watchdog(); 874 return 0; 875} 876 877arch_initcall(at91_add_standard_devices); 878