1/* 2 * linux/arch/arm/kernel/head.S 3 * 4 * Copyright (C) 1994-2002 Russell King 5 * Copyright (c) 2003 ARM Limited 6 * All Rights Reserved 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Kernel startup code for all 32-bit CPUs 13 */ 14#include <linux/linkage.h> 15#include <linux/init.h> 16 17#include <asm/assembler.h> 18#include <asm/domain.h> 19#include <asm/ptrace.h> 20#include <asm/asm-offsets.h> 21#include <asm/memory.h> 22#include <asm/thread_info.h> 23#include <asm/system.h> 24 25#if (PHYS_OFFSET & 0x001fffff) 26#error "PHYS_OFFSET must be at an even 2MiB boundary!" 27#endif 28 29#define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET) 30#define KERNEL_RAM_PADDR (PHYS_OFFSET + TEXT_OFFSET) 31 32/* 33 * swapper_pg_dir is the virtual address of the initial page table. 34 * We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must 35 * make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect 36 * the least significant 16 bits to be 0x8000, but we could probably 37 * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000. 38 */ 39#if (KERNEL_RAM_VADDR & 0xffff) != 0x8000 40#error KERNEL_RAM_VADDR must start at 0xXXXX8000 41#endif 42 43 .globl swapper_pg_dir 44 .equ swapper_pg_dir, KERNEL_RAM_VADDR - 0x4000 45 46 .macro pgtbl, rd 47 ldr \rd, =(KERNEL_RAM_PADDR - 0x4000) 48 .endm 49 50#ifdef CONFIG_XIP_KERNEL 51#define KERNEL_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR) 52#define KERNEL_END _edata_loc 53#else 54#define KERNEL_START KERNEL_RAM_VADDR 55#define KERNEL_END _end 56#endif 57 58/* 59 * Kernel startup entry point. 60 * --------------------------- 61 * 62 * This is normally called from the decompressor code. The requirements 63 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0, 64 * r1 = machine nr. 65 * 66 * This code is mostly position independent, so if you link the kernel at 67 * 0xc0008000, you call this at __pa(0xc0008000). 68 * 69 * See linux/arch/arm/tools/mach-types for the complete list of machine 70 * numbers for r1. 71 * 72 * We're trying to keep crap to a minimum; DO NOT add any machine specific 73 * crap here - that's what the boot loader (or in extreme, well justified 74 * circumstances, zImage) is for. 75 */ 76 .section ".text.head", "ax" 77 .type stext, %function 78ENTRY(stext) 79 msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode 80 @ and irqs disabled 81 mrc p15, 0, r9, c0, c0 @ get processor id 82 bl __lookup_processor_type @ r5=procinfo r9=cpuid 83 movs r10, r5 @ invalid processor (r5=0)? 84 beq __error_p @ yes, error 'p' 85 bl __lookup_machine_type @ r5=machinfo 86 movs r8, r5 @ invalid machine (r5=0)? 87 beq __error_a @ yes, error 'a' 88 bl __create_page_tables 89 90 /* 91 * The following calls CPU specific code in a position independent 92 * manner. See arch/arm/mm/proc-*.S for details. r10 = base of 93 * xxx_proc_info structure selected by __lookup_machine_type 94 * above. On return, the CPU will be ready for the MMU to be 95 * turned on, and r0 will hold the CPU control register value. 96 */ 97 ldr r13, __switch_data @ address to jump to after 98 @ mmu has been enabled 99 adr lr, __enable_mmu @ return (PIC) address 100 add pc, r10, #PROCINFO_INITFUNC 101 102#if defined(CONFIG_SMP) 103 .type secondary_startup, #function 104ENTRY(secondary_startup) 105 /* 106 * Common entry point for secondary CPUs. 107 * 108 * Ensure that we're in SVC mode, and IRQs are disabled. Lookup 109 * the processor type - there is no need to check the machine type 110 * as it has already been validated by the primary processor. 111 */ 112 msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE 113 mrc p15, 0, r9, c0, c0 @ get processor id 114 bl __lookup_processor_type 115 movs r10, r5 @ invalid processor? 116 moveq r0, #'p' @ yes, error 'p' 117 beq __error 118 119 /* 120 * Use the page tables supplied from __cpu_up. 121 */ 122 adr r4, __secondary_data 123 ldmia r4, {r5, r7, r13} @ address to jump to after 124 sub r4, r4, r5 @ mmu has been enabled 125 ldr r4, [r7, r4] @ get secondary_data.pgdir 126 adr lr, __enable_mmu @ return address 127 add pc, r10, #PROCINFO_INITFUNC @ initialise processor 128 @ (return control reg) 129 130 /* 131 * r6 = &secondary_data 132 */ 133ENTRY(__secondary_switched) 134 ldr sp, [r7, #4] @ get secondary_data.stack 135 mov fp, #0 136 b secondary_start_kernel 137 138 .type __secondary_data, %object 139__secondary_data: 140 .long . 141 .long secondary_data 142 .long __secondary_switched 143#endif /* defined(CONFIG_SMP) */ 144 145 146 147/* 148 * Setup common bits before finally enabling the MMU. Essentially 149 * this is just loading the page table pointer and domain access 150 * registers. 151 */ 152 .type __enable_mmu, %function 153__enable_mmu: 154#ifdef CONFIG_ALIGNMENT_TRAP 155 orr r0, r0, #CR_A 156#else 157 bic r0, r0, #CR_A 158#endif 159#ifdef CONFIG_CPU_DCACHE_DISABLE 160 bic r0, r0, #CR_C 161#endif 162#ifdef CONFIG_CPU_BPREDICT_DISABLE 163 bic r0, r0, #CR_Z 164#endif 165#ifdef CONFIG_CPU_ICACHE_DISABLE 166 bic r0, r0, #CR_I 167#endif 168 mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \ 169 domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \ 170 domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \ 171 domain_val(DOMAIN_IO, DOMAIN_CLIENT)) 172 mcr p15, 0, r5, c3, c0, 0 @ load domain access register 173 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer 174 b __turn_mmu_on 175 176/* 177 * Enable the MMU. This completely changes the structure of the visible 178 * memory space. You will not be able to trace execution through this. 179 * If you have an enquiry about this, *please* check the linux-arm-kernel 180 * mailing list archives BEFORE sending another post to the list. 181 * 182 * r0 = cp#15 control register 183 * r13 = *virtual* address to jump to upon completion 184 * 185 * other registers depend on the function called upon completion 186 */ 187 .align 5 188 .type __turn_mmu_on, %function 189__turn_mmu_on: 190 mov r0, r0 191 mcr p15, 0, r0, c1, c0, 0 @ write control reg 192 mrc p15, 0, r3, c0, c0, 0 @ read id reg 193 mov r3, r3 194 mov r3, r3 195 mov pc, r13 196 197 198 199/* 200 * Setup the initial page tables. We only setup the barest 201 * amount which are required to get the kernel running, which 202 * generally means mapping in the kernel code. 203 * 204 * r8 = machinfo 205 * r9 = cpuid 206 * r10 = procinfo 207 * 208 * Returns: 209 * r0, r3, r6, r7 corrupted 210 * r4 = physical page table address 211 */ 212 .type __create_page_tables, %function 213__create_page_tables: 214 pgtbl r4 @ page table address 215 216 /* 217 * Clear the 16K level 1 swapper page table 218 */ 219 mov r0, r4 220 mov r3, #0 221 add r6, r0, #0x4000 2221: str r3, [r0], #4 223 str r3, [r0], #4 224 str r3, [r0], #4 225 str r3, [r0], #4 226 teq r0, r6 227 bne 1b 228 229 ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags 230 231 /* 232 * Create identity mapping for first MB of kernel to 233 * cater for the MMU enable. This identity mapping 234 * will be removed by paging_init(). We use our current program 235 * counter to determine corresponding section base address. 236 */ 237 mov r6, pc, lsr #20 @ start of kernel section 238 orr r3, r7, r6, lsl #20 @ flags + kernel base 239 str r3, [r4, r6, lsl #2] @ identity mapping 240 241 /* 242 * Now setup the pagetables for our kernel direct 243 * mapped region. 244 */ 245 add r0, r4, #(KERNEL_START & 0xff000000) >> 18 246 str r3, [r0, #(KERNEL_START & 0x00f00000) >> 18]! 247 ldr r6, =(KERNEL_END - 1) 248 add r0, r0, #4 249 add r6, r4, r6, lsr #18 2501: cmp r0, r6 251 add r3, r3, #1 << 20 252 strls r3, [r0], #4 253 bls 1b 254 255#ifdef CONFIG_XIP_KERNEL 256 /* 257 * Map some ram to cover our .data and .bss areas. 258 */ 259 orr r3, r7, #(KERNEL_RAM_PADDR & 0xff000000) 260 .if (KERNEL_RAM_PADDR & 0x00f00000) 261 orr r3, r3, #(KERNEL_RAM_PADDR & 0x00f00000) 262 .endif 263 add r0, r4, #(KERNEL_RAM_VADDR & 0xff000000) >> 18 264 str r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> 18]! 265 ldr r6, =(_end - 1) 266 add r0, r0, #4 267 add r6, r4, r6, lsr #18 2681: cmp r0, r6 269 add r3, r3, #1 << 20 270 strls r3, [r0], #4 271 bls 1b 272#endif 273 274 /* 275 * Then map first 1MB of ram in case it contains our boot params. 276 */ 277 add r0, r4, #PAGE_OFFSET >> 18 278 orr r6, r7, #(PHYS_OFFSET & 0xff000000) 279 .if (PHYS_OFFSET & 0x00f00000) 280 orr r6, r6, #(PHYS_OFFSET & 0x00f00000) 281 .endif 282 str r6, [r0] 283 284#ifdef CONFIG_DEBUG_LL 285 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags 286 /* 287 * Map in IO space for serial debugging. 288 * This allows debug messages to be output 289 * via a serial console before paging_init. 290 */ 291 ldr r3, [r8, #MACHINFO_PGOFFIO] 292 add r0, r4, r3 293 rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long) 294 cmp r3, #0x0800 @ limit to 512MB 295 movhi r3, #0x0800 296 add r6, r0, r3 297 ldr r3, [r8, #MACHINFO_PHYSIO] 298 orr r3, r3, r7 2991: str r3, [r0], #4 300 add r3, r3, #1 << 20 301 teq r0, r6 302 bne 1b 303#if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS) 304 /* 305 * If we're using the NetWinder or CATS, we also need to map 306 * in the 16550-type serial port for the debug messages 307 */ 308 add r0, r4, #0xff000000 >> 18 309 orr r3, r7, #0x7c000000 310 str r3, [r0] 311#endif 312#ifdef CONFIG_ARCH_RPC 313 /* 314 * Map in screen at 0x02000000 & SCREEN2_BASE 315 * Similar reasons here - for debug. This is 316 * only for Acorn RiscPC architectures. 317 */ 318 add r0, r4, #0x02000000 >> 18 319 orr r3, r7, #0x02000000 320 str r3, [r0] 321 add r0, r4, #0xd8000000 >> 18 322 str r3, [r0] 323#endif 324#endif 325 mov pc, lr 326 .ltorg 327 328#include "head-common.S" 329