1/* 2 * linux/arch/alpha/kernel/sys_cabriolet.c 3 * 4 * Copyright (C) 1995 David A Rusling 5 * Copyright (C) 1996 Jay A Estabrook 6 * Copyright (C) 1998, 1999, 2000 Richard Henderson 7 * 8 * Code supporting the Cabriolet (AlphaPC64), EB66+, and EB164, 9 * PC164 and LX164. 10 */ 11 12#include <linux/kernel.h> 13#include <linux/types.h> 14#include <linux/mm.h> 15#include <linux/sched.h> 16#include <linux/pci.h> 17#include <linux/init.h> 18#include <linux/bitops.h> 19 20#include <asm/ptrace.h> 21#include <asm/system.h> 22#include <asm/dma.h> 23#include <asm/irq.h> 24#include <asm/mmu_context.h> 25#include <asm/io.h> 26#include <asm/pgtable.h> 27#include <asm/core_apecs.h> 28#include <asm/core_cia.h> 29#include <asm/core_lca.h> 30#include <asm/tlbflush.h> 31 32#include "proto.h" 33#include "irq_impl.h" 34#include "pci_impl.h" 35#include "machvec_impl.h" 36 37 38/* Note mask bit is true for DISABLED irqs. */ 39static unsigned long cached_irq_mask = ~0UL; 40 41static inline void 42cabriolet_update_irq_hw(unsigned int irq, unsigned long mask) 43{ 44 int ofs = (irq - 16) / 8; 45 outb(mask >> (16 + ofs * 8), 0x804 + ofs); 46} 47 48static inline void 49cabriolet_enable_irq(unsigned int irq) 50{ 51 cabriolet_update_irq_hw(irq, cached_irq_mask &= ~(1UL << irq)); 52} 53 54static void 55cabriolet_disable_irq(unsigned int irq) 56{ 57 cabriolet_update_irq_hw(irq, cached_irq_mask |= 1UL << irq); 58} 59 60static unsigned int 61cabriolet_startup_irq(unsigned int irq) 62{ 63 cabriolet_enable_irq(irq); 64 return 0; /* never anything pending */ 65} 66 67static void 68cabriolet_end_irq(unsigned int irq) 69{ 70 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 71 cabriolet_enable_irq(irq); 72} 73 74static struct hw_interrupt_type cabriolet_irq_type = { 75 .typename = "CABRIOLET", 76 .startup = cabriolet_startup_irq, 77 .shutdown = cabriolet_disable_irq, 78 .enable = cabriolet_enable_irq, 79 .disable = cabriolet_disable_irq, 80 .ack = cabriolet_disable_irq, 81 .end = cabriolet_end_irq, 82}; 83 84static void 85cabriolet_device_interrupt(unsigned long v) 86{ 87 unsigned long pld; 88 unsigned int i; 89 90 /* Read the interrupt summary registers */ 91 pld = inb(0x804) | (inb(0x805) << 8) | (inb(0x806) << 16); 92 93 /* 94 * Now for every possible bit set, work through them and call 95 * the appropriate interrupt handler. 96 */ 97 while (pld) { 98 i = ffz(~pld); 99 pld &= pld - 1; /* clear least bit set */ 100 if (i == 4) { 101 isa_device_interrupt(v); 102 } else { 103 handle_irq(16 + i); 104 } 105 } 106} 107 108static void __init 109common_init_irq(void (*srm_dev_int)(unsigned long v)) 110{ 111 init_i8259a_irqs(); 112 113 if (alpha_using_srm) { 114 alpha_mv.device_interrupt = srm_dev_int; 115 init_srm_irqs(35, 0); 116 } 117 else { 118 long i; 119 120 outb(0xff, 0x804); 121 outb(0xff, 0x805); 122 outb(0xff, 0x806); 123 124 for (i = 16; i < 35; ++i) { 125 irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; 126 irq_desc[i].chip = &cabriolet_irq_type; 127 } 128 } 129 130 common_init_isa_dma(); 131 setup_irq(16+4, &isa_cascade_irqaction); 132} 133 134#ifndef CONFIG_ALPHA_PC164 135static void __init 136cabriolet_init_irq(void) 137{ 138 common_init_irq(srm_device_interrupt); 139} 140#endif 141 142#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_PC164) 143 144static void 145pc164_srm_device_interrupt(unsigned long v) 146{ 147 __min_ipl = getipl(); 148 srm_device_interrupt(v); 149 __min_ipl = 0; 150} 151 152static void 153pc164_device_interrupt(unsigned long v) 154{ 155 __min_ipl = getipl(); 156 cabriolet_device_interrupt(v); 157 __min_ipl = 0; 158} 159 160static void __init 161pc164_init_irq(void) 162{ 163 common_init_irq(pc164_srm_device_interrupt); 164} 165#endif 166 167/* 168 * The EB66+ is very similar to the EB66 except that it does not have 169 * the on-board NCR and Tulip chips. In the code below, I have used 170 * slot number to refer to the id select line and *not* the slot 171 * number used in the EB66+ documentation. However, in the table, 172 * I've given the slot number, the id select line and the Jxx number 173 * that's printed on the board. The interrupt pins from the PCI slots 174 * are wired into 3 interrupt summary registers at 0x804, 0x805 and 175 * 0x806 ISA. 176 * 177 * In the table, -1 means don't assign an IRQ number. This is usually 178 * because it is the Saturn IO (SIO) PCI/ISA Bridge Chip. 179 */ 180 181static inline int __init 182eb66p_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 183{ 184 static char irq_tab[5][5] __initdata = { 185 /*INT INTA INTB INTC INTD */ 186 {16+0, 16+0, 16+5, 16+9, 16+13}, /* IdSel 6, slot 0, J25 */ 187 {16+1, 16+1, 16+6, 16+10, 16+14}, /* IdSel 7, slot 1, J26 */ 188 { -1, -1, -1, -1, -1}, /* IdSel 8, SIO */ 189 {16+2, 16+2, 16+7, 16+11, 16+15}, /* IdSel 9, slot 2, J27 */ 190 {16+3, 16+3, 16+8, 16+12, 16+6} /* IdSel 10, slot 3, J28 */ 191 }; 192 const long min_idsel = 6, max_idsel = 10, irqs_per_slot = 5; 193 return COMMON_TABLE_LOOKUP; 194} 195 196 197/* 198 * The AlphaPC64 is very similar to the EB66+ except that its slots 199 * are numbered differently. In the code below, I have used slot 200 * number to refer to the id select line and *not* the slot number 201 * used in the AlphaPC64 documentation. However, in the table, I've 202 * given the slot number, the id select line and the Jxx number that's 203 * printed on the board. The interrupt pins from the PCI slots are 204 * wired into 3 interrupt summary registers at 0x804, 0x805 and 0x806 205 * ISA. 206 * 207 * In the table, -1 means don't assign an IRQ number. This is usually 208 * because it is the Saturn IO (SIO) PCI/ISA Bridge Chip. 209 */ 210 211static inline int __init 212cabriolet_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 213{ 214 static char irq_tab[5][5] __initdata = { 215 /*INT INTA INTB INTC INTD */ 216 { 16+2, 16+2, 16+7, 16+11, 16+15}, /* IdSel 5, slot 2, J21 */ 217 { 16+0, 16+0, 16+5, 16+9, 16+13}, /* IdSel 6, slot 0, J19 */ 218 { 16+1, 16+1, 16+6, 16+10, 16+14}, /* IdSel 7, slot 1, J20 */ 219 { -1, -1, -1, -1, -1}, /* IdSel 8, SIO */ 220 { 16+3, 16+3, 16+8, 16+12, 16+16} /* IdSel 9, slot 3, J22 */ 221 }; 222 const long min_idsel = 5, max_idsel = 9, irqs_per_slot = 5; 223 return COMMON_TABLE_LOOKUP; 224} 225 226static inline void __init 227cabriolet_init_pci(void) 228{ 229 common_init_pci(); 230 ns87312_enable_ide(0x398); 231} 232 233static inline void __init 234cia_cab_init_pci(void) 235{ 236 cia_init_pci(); 237 ns87312_enable_ide(0x398); 238} 239 240/* 241 * The PC164 and LX164 have 19 PCI interrupts, four from each of the four 242 * PCI slots, the SIO, PCI/IDE, and USB. 243 * 244 * Each of the interrupts can be individually masked. This is 245 * accomplished by setting the appropriate bit in the mask register. 246 * A bit is set by writing a "1" to the desired position in the mask 247 * register and cleared by writing a "0". There are 3 mask registers 248 * located at ISA address 804h, 805h and 806h. 249 * 250 * An I/O read at ISA address 804h, 805h, 806h will return the 251 * state of the 11 PCI interrupts and not the state of the MASKED 252 * interrupts. 253 * 254 * Note: A write to I/O 804h, 805h, and 806h the mask register will be 255 * updated. 256 * 257 * 258 * ISA DATA<7:0> 259 * ISA +--------------------------------------------------------------+ 260 * ADDRESS | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 261 * +==============================================================+ 262 * 0x804 | INTB0 | USB | IDE | SIO | INTA3 |INTA2 | INTA1 | INTA0 | 263 * +--------------------------------------------------------------+ 264 * 0x805 | INTD0 | INTC3 | INTC2 | INTC1 | INTC0 |INTB3 | INTB2 | INTB1 | 265 * +--------------------------------------------------------------+ 266 * 0x806 | Rsrv | Rsrv | Rsrv | Rsrv | Rsrv |INTD3 | INTD2 | INTD1 | 267 * +--------------------------------------------------------------+ 268 * * Rsrv = reserved bits 269 * Note: The mask register is write-only. 270 * 271 * IdSel 272 * 5 32 bit PCI option slot 2 273 * 6 64 bit PCI option slot 0 274 * 7 64 bit PCI option slot 1 275 * 8 Saturn I/O 276 * 9 32 bit PCI option slot 3 277 * 10 USB 278 * 11 IDE 279 * 280 */ 281 282static inline int __init 283alphapc164_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 284{ 285 static char irq_tab[7][5] __initdata = { 286 /*INT INTA INTB INTC INTD */ 287 { 16+2, 16+2, 16+9, 16+13, 16+17}, /* IdSel 5, slot 2, J20 */ 288 { 16+0, 16+0, 16+7, 16+11, 16+15}, /* IdSel 6, slot 0, J29 */ 289 { 16+1, 16+1, 16+8, 16+12, 16+16}, /* IdSel 7, slot 1, J26 */ 290 { -1, -1, -1, -1, -1}, /* IdSel 8, SIO */ 291 { 16+3, 16+3, 16+10, 16+14, 16+18}, /* IdSel 9, slot 3, J19 */ 292 { 16+6, 16+6, 16+6, 16+6, 16+6}, /* IdSel 10, USB */ 293 { 16+5, 16+5, 16+5, 16+5, 16+5} /* IdSel 11, IDE */ 294 }; 295 const long min_idsel = 5, max_idsel = 11, irqs_per_slot = 5; 296 return COMMON_TABLE_LOOKUP; 297} 298 299static inline void __init 300alphapc164_init_pci(void) 301{ 302 cia_init_pci(); 303 SMC93x_Init(); 304} 305 306 307/* 308 * The System Vector 309 */ 310 311#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_CABRIOLET) 312struct alpha_machine_vector cabriolet_mv __initmv = { 313 .vector_name = "Cabriolet", 314 DO_EV4_MMU, 315 DO_DEFAULT_RTC, 316 DO_APECS_IO, 317 .machine_check = apecs_machine_check, 318 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, 319 .min_io_address = DEFAULT_IO_BASE, 320 .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE, 321 322 .nr_irqs = 35, 323 .device_interrupt = cabriolet_device_interrupt, 324 325 .init_arch = apecs_init_arch, 326 .init_irq = cabriolet_init_irq, 327 .init_rtc = common_init_rtc, 328 .init_pci = cabriolet_init_pci, 329 .pci_map_irq = cabriolet_map_irq, 330 .pci_swizzle = common_swizzle, 331}; 332#ifndef CONFIG_ALPHA_EB64P 333ALIAS_MV(cabriolet) 334#endif 335#endif 336 337#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EB164) 338struct alpha_machine_vector eb164_mv __initmv = { 339 .vector_name = "EB164", 340 DO_EV5_MMU, 341 DO_DEFAULT_RTC, 342 DO_CIA_IO, 343 .machine_check = cia_machine_check, 344 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, 345 .min_io_address = DEFAULT_IO_BASE, 346 .min_mem_address = CIA_DEFAULT_MEM_BASE, 347 348 .nr_irqs = 35, 349 .device_interrupt = cabriolet_device_interrupt, 350 351 .init_arch = cia_init_arch, 352 .init_irq = cabriolet_init_irq, 353 .init_rtc = common_init_rtc, 354 .init_pci = cia_cab_init_pci, 355 .kill_arch = cia_kill_arch, 356 .pci_map_irq = cabriolet_map_irq, 357 .pci_swizzle = common_swizzle, 358}; 359ALIAS_MV(eb164) 360#endif 361 362#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EB66P) 363struct alpha_machine_vector eb66p_mv __initmv = { 364 .vector_name = "EB66+", 365 DO_EV4_MMU, 366 DO_DEFAULT_RTC, 367 DO_LCA_IO, 368 .machine_check = lca_machine_check, 369 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, 370 .min_io_address = DEFAULT_IO_BASE, 371 .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE, 372 373 .nr_irqs = 35, 374 .device_interrupt = cabriolet_device_interrupt, 375 376 .init_arch = lca_init_arch, 377 .init_irq = cabriolet_init_irq, 378 .init_rtc = common_init_rtc, 379 .init_pci = cabriolet_init_pci, 380 .pci_map_irq = eb66p_map_irq, 381 .pci_swizzle = common_swizzle, 382}; 383ALIAS_MV(eb66p) 384#endif 385 386#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_LX164) 387struct alpha_machine_vector lx164_mv __initmv = { 388 .vector_name = "LX164", 389 DO_EV5_MMU, 390 DO_DEFAULT_RTC, 391 DO_PYXIS_IO, 392 .machine_check = cia_machine_check, 393 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, 394 .min_io_address = DEFAULT_IO_BASE, 395 .min_mem_address = DEFAULT_MEM_BASE, 396 .pci_dac_offset = PYXIS_DAC_OFFSET, 397 398 .nr_irqs = 35, 399 .device_interrupt = cabriolet_device_interrupt, 400 401 .init_arch = pyxis_init_arch, 402 .init_irq = cabriolet_init_irq, 403 .init_rtc = common_init_rtc, 404 .init_pci = alphapc164_init_pci, 405 .kill_arch = cia_kill_arch, 406 .pci_map_irq = alphapc164_map_irq, 407 .pci_swizzle = common_swizzle, 408}; 409ALIAS_MV(lx164) 410#endif 411 412#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_PC164) 413struct alpha_machine_vector pc164_mv __initmv = { 414 .vector_name = "PC164", 415 DO_EV5_MMU, 416 DO_DEFAULT_RTC, 417 DO_CIA_IO, 418 .machine_check = cia_machine_check, 419 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, 420 .min_io_address = DEFAULT_IO_BASE, 421 .min_mem_address = CIA_DEFAULT_MEM_BASE, 422 423 .nr_irqs = 35, 424 .device_interrupt = pc164_device_interrupt, 425 426 .init_arch = cia_init_arch, 427 .init_irq = pc164_init_irq, 428 .init_rtc = common_init_rtc, 429 .init_pci = alphapc164_init_pci, 430 .kill_arch = cia_kill_arch, 431 .pci_map_irq = alphapc164_map_irq, 432 .pci_swizzle = common_swizzle, 433}; 434ALIAS_MV(pc164) 435#endif 436