1/* 2 * Misc utility routines for accessing the SOC Interconnects 3 * of Broadcom HNBU chips. 4 * 5 * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 14 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 16 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 17 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 * $Id: siutils.h 401759 2013-05-13 16:08:08Z $ 20 */ 21 22#ifndef _siutils_h_ 23#define _siutils_h_ 24 25#if defined(WLC_HIGH) && !defined(WLC_LOW) 26#include "bcm_rpc.h" 27#endif 28 29#include <bcmutils.h> 30/* 31 * Data structure to export all chip specific common variables 32 * public (read-only) portion of siutils handle returned by si_attach()/si_kattach() 33 */ 34struct si_pub { 35 uint socitype; /* SOCI_SB, SOCI_AI */ 36 37 uint bustype; /* SI_BUS, PCI_BUS */ 38 uint buscoretype; /* PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */ 39 uint buscorerev; /* buscore rev */ 40 uint buscoreidx; /* buscore index */ 41 int ccrev; /* chip common core rev */ 42 uint32 cccaps; /* chip common capabilities */ 43 uint32 cccaps_ext; /* chip common capabilities extension */ 44 int pmurev; /* pmu core rev */ 45 uint32 pmucaps; /* pmu capabilities */ 46 uint boardtype; /* board type */ 47 uint boardrev; /* board rev */ 48 uint boardvendor; /* board vendor */ 49 uint boardflags; /* board flags */ 50 uint boardflags2; /* board flags2 */ 51 uint chip; /* chip number */ 52 uint chiprev; /* chip revision */ 53 uint chippkg; /* chip package option */ 54 uint32 chipst; /* chip status */ 55 bool issim; /* chip is in simulation or emulation */ 56 uint socirev; /* SOC interconnect rev */ 57 bool pci_pr32414; 58 59#if defined(WLC_HIGH) && !defined(WLC_LOW) 60 rpc_info_t *rpc; 61#endif 62#ifdef SI_ENUM_BASE_VARIABLE 63 uint32 si_enum_base; 64#endif /* SI_ENUM_BASE_VARIABLE */ 65}; 66 67/* for HIGH_ONLY driver, the si_t must be writable to allow states sync from BMAC to HIGH driver 68 * for monolithic driver, it is readonly to prevent accident change 69 */ 70#if defined(WLC_HIGH) && !defined(WLC_LOW) 71typedef struct si_pub si_t; 72#else 73typedef const struct si_pub si_t; 74#endif 75 76#ifdef ATE_BUILD 77typedef struct _ate_params { 78 void* wl; 79 uint8 gpio_input; 80 uint8 gpio_output; 81 bool cmd_proceed; 82 uint16 cmd_idx; 83 bool ate_cmd_done; 84} ate_params_t; 85#endif /* ATE_BUILD */ 86 87/* 88 * Many of the routines below take an 'sih' handle as their first arg. 89 * Allocate this by calling si_attach(). Free it by calling si_detach(). 90 * At any one time, the sih is logically focused on one particular si core 91 * (the "current core"). 92 * Use si_setcore() or si_setcoreidx() to change the association to another core. 93 */ 94#define SI_OSH NULL /* Use for si_kattach when no osh is available */ 95 96#define BADIDX (SI_MAXCORES + 1) 97 98/* clkctl xtal what flags */ 99#define XTAL 0x1 /* primary crystal oscillator (2050) */ 100#define PLL 0x2 /* main chip pll */ 101 102/* clkctl clk mode */ 103#define CLK_FAST 0 /* force fast (pll) clock */ 104#define CLK_DYNAMIC 2 /* enable dynamic clock control */ 105 106/* GPIO usage priorities */ 107#define GPIO_DRV_PRIORITY 0 /* Driver */ 108#define GPIO_APP_PRIORITY 1 /* Application */ 109#define GPIO_HI_PRIORITY 2 /* Highest priority. Ignore GPIO reservation */ 110 111/* GPIO pull up/down */ 112#define GPIO_PULLUP 0 113#define GPIO_PULLDN 1 114 115/* GPIO event regtype */ 116#define GPIO_REGEVT 0 /* GPIO register event */ 117#define GPIO_REGEVT_INTMSK 1 /* GPIO register event int mask */ 118#define GPIO_REGEVT_INTPOL 2 /* GPIO register event int polarity */ 119 120/* device path */ 121#define SI_DEVPATH_BUFSZ 16 /* min buffer size in bytes */ 122 123/* SI routine enumeration: to be used by update function with multiple hooks */ 124#define SI_DOATTACH 1 125#define SI_PCIDOWN 2 126#define SI_PCIUP 3 127 128#if defined(BCMQT) 129#define ISSIM_ENAB(sih) TRUE 130#else 131#define ISSIM_ENAB(sih) FALSE 132#endif 133 134/* PMU clock/power control */ 135#if defined(BCMPMUCTL) 136#define PMUCTL_ENAB(sih) (BCMPMUCTL) 137#else 138#define PMUCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PMU) 139#endif 140 141/* chipcommon clock/power control (exclusive with PMU's) */ 142#if defined(BCMPMUCTL) && BCMPMUCTL 143#define CCCTL_ENAB(sih) (0) 144#define CCPLL_ENAB(sih) (0) 145#else 146#define CCCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PWR_CTL) 147#define CCPLL_ENAB(sih) ((sih)->cccaps & CC_CAP_PLL_MASK) 148#endif 149 150typedef void (*gpio_handler_t)(uint32 stat, void *arg); 151/* External BT Coex enable mask */ 152#define CC_BTCOEX_EN_MASK 0x01 153/* External PA enable mask */ 154#define GPIO_CTRL_EPA_EN_MASK 0x40 155/* WL/BT control enable mask */ 156#define GPIO_CTRL_5_6_EN_MASK 0x60 157#define GPIO_CTRL_7_6_EN_MASK 0xC0 158#define GPIO_OUT_7_EN_MASK 0x80 159 160 161#if defined(WLOFFLD) 162/* CR4 specific defines used by the host driver */ 163#define SI_CR4_CAP (0x04) 164#define SI_CR4_BANKIDX (0x40) 165#define SI_CR4_BANKINFO (0x44) 166 167#define ARMCR4_TCBBNB_MASK 0xf0 168#define ARMCR4_TCBBNB_SHIFT 4 169#define ARMCR4_TCBANB_MASK 0xf 170#define ARMCR4_TCBANB_SHIFT 0 171 172#define SICF_CPUHALT (0x0020) 173#define ARMCR4_BSZ_MASK 0x3f 174#define ARMCR4_BSZ_MULT 8192 175#endif 176 177/* === exported functions === */ 178extern si_t *si_attach(uint pcidev, osl_t *osh, void *regs, uint bustype, 179 void *sdh, char **vars, uint *varsz); 180extern si_t *si_kattach(osl_t *osh); 181extern void si_detach(si_t *sih); 182extern bool si_pci_war16165(si_t *sih); 183 184extern uint si_corelist(si_t *sih, uint coreid[]); 185extern uint si_coreid(si_t *sih); 186extern uint si_flag(si_t *sih); 187extern uint si_flag_alt(si_t *sih); 188extern uint si_intflag(si_t *sih); 189extern uint si_coreidx(si_t *sih); 190extern uint si_coreunit(si_t *sih); 191extern uint si_corevendor(si_t *sih); 192extern uint si_corerev(si_t *sih); 193extern void *si_osh(si_t *sih); 194extern void si_setosh(si_t *sih, osl_t *osh); 195extern uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val); 196extern void *si_coreregs(si_t *sih); 197extern uint si_wrapperreg(si_t *sih, uint32 offset, uint32 mask, uint32 val); 198extern uint si_core_wrapperreg(si_t *sih, uint32 coreidx, uint32 offset, uint32 mask, uint32 val); 199extern void *si_wrapperregs(si_t *sih); 200extern uint32 si_core_cflags(si_t *sih, uint32 mask, uint32 val); 201extern void si_core_cflags_wo(si_t *sih, uint32 mask, uint32 val); 202extern uint32 si_core_sflags(si_t *sih, uint32 mask, uint32 val); 203#ifdef WLC_HIGH_ONLY 204extern bool wlc_bmac_iscoreup(si_t *sih); 205#define si_iscoreup(sih) wlc_bmac_iscoreup(sih) 206#else 207extern bool si_iscoreup(si_t *sih); 208#endif /* __CONFIG_USBAP__ */ 209extern uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit); 210extern void *si_setcoreidx(si_t *sih, uint coreidx); 211extern void *si_setcore(si_t *sih, uint coreid, uint coreunit); 212 213#ifdef WLC_LOW 214extern uint si_corereg_ifup(si_t *sih, uint core_id, uint regoff, uint mask, uint val); 215extern void si_lowpwr_opt(si_t *sih); 216#endif /* WLC_LOW */ 217 218extern void *si_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val); 219extern void si_restore_core(si_t *sih, uint coreid, uint intr_val); 220extern int si_numaddrspaces(si_t *sih); 221extern uint32 si_addrspace(si_t *sih, uint asidx); 222extern uint32 si_addrspacesize(si_t *sih, uint asidx); 223extern void si_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, uint32 *size); 224extern int si_corebist(si_t *sih); 225extern void si_core_reset(si_t *sih, uint32 bits, uint32 resetbits); 226extern void si_core_disable(si_t *sih, uint32 bits); 227extern uint32 si_clock_rate(uint32 pll_type, uint32 n, uint32 m); 228extern uint si_chip_hostif(si_t *sih); 229extern bool si_read_pmu_autopll(si_t *sih); 230extern uint32 si_clock(si_t *sih); 231extern uint32 si_alp_clock(si_t *sih); 232extern uint32 si_ilp_clock(si_t *sih); 233extern void si_pci_setup(si_t *sih, uint coremask); 234extern void si_pcmcia_init(si_t *sih); 235extern void si_setint(si_t *sih, int siflag); 236extern bool si_backplane64(si_t *sih); 237extern void si_register_intr_callback(si_t *sih, void *intrsoff_fn, void *intrsrestore_fn, 238 void *intrsenabled_fn, void *intr_arg); 239extern void si_deregister_intr_callback(si_t *sih); 240extern void si_clkctl_init(si_t *sih); 241extern uint16 si_clkctl_fast_pwrup_delay(si_t *sih); 242extern bool si_clkctl_cc(si_t *sih, uint mode); 243extern int si_clkctl_xtal(si_t *sih, uint what, bool on); 244extern uint32 si_gpiotimerval(si_t *sih, uint32 mask, uint32 val); 245extern void si_btcgpiowar(si_t *sih); 246extern bool si_deviceremoved(si_t *sih); 247extern uint32 si_socram_size(si_t *sih); 248extern uint32 si_socdevram_size(si_t *sih); 249extern void si_socdevram(si_t *sih, bool set, uint8 *ennable, uint8 *protect, uint8 *remap); 250extern bool si_socdevram_pkg(si_t *sih); 251extern bool si_socdevram_remap_isenb(si_t *sih); 252extern uint32 si_socdevram_remap_size(si_t *sih); 253 254extern void si_watchdog(si_t *sih, uint ticks); 255extern void si_watchdog_ms(si_t *sih, uint32 ms); 256extern uint32 si_watchdog_msticks(void); 257extern void *si_gpiosetcore(si_t *sih); 258extern uint32 si_gpiocontrol(si_t *sih, uint32 mask, uint32 val, uint8 priority); 259extern uint32 si_gpioouten(si_t *sih, uint32 mask, uint32 val, uint8 priority); 260extern uint32 si_gpioout(si_t *sih, uint32 mask, uint32 val, uint8 priority); 261extern uint32 si_gpioin(si_t *sih); 262extern uint32 si_gpiointpolarity(si_t *sih, uint32 mask, uint32 val, uint8 priority); 263extern uint32 si_gpiointmask(si_t *sih, uint32 mask, uint32 val, uint8 priority); 264extern uint32 si_gpioled(si_t *sih, uint32 mask, uint32 val); 265extern uint32 si_gpioreserve(si_t *sih, uint32 gpio_num, uint8 priority); 266extern uint32 si_gpiorelease(si_t *sih, uint32 gpio_num, uint8 priority); 267extern uint32 si_gpiopull(si_t *sih, bool updown, uint32 mask, uint32 val); 268extern uint32 si_gpioevent(si_t *sih, uint regtype, uint32 mask, uint32 val); 269extern uint32 si_gpio_int_enable(si_t *sih, bool enable); 270 271/* GPIO event handlers */ 272extern void *si_gpio_handler_register(si_t *sih, uint32 e, bool lev, gpio_handler_t cb, void *arg); 273extern void si_gpio_handler_unregister(si_t *sih, void* gpioh); 274extern void si_gpio_handler_process(si_t *sih); 275 276/* Wake-on-wireless-LAN (WOWL) */ 277extern bool si_pci_pmecap(si_t *sih); 278struct osl_info; 279extern bool si_pci_fastpmecap(struct osl_info *osh); 280extern bool si_pci_pmestat(si_t *sih); 281extern void si_pci_pmeclr(si_t *sih); 282extern void si_pci_pmeen(si_t *sih); 283extern void si_pci_pmestatclr(si_t *sih); 284extern uint si_pcie_readreg(void *sih, uint addrtype, uint offset); 285extern uint si_pcie_writereg(void *sih, uint addrtype, uint offset, uint val); 286 287 288 289extern uint16 si_d11_devid(si_t *sih); 290extern int si_corepciid(si_t *sih, uint func, uint16 *pcivendor, uint16 *pcidevice, 291 uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif, uint8 *pciheader); 292 293#if defined(BCMECICOEX) 294extern bool si_eci(si_t *sih); 295extern int si_eci_init(si_t *sih); 296extern void si_eci_notify_bt(si_t *sih, uint32 mask, uint32 val, bool interrupt); 297extern bool si_seci(si_t *sih); 298extern void* si_seci_init(si_t *sih, uint8 seci_mode); 299extern void* si_gci_init(si_t *sih); 300extern void si_seci_down(si_t *sih); 301extern void si_seci_upd(si_t *sih, bool enable); 302extern bool si_gci(si_t *sih); 303#else 304#define si_eci(sih) 0 305static INLINE void * si_eci_init(si_t *sih) {return NULL;} 306#define si_eci_notify_bt(sih, type, val) (0) 307#define si_seci(sih) 0 308#define si_seci_upd(sih, a) do {} while (0) 309static INLINE void * si_seci_init(si_t *sih, uint8 use_seci) {return NULL;} 310static INLINE void * si_gci_init(si_t *sih) {return NULL;} 311#define si_seci_down(sih) do {} while (0) 312#define si_gci(sih) 0 313#endif /* BCMECICOEX */ 314 315/* OTP status */ 316extern bool si_is_otp_disabled(si_t *sih); 317extern bool si_is_otp_powered(si_t *sih); 318extern void si_otp_power(si_t *sih, bool on); 319 320/* SPROM availability */ 321extern bool si_is_sprom_available(si_t *sih); 322extern bool si_is_sprom_enabled(si_t *sih); 323extern void si_sprom_enable(si_t *sih, bool enable); 324#ifdef SI_SPROM_PROBE 325extern void si_sprom_init(si_t *sih); 326#endif /* SI_SPROM_PROBE */ 327 328/* OTP/SROM CIS stuff */ 329extern int si_cis_source(si_t *sih); 330#define CIS_DEFAULT 0 331#define CIS_SROM 1 332#define CIS_OTP 2 333 334/* Fab-id information */ 335#define DEFAULT_FAB 0x0 /* Original/first fab used for this chip */ 336#define CSM_FAB7 0x1 /* CSM Fab7 chip */ 337#define TSMC_FAB12 0x2 /* TSMC Fab12/Fab14 chip */ 338#define SMIC_FAB4 0x3 /* SMIC Fab4 chip */ 339extern int BCMINITFN(si_otp_fabid)(si_t *sih, uint16 *fabid, bool rw); 340 341/* 342 * Build device path. Path size must be >= SI_DEVPATH_BUFSZ. 343 * The returned path is NULL terminated and has trailing '/'. 344 * Return 0 on success, nonzero otherwise. 345 */ 346extern int si_devpath(si_t *sih, char *path, int size); 347/* Read variable with prepending the devpath to the name */ 348extern char *si_getdevpathvar(si_t *sih, const char *name); 349extern int si_getdevpathintvar(si_t *sih, const char *name); 350 351 352extern uint8 si_pcieclkreq(si_t *sih, uint32 mask, uint32 val); 353extern uint32 si_pcielcreg(si_t *sih, uint32 mask, uint32 val); 354extern uint8 si_pcieltrenable(si_t *sih, uint32 mask, uint32 val); 355extern uint8 si_pcieobffenable(si_t *sih, uint32 mask, uint32 val); 356extern uint32 si_pcieltr_reg(si_t *sih, uint32 reg, uint32 mask, uint32 val); 357extern uint32 si_pcieltrspacing_reg(si_t *sih, uint32 mask, uint32 val); 358extern uint32 si_pcieltrhysteresiscnt_reg(si_t *sih, uint32 mask, uint32 val); 359extern void si_pcie_set_error_injection(si_t *sih, uint32 mode); 360extern void si_pcie_set_L1substate(si_t *sih, uint32 substate); 361extern uint32 si_pcie_get_L1substate(si_t *sih); 362extern void si_war42780_clkreq(si_t *sih, bool clkreq); 363extern void si_pci_down(si_t *sih); 364extern void si_pci_up(si_t *sih); 365#ifdef WLC_HIGH_ONLY 366#define si_pci_sleep(sih) do { ASSERT(0); } while (0) 367#define si_pcie_war_ovr_update(sih, aspm) do { ASSERT(0); } while (0) 368#define si_pcie_power_save_enable(sih, up) do { ASSERT(0); } while (0) 369#else 370extern void si_pci_sleep(si_t *sih); 371extern void si_pcie_war_ovr_update(si_t *sih, uint8 aspm); 372extern void si_pcie_power_save_enable(si_t *sih, bool enable); 373#endif /* __CONFIG_USBAP__ */ 374extern void si_pcie_extendL1timer(si_t *sih, bool extend); 375extern int si_pci_fixcfg(si_t *sih); 376extern bool si_ldo_war(si_t *sih, uint devid); 377extern void si_chippkg_set(si_t *sih, uint); 378 379extern void si_chipcontrl_btshd0_4331(si_t *sih, bool on); 380extern void si_chipcontrl_restore(si_t *sih, uint32 val); 381extern uint32 si_chipcontrl_read(si_t *sih); 382extern void si_chipcontrl_epa4331(si_t *sih, bool on); 383extern void si_chipcontrl_epa4331_wowl(si_t *sih, bool enter_wowl); 384extern void si_chipcontrl_srom4360(si_t *sih, bool on); 385/* Enable BT-COEX & Ex-PA for 4313 */ 386extern void si_epa_4313war(si_t *sih); 387extern void si_btc_enable_chipcontrol(si_t *sih); 388/* BT/WL selection for 4313 bt combo >= P250 boards */ 389extern void si_btcombo_p250_4313_war(si_t *sih); 390extern void si_btcombo_43228_war(si_t *sih); 391extern void si_clk_pmu_htavail_set(si_t *sih, bool set_clear); 392extern void si_pmu_synth_pwrsw_4313_war(si_t *sih); 393extern uint si_pll_reset(si_t *sih); 394/* === debug routines === */ 395 396extern bool si_taclear(si_t *sih, bool details); 397 398#if defined(BCMDBG_DUMP) || defined(WLTEST) 399extern int si_dump_pcieinfo(si_t *sih, struct bcmstrbuf *b); 400#endif 401 402#if defined(BCMDBG_DUMP) 403struct bcmstrbuf; 404extern void si_dumpregs(si_t *sih, struct bcmstrbuf *b); 405#endif 406extern uint32 si_ccreg(si_t *sih, uint32 offset, uint32 mask, uint32 val); 407extern uint32 si_pciereg(si_t *sih, uint32 offset, uint32 mask, uint32 val, uint type); 408extern uint32 write_ccreg(si_t *sih, uint32 offset, uint32 mask, uint32 val); 409extern uint32 si_pcieserdesreg(si_t *sih, uint32 mdioslave, uint32 offset, uint32 mask, uint32 val); 410extern void si_pcie_set_request_size(si_t *sih, uint16 size); 411extern uint16 si_pcie_get_request_size(si_t *sih); 412extern void si_pcie_set_maxpayload_size(si_t *sih, uint16 size); 413extern uint16 si_pcie_get_maxpayload_size(si_t *sih); 414extern uint16 si_pcie_get_ssid(si_t *sih); 415extern uint32 si_pcie_get_bar0(si_t *sih); 416extern int si_pcie_configspace_cache(si_t *sih); 417extern int si_pcie_configspace_restore(si_t *sih); 418extern int si_pcie_configspace_get(si_t *sih, uint8 *buf, uint size); 419 420#ifndef DONGLEBUILD 421char *si_getnvramflvar(si_t *sih, const char *name); 422#endif /* DONGLEBUILD */ 423 424extern void BCMATTACHFN(si_muxenab)(si_t *sih, uint32 w); 425 426#if defined(WLOFFLD) 427extern uint32 si_tcm_size(si_t *sih); 428extern bool si_has_flops(si_t *sih); 429#endif 430 431extern uint32 si_gci_direct(si_t *sih, uint offset, uint32 mask, uint32 val); 432extern uint32 si_gci_indirect(si_t *sih, uint regidx, uint offset, uint32 mask, uint32 val); 433extern uint32 si_gci_output(si_t *sih, uint reg, uint32 mask, uint32 val); 434extern uint32 si_gci_input(si_t *sih, uint reg); 435extern uint32 si_gci_int_enable(si_t *sih, bool enable); 436extern void si_gci_reset(si_t *sih); 437extern void si_ercx_init(si_t *sih); 438extern void si_wci2_init(si_t *sih); 439extern void si_gci_seci_init(si_t *sih); 440extern void si_gci_set_functionsel(si_t *sih, uint32 pin, uint8 fnsel); 441extern uint8 si_gci_get_chipctrlreg_idx(uint32 pin, uint32 *regidx, uint32 *pos); 442extern uint32 si_gci_chipcontrol(si_t *sih, uint reg, uint32 mask, uint32 val); 443extern int si_set_sromctl(si_t *sih, uint32 value); 444extern uint32 si_get_sromctl(si_t *sih); 445 446extern uint16 si_cc_get_reg16(uint32 reg_offs); 447extern uint32 si_cc_get_reg32(uint32 reg_offs); 448extern uint32 si_cc_set_reg32(uint32 reg_offs, uint32 val); 449extern uint32 si_gci_preinit_upd_indirect(uint32 regidx, uint32 setval, uint32 mask); 450 451extern uint si_chipid_override(si_t *sih); 452extern uint si_chiprev_override(si_t *sih); 453 454#define CHIPCTRLREG1 0x1 455#define CHIPCTRLREG2 0x2 456#define CHIPCTRLREG3 0x3 457#define CHIPCTRLREG4 0x4 458#define CHIPCTRLREG5 0x5 459#define REGCTRLREG4 0x4 460#define MINRESMASKREG 0x618 461#define MAXRESMASKREG 0x61c 462#define CHIPCTRLADDR 0x650 463#define CHIPCTRLDATA 0x654 464#define RSRCTABLEADDR 0x620 465#define RSRCUPDWNTIME 0x628 466#define PMUREG_RESREQ_MASK 0x68c 467 468extern void si_update_masks(si_t *sih); 469 470extern void si_force_islanding(si_t *sih, bool enable); 471 472extern uint32 si_pmu_res_req_timer_clr(si_t *sih); 473extern void si_pmu_rfldo(si_t *sih, bool on); 474extern void si_survive_perst_war(si_t *sih, bool reset, uint32 sperst_mask, uint32 spert_val); 475extern void si_pcie_ltr_war(si_t *sih); 476 477/* Macro to enable clock gating changes in different cores */ 478#define MEM_CLK_GATE_BIT 5 479#define GCI_CLK_GATE_BIT 18 480 481#define USBAPP_CLK_BIT 0 482#define PCIE_CLK_BIT 3 483#define ARMCR4_DBG_CLK_BIT 4 484#define SAMPLE_SYNC_CLK_BIT 17 485#define PCIE_TL_CLK_BIT 18 486#define HQ_REQ_BIT 24 487#define PLL_DIV2_BIT_START 9 488#define PLL_DIV2_MASK (0x37 << PLL_DIV2_BIT_START) 489#define PLL_DIV2_DIS_OP (0x37 << PLL_DIV2_BIT_START) 490 491extern uint si_jtag_ureg_read(si_t *sih, uint num); 492extern void si_jtag_ureg_write(si_t *sih, uint num, uint data); 493extern uint si_bbpll_war(si_t *sih, uint state); 494 495#endif /* _siutils_h_ */ 496