1/* 2 * Generic Broadcom Home Networking Division (HND) DMA engine HW interface 3 * This supports the following chips: BCM42xx, 44xx, 47xx . 4 * 5 * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 14 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 16 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 17 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 * $Id: sbhnddma.h 401759 2013-05-13 16:08:08Z $ 20 */ 21 22#ifndef _sbhnddma_h_ 23#define _sbhnddma_h_ 24 25/* DMA structure: 26 * support two DMA engines: 32 bits address or 64 bit addressing 27 * basic DMA register set is per channel(transmit or receive) 28 * a pair of channels is defined for convenience 29 */ 30 31 32/* 32 bits addressing */ 33 34/* dma registers per channel(xmt or rcv) */ 35typedef volatile struct { 36 uint32 control; /* enable, et al */ 37 uint32 addr; /* descriptor ring base address (4K aligned) */ 38 uint32 ptr; /* last descriptor posted to chip */ 39 uint32 status; /* current active descriptor, et al */ 40} dma32regs_t; 41 42typedef volatile struct { 43 dma32regs_t xmt; /* dma tx channel */ 44 dma32regs_t rcv; /* dma rx channel */ 45} dma32regp_t; 46 47typedef volatile struct { /* diag access */ 48 uint32 fifoaddr; /* diag address */ 49 uint32 fifodatalow; /* low 32bits of data */ 50 uint32 fifodatahigh; /* high 32bits of data */ 51 uint32 pad; /* reserved */ 52} dma32diag_t; 53 54/* 55 * DMA Descriptor 56 * Descriptors are only read by the hardware, never written back. 57 */ 58typedef volatile struct { 59 uint32 ctrl; /* misc control bits & bufcount */ 60 uint32 addr; /* data buffer address */ 61} dma32dd_t; 62 63/* 64 * Each descriptor ring must be 4096byte aligned, and fit within a single 4096byte page. 65 */ 66#define D32RINGALIGN_BITS 12 67#define D32MAXRINGSZ (1 << D32RINGALIGN_BITS) 68#define D32RINGALIGN (1 << D32RINGALIGN_BITS) 69 70#define D32MAXDD (D32MAXRINGSZ / sizeof (dma32dd_t)) 71 72/* transmit channel control */ 73#define XC_XE ((uint32)1 << 0) /* transmit enable */ 74#define XC_SE ((uint32)1 << 1) /* transmit suspend request */ 75#define XC_LE ((uint32)1 << 2) /* loopback enable */ 76#define XC_FL ((uint32)1 << 4) /* flush request */ 77#define XC_MR_MASK 0x000000C0 /* Multiple outstanding reads */ 78#define XC_MR_SHIFT 6 79#define XC_PD ((uint32)1 << 11) /* parity check disable */ 80#define XC_AE ((uint32)3 << 16) /* address extension bits */ 81#define XC_AE_SHIFT 16 82#define XC_BL_MASK 0x001C0000 /* BurstLen bits */ 83#define XC_BL_SHIFT 18 84#define XC_PC_MASK 0x00E00000 /* Prefetch control */ 85#define XC_PC_SHIFT 21 86#define XC_PT_MASK 0x03000000 /* Prefetch threshold */ 87#define XC_PT_SHIFT 24 88 89/* Multiple outstanding reads */ 90#define DMA_MR_1 0 91#define DMA_MR_2 1 92/* 2, 3: reserved */ 93 94/* DMA Burst Length in bytes */ 95#define DMA_BL_16 0 96#define DMA_BL_32 1 97#define DMA_BL_64 2 98#define DMA_BL_128 3 99#define DMA_BL_256 4 100#define DMA_BL_512 5 101#define DMA_BL_1024 6 102 103/* Prefetch control */ 104#define DMA_PC_0 0 105#define DMA_PC_4 1 106#define DMA_PC_8 2 107#define DMA_PC_16 3 108/* others: reserved */ 109 110/* Prefetch threshold */ 111#define DMA_PT_1 0 112#define DMA_PT_2 1 113#define DMA_PT_4 2 114#define DMA_PT_8 3 115 116/* transmit descriptor table pointer */ 117#define XP_LD_MASK 0xfff /* last valid descriptor */ 118 119/* transmit channel status */ 120#define XS_CD_MASK 0x0fff /* current descriptor pointer */ 121#define XS_XS_MASK 0xf000 /* transmit state */ 122#define XS_XS_SHIFT 12 123#define XS_XS_DISABLED 0x0000 /* disabled */ 124#define XS_XS_ACTIVE 0x1000 /* active */ 125#define XS_XS_IDLE 0x2000 /* idle wait */ 126#define XS_XS_STOPPED 0x3000 /* stopped */ 127#define XS_XS_SUSP 0x4000 /* suspend pending */ 128#define XS_XE_MASK 0xf0000 /* transmit errors */ 129#define XS_XE_SHIFT 16 130#define XS_XE_NOERR 0x00000 /* no error */ 131#define XS_XE_DPE 0x10000 /* descriptor protocol error */ 132#define XS_XE_DFU 0x20000 /* data fifo underrun */ 133#define XS_XE_BEBR 0x30000 /* bus error on buffer read */ 134#define XS_XE_BEDA 0x40000 /* bus error on descriptor access */ 135#define XS_AD_MASK 0xfff00000 /* active descriptor */ 136#define XS_AD_SHIFT 20 137 138/* receive channel control */ 139#define RC_RE ((uint32)1 << 0) /* receive enable */ 140#define RC_RO_MASK 0xfe /* receive frame offset */ 141#define RC_RO_SHIFT 1 142#define RC_FM ((uint32)1 << 8) /* direct fifo receive (pio) mode */ 143#define RC_SH ((uint32)1 << 9) /* separate rx header descriptor enable */ 144#define RC_OC ((uint32)1 << 10) /* overflow continue */ 145#define RC_PD ((uint32)1 << 11) /* parity check disable */ 146#define RC_AE ((uint32)3 << 16) /* address extension bits */ 147#define RC_AE_SHIFT 16 148#define RC_BL_MASK 0x001C0000 /* BurstLen bits */ 149#define RC_BL_SHIFT 18 150#define RC_PC_MASK 0x00E00000 /* Prefetch control */ 151#define RC_PC_SHIFT 21 152#define RC_PT_MASK 0x03000000 /* Prefetch threshold */ 153#define RC_PT_SHIFT 24 154 155/* receive descriptor table pointer */ 156#define RP_LD_MASK 0xfff /* last valid descriptor */ 157 158/* receive channel status */ 159#define RS_CD_MASK 0x0fff /* current descriptor pointer */ 160#define RS_RS_MASK 0xf000 /* receive state */ 161#define RS_RS_SHIFT 12 162#define RS_RS_DISABLED 0x0000 /* disabled */ 163#define RS_RS_ACTIVE 0x1000 /* active */ 164#define RS_RS_IDLE 0x2000 /* idle wait */ 165#define RS_RS_STOPPED 0x3000 /* reserved */ 166#define RS_RE_MASK 0xf0000 /* receive errors */ 167#define RS_RE_SHIFT 16 168#define RS_RE_NOERR 0x00000 /* no error */ 169#define RS_RE_DPE 0x10000 /* descriptor protocol error */ 170#define RS_RE_DFO 0x20000 /* data fifo overflow */ 171#define RS_RE_BEBW 0x30000 /* bus error on buffer write */ 172#define RS_RE_BEDA 0x40000 /* bus error on descriptor access */ 173#define RS_AD_MASK 0xfff00000 /* active descriptor */ 174#define RS_AD_SHIFT 20 175 176/* fifoaddr */ 177#define FA_OFF_MASK 0xffff /* offset */ 178#define FA_SEL_MASK 0xf0000 /* select */ 179#define FA_SEL_SHIFT 16 180#define FA_SEL_XDD 0x00000 /* transmit dma data */ 181#define FA_SEL_XDP 0x10000 /* transmit dma pointers */ 182#define FA_SEL_RDD 0x40000 /* receive dma data */ 183#define FA_SEL_RDP 0x50000 /* receive dma pointers */ 184#define FA_SEL_XFD 0x80000 /* transmit fifo data */ 185#define FA_SEL_XFP 0x90000 /* transmit fifo pointers */ 186#define FA_SEL_RFD 0xc0000 /* receive fifo data */ 187#define FA_SEL_RFP 0xd0000 /* receive fifo pointers */ 188#define FA_SEL_RSD 0xe0000 /* receive frame status data */ 189#define FA_SEL_RSP 0xf0000 /* receive frame status pointers */ 190 191/* descriptor control flags */ 192#define CTRL_BC_MASK 0x00001fff /* buffer byte count, real data len must <= 4KB */ 193#define CTRL_AE ((uint32)3 << 16) /* address extension bits */ 194#define CTRL_AE_SHIFT 16 195#define CTRL_PARITY ((uint32)3 << 18) /* parity bit */ 196#define CTRL_EOT ((uint32)1 << 28) /* end of descriptor table */ 197#define CTRL_IOC ((uint32)1 << 29) /* interrupt on completion */ 198#define CTRL_EOF ((uint32)1 << 30) /* end of frame */ 199#define CTRL_SOF ((uint32)1 << 31) /* start of frame */ 200 201/* control flags in the range [27:20] are core-specific and not defined here */ 202#define CTRL_CORE_MASK 0x0ff00000 203 204/* 64 bits addressing */ 205 206/* dma registers per channel(xmt or rcv) */ 207typedef volatile struct { 208 uint32 control; /* enable, et al */ 209 uint32 ptr; /* last descriptor posted to chip */ 210 uint32 addrlow; /* descriptor ring base address low 32-bits (8K aligned) */ 211 uint32 addrhigh; /* descriptor ring base address bits 63:32 (8K aligned) */ 212 uint32 status0; /* current descriptor, xmt state */ 213 uint32 status1; /* active descriptor, xmt error */ 214} dma64regs_t; 215 216typedef volatile struct { 217 dma64regs_t tx; /* dma64 tx channel */ 218 dma64regs_t rx; /* dma64 rx channel */ 219} dma64regp_t; 220 221typedef volatile struct { /* diag access */ 222 uint32 fifoaddr; /* diag address */ 223 uint32 fifodatalow; /* low 32bits of data */ 224 uint32 fifodatahigh; /* high 32bits of data */ 225 uint32 pad; /* reserved */ 226} dma64diag_t; 227 228/* 229 * DMA Descriptor 230 * Descriptors are only read by the hardware, never written back. 231 */ 232typedef volatile struct { 233 uint32 ctrl1; /* misc control bits */ 234 uint32 ctrl2; /* buffer count and address extension */ 235 uint32 addrlow; /* memory address of the date buffer, bits 31:0 */ 236 uint32 addrhigh; /* memory address of the date buffer, bits 63:32 */ 237} dma64dd_t; 238 239/* 240 * Each descriptor ring must be 8kB aligned, and fit within a contiguous 8kB physical addresss. 241 */ 242#define D64RINGALIGN_BITS 13 243#define D64MAXRINGSZ (1 << D64RINGALIGN_BITS) 244#define D64RINGBOUNDARY (1 << D64RINGALIGN_BITS) 245 246#define D64MAXDD (D64MAXRINGSZ / sizeof (dma64dd_t)) 247 248/* for cores with large descriptor ring support, descriptor ring size can be up to 4096 */ 249#define D64MAXDD_LARGE ((1 << 16) / sizeof (dma64dd_t)) 250 251/* for cores with large descriptor ring support (4k descriptors), descriptor ring cannot cross 252 * 64K boundary 253 */ 254#define D64RINGBOUNDARY_LARGE (1 << 16) 255 256/* 257 * Default DMA Burstlen values for USBRev >= 12 and SDIORev >= 11. 258 * When this field contains the value N, the burst length is 2**(N + 4) bytes. 259 */ 260#define D64_DEF_USBBURSTLEN 2 261#define D64_DEF_SDIOBURSTLEN 1 262 263 264#ifndef D64_USBBURSTLEN 265#define D64_USBBURSTLEN DMA_BL_64 266#endif 267#ifndef D64_SDIOBURSTLEN 268#define D64_SDIOBURSTLEN DMA_BL_32 269#endif 270 271/* transmit channel control */ 272#define D64_XC_XE 0x00000001 /* transmit enable */ 273#define D64_XC_SE 0x00000002 /* transmit suspend request */ 274#define D64_XC_LE 0x00000004 /* loopback enable */ 275#define D64_XC_FL 0x00000010 /* flush request */ 276#define D64_XC_MR_MASK 0x000000C0 /* Multiple outstanding reads */ 277#define D64_XC_MR_SHIFT 6 278#define D64_XC_PD 0x00000800 /* parity check disable */ 279#define D64_XC_AE 0x00030000 /* address extension bits */ 280#define D64_XC_AE_SHIFT 16 281#define D64_XC_BL_MASK 0x001C0000 /* BurstLen bits */ 282#define D64_XC_BL_SHIFT 18 283#define D64_XC_PC_MASK 0x00E00000 /* Prefetch control */ 284#define D64_XC_PC_SHIFT 21 285#define D64_XC_PT_MASK 0x03000000 /* Prefetch threshold */ 286#define D64_XC_PT_SHIFT 24 287 288/* transmit descriptor table pointer */ 289#define D64_XP_LD_MASK 0x00001fff /* last valid descriptor */ 290 291/* transmit channel status */ 292#define D64_XS0_CD_MASK (di->d64_xs0_cd_mask) /* current descriptor pointer */ 293#define D64_XS0_XS_MASK 0xf0000000 /* transmit state */ 294#define D64_XS0_XS_SHIFT 28 295#define D64_XS0_XS_DISABLED 0x00000000 /* disabled */ 296#define D64_XS0_XS_ACTIVE 0x10000000 /* active */ 297#define D64_XS0_XS_IDLE 0x20000000 /* idle wait */ 298#define D64_XS0_XS_STOPPED 0x30000000 /* stopped */ 299#define D64_XS0_XS_SUSP 0x40000000 /* suspend pending */ 300 301#define D64_XS1_AD_MASK (di->d64_xs1_ad_mask) /* active descriptor */ 302#define D64_XS1_XE_MASK 0xf0000000 /* transmit errors */ 303#define D64_XS1_XE_SHIFT 28 304#define D64_XS1_XE_NOERR 0x00000000 /* no error */ 305#define D64_XS1_XE_DPE 0x10000000 /* descriptor protocol error */ 306#define D64_XS1_XE_DFU 0x20000000 /* data fifo underrun */ 307#define D64_XS1_XE_DTE 0x30000000 /* data transfer error */ 308#define D64_XS1_XE_DESRE 0x40000000 /* descriptor read error */ 309#define D64_XS1_XE_COREE 0x50000000 /* core error */ 310 311/* receive channel control */ 312#define D64_RC_RE 0x00000001 /* receive enable */ 313#define D64_RC_RO_MASK 0x000000fe /* receive frame offset */ 314#define D64_RC_RO_SHIFT 1 315#define D64_RC_FM 0x00000100 /* direct fifo receive (pio) mode */ 316#define D64_RC_SH 0x00000200 /* separate rx header descriptor enable */ 317#define D64_RC_OC 0x00000400 /* overflow continue */ 318#define D64_RC_PD 0x00000800 /* parity check disable */ 319#define D64_RC_GE 0x00004000 /* Glom enable */ 320#define D64_RC_AE 0x00030000 /* address extension bits */ 321#define D64_RC_AE_SHIFT 16 322#define D64_RC_BL_MASK 0x001C0000 /* BurstLen bits */ 323#define D64_RC_BL_SHIFT 18 324#define D64_RC_PC_MASK 0x00E00000 /* Prefetch control */ 325#define D64_RC_PC_SHIFT 21 326#define D64_RC_PT_MASK 0x03000000 /* Prefetch threshold */ 327#define D64_RC_PT_SHIFT 24 328 329/* flags for dma controller */ 330#define DMA_CTRL_PEN (1 << 0) /* partity enable */ 331#define DMA_CTRL_ROC (1 << 1) /* rx overflow continue */ 332#define DMA_CTRL_RXMULTI (1 << 2) /* allow rx scatter to multiple descriptors */ 333#define DMA_CTRL_UNFRAMED (1 << 3) /* Unframed Rx/Tx data */ 334#define DMA_CTRL_USB_BOUNDRY4KB_WAR (1 << 4) 335#define DMA_CTRL_DMA_AVOIDANCE_WAR (1 << 5) /* DMA avoidance WAR for 4331 */ 336 337/* receive descriptor table pointer */ 338#define D64_RP_LD_MASK 0x00001fff /* last valid descriptor */ 339 340/* receive channel status */ 341#define D64_RS0_CD_MASK (di->d64_rs0_cd_mask) /* current descriptor pointer */ 342#define D64_RS0_RS_MASK 0xf0000000 /* receive state */ 343#define D64_RS0_RS_SHIFT 28 344#define D64_RS0_RS_DISABLED 0x00000000 /* disabled */ 345#define D64_RS0_RS_ACTIVE 0x10000000 /* active */ 346#define D64_RS0_RS_IDLE 0x20000000 /* idle wait */ 347#define D64_RS0_RS_STOPPED 0x30000000 /* stopped */ 348#define D64_RS0_RS_SUSP 0x40000000 /* suspend pending */ 349 350#define D64_RS1_AD_MASK 0x0001ffff /* active descriptor */ 351#define D64_RS1_RE_MASK 0xf0000000 /* receive errors */ 352#define D64_RS1_RE_SHIFT 28 353#define D64_RS1_RE_NOERR 0x00000000 /* no error */ 354#define D64_RS1_RE_DPO 0x10000000 /* descriptor protocol error */ 355#define D64_RS1_RE_DFU 0x20000000 /* data fifo overflow */ 356#define D64_RS1_RE_DTE 0x30000000 /* data transfer error */ 357#define D64_RS1_RE_DESRE 0x40000000 /* descriptor read error */ 358#define D64_RS1_RE_COREE 0x50000000 /* core error */ 359 360/* fifoaddr */ 361#define D64_FA_OFF_MASK 0xffff /* offset */ 362#define D64_FA_SEL_MASK 0xf0000 /* select */ 363#define D64_FA_SEL_SHIFT 16 364#define D64_FA_SEL_XDD 0x00000 /* transmit dma data */ 365#define D64_FA_SEL_XDP 0x10000 /* transmit dma pointers */ 366#define D64_FA_SEL_RDD 0x40000 /* receive dma data */ 367#define D64_FA_SEL_RDP 0x50000 /* receive dma pointers */ 368#define D64_FA_SEL_XFD 0x80000 /* transmit fifo data */ 369#define D64_FA_SEL_XFP 0x90000 /* transmit fifo pointers */ 370#define D64_FA_SEL_RFD 0xc0000 /* receive fifo data */ 371#define D64_FA_SEL_RFP 0xd0000 /* receive fifo pointers */ 372#define D64_FA_SEL_RSD 0xe0000 /* receive frame status data */ 373#define D64_FA_SEL_RSP 0xf0000 /* receive frame status pointers */ 374 375/* descriptor control flags 1 */ 376#define D64_CTRL_COREFLAGS 0x0ff00000 /* core specific flags */ 377#define D64_CTRL1_EOT ((uint32)1 << 28) /* end of descriptor table */ 378#define D64_CTRL1_IOC ((uint32)1 << 29) /* interrupt on completion */ 379#define D64_CTRL1_EOF ((uint32)1 << 30) /* end of frame */ 380#define D64_CTRL1_SOF ((uint32)1 << 31) /* start of frame */ 381 382/* descriptor control flags 2 */ 383#define D64_CTRL2_BC_MASK 0x00007fff /* buffer byte count. real data len must <= 16KB */ 384#define D64_CTRL2_AE 0x00030000 /* address extension bits */ 385#define D64_CTRL2_AE_SHIFT 16 386#define D64_CTRL2_PARITY 0x00040000 /* parity bit */ 387 388/* control flags in the range [27:20] are core-specific and not defined here */ 389#define D64_CTRL_CORE_MASK 0x0ff00000 390 391#define D64_RX_FRM_STS_LEN 0x0000ffff /* frame length mask */ 392#define D64_RX_FRM_STS_OVFL 0x00800000 /* RxOverFlow */ 393#define D64_RX_FRM_STS_DSCRCNT 0x0f000000 /* no. of descriptors used - 1, d11corerev >= 22 */ 394#define D64_RX_FRM_STS_DATATYPE 0xf0000000 /* core-dependent data type */ 395 396/* receive frame status */ 397typedef volatile struct { 398 uint16 len; 399 uint16 flags; 400} dma_rxh_t; 401 402#endif /* _sbhnddma_h_ */ 403