1/* 2 * BCM43XX PCIE core hardware definitions. 3 * 4 * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved. 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 13 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 15 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 16 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * 18 * $Id: pcie_core.h 401759 2013-05-13 16:08:08Z $ 19 */ 20#ifndef _PCIE_CORE_H 21#define _PCIE_CORE_H 22 23/* cpp contortions to concatenate w/arg prescan */ 24#ifndef PAD 25#define _PADLINE(line) pad ## line 26#define _XSTR(line) _PADLINE(line) 27#define PAD _XSTR(__LINE__) 28#endif 29 30/* PCIE Enumeration space offsets */ 31#define PCIE_CORE_CONFIG_OFFSET 0x0 32#define PCIE_FUNC0_CONFIG_OFFSET 0x400 33#define PCIE_FUNC1_CONFIG_OFFSET 0x500 34#define PCIE_FUNC2_CONFIG_OFFSET 0x600 35#define PCIE_FUNC3_CONFIG_OFFSET 0x700 36#define PCIE_SPROM_SHADOW_OFFSET 0x800 37#define PCIE_SBCONFIG_OFFSET 0xE00 38 39/* PCIE Bar0 Address Mapping. Each function maps 16KB config space */ 40#define PCIE_DEV_BAR0_SIZE 0x4000 41#define PCIE_BAR0_WINMAPCORE_OFFSET 0x0 42#define PCIE_BAR0_EXTSPROM_OFFSET 0x1000 43#define PCIE_BAR0_PCIECORE_OFFSET 0x2000 44#define PCIE_BAR0_CCCOREREG_OFFSET 0x3000 45 46/* different register spaces to access thr'u pcie indirect access */ 47#define PCIE_CONFIGREGS 1 /* Access to config space */ 48#define PCIE_PCIEREGS 2 /* Access to pcie registers */ 49 50/* SB side: PCIE core and host control registers */ 51typedef struct sbpcieregs { 52 uint32 control; /* host mode only */ 53 uint32 iocstatus; /* PCIE2: iostatus */ 54 uint32 PAD[1]; 55 uint32 biststatus; /* bist Status: 0x00C */ 56 uint32 gpiosel; /* PCIE gpio sel: 0x010 */ 57 uint32 gpioouten; /* PCIE gpio outen: 0x14 */ 58 uint32 PAD[2]; 59 uint32 intstatus; /* Interrupt status: 0x20 */ 60 uint32 intmask; /* Interrupt mask: 0x24 */ 61 uint32 sbtopcimailbox; /* sb to pcie mailbox: 0x028 */ 62 uint32 obffcontrol; /* PCIE2: 0x2C */ 63 uint32 obffintstatus; /* PCIE2: 0x30 */ 64 uint32 obffdatastatus; /* PCIE2: 0x34 */ 65 uint32 PAD[2]; 66 uint32 errlog; /* PCIE2: 0x40 */ 67 uint32 errlogaddr; /* PCIE2: 0x44 */ 68 uint32 mailboxint; /* PCIE2: 0x48 */ 69 uint32 mailboxintmsk; /* PCIE2: 0x4c */ 70 uint32 ltrspacing; /* PCIE2: 0x50 */ 71 uint32 ltrhysteresiscnt; /* PCIE2: 0x54 */ 72 uint32 PAD[42]; 73 74 uint32 sbtopcie0; /* sb to pcie translation 0: 0x100 */ 75 uint32 sbtopcie1; /* sb to pcie translation 1: 0x104 */ 76 uint32 sbtopcie2; /* sb to pcie translation 2: 0x108 */ 77 uint32 PAD[5]; 78 79 /* pcie core supports in direct access to config space */ 80 uint32 configaddr; /* pcie config space access: Address field: 0x120 */ 81 uint32 configdata; /* pcie config space access: Data field: 0x124 */ 82 union { 83 struct { 84 /* mdio access to serdes */ 85 uint32 mdiocontrol; /* controls the mdio access: 0x128 */ 86 uint32 mdiodata; /* Data to the mdio access: 0x12c */ 87 /* pcie protocol phy/dllp/tlp register indirect access mechanism */ 88 uint32 pcieindaddr; /* indirect access to the internal register: 0x130 */ 89 uint32 pcieinddata; /* Data to/from the internal regsiter: 0x134 */ 90 uint32 clkreqenctrl; /* >= rev 6, Clkreq rdma control : 0x138 */ 91 } pcie1; 92 struct { 93 /* mdio access to serdes */ 94 uint32 mdiocontrol; /* controls the mdio access: 0x128 */ 95 uint32 mdiowrdata; /* write data to mdio 0x12C */ 96 uint32 mdiorddata; /* read data to mdio 0x130 */ 97 uint32 PAD[2]; 98 } pcie2; 99 } u; 100 uint32 PAD[177]; 101 uint32 pciecfg[4][64]; /* 0x400 - 0x7FF, PCIE Cfg Space */ 102 uint16 sprom[64]; /* SPROM shadow Area */ 103} sbpcieregs_t; 104 105/* PCI control */ 106#define PCIE_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */ 107#define PCIE_RST 0x02 /* Value driven out to pin */ 108#define PCIE_SPERST 0x04 /* SurvivePeRst */ 109#define PCIE_DISSPROMLD 0x200 /* DisableSpromLoadOnPerst */ 110 111#define PCIE_CFGADDR 0x120 /* offsetof(configaddr) */ 112#define PCIE_CFGDATA 0x124 /* offsetof(configdata) */ 113 114/* Interrupt status/mask */ 115#define PCIE_INTA 0x01 /* PCIE INTA message is received */ 116#define PCIE_INTB 0x02 /* PCIE INTB message is received */ 117#define PCIE_INTFATAL 0x04 /* PCIE INTFATAL message is received */ 118#define PCIE_INTNFATAL 0x08 /* PCIE INTNONFATAL message is received */ 119#define PCIE_INTCORR 0x10 /* PCIE INTCORR message is received */ 120#define PCIE_INTPME 0x20 /* PCIE INTPME message is received */ 121#define PCIE_PERST 0x40 /* PCIE Reset Interrupt */ 122 123#define PCIE_INT_MB_FN0_0 0x0100 /* PCIE to SB Mailbox int Fn0.0 is received */ 124#define PCIE_INT_MB_FN0_1 0x0200 /* PCIE to SB Mailbox int Fn0.1 is received */ 125#define PCIE_INT_MB_FN1_0 0x0400 /* PCIE to SB Mailbox int Fn1.0 is received */ 126#define PCIE_INT_MB_FN1_1 0x0800 /* PCIE to SB Mailbox int Fn1.1 is received */ 127#define PCIE_INT_MB_FN2_0 0x1000 /* PCIE to SB Mailbox int Fn2.0 is received */ 128#define PCIE_INT_MB_FN2_1 0x2000 /* PCIE to SB Mailbox int Fn2.1 is received */ 129#define PCIE_INT_MB_FN3_0 0x4000 /* PCIE to SB Mailbox int Fn3.0 is received */ 130#define PCIE_INT_MB_FN3_1 0x8000 /* PCIE to SB Mailbox int Fn3.1 is received */ 131 132/* PCIE MailboxInt/MailboxIntMask register */ 133#define PCIE_MB_TOSB_FN0_0 0x0001 /* write to assert PCIEtoSB Mailbox interrupt */ 134#define PCIE_MB_TOSB_FN0_1 0x0002 135#define PCIE_MB_TOSB_FN1_0 0x0004 136#define PCIE_MB_TOSB_FN1_1 0x0008 137#define PCIE_MB_TOSB_FN2_0 0x0010 138#define PCIE_MB_TOSB_FN2_1 0x0020 139#define PCIE_MB_TOSB_FN3_0 0x0040 140#define PCIE_MB_TOSB_FN3_1 0x0080 141#define PCIE_MB_TOPCIE_FN0_0 0x0100 /* int status/mask for SBtoPCIE Mailbox interrupts */ 142#define PCIE_MB_TOPCIE_FN0_1 0x0200 143#define PCIE_MB_TOPCIE_FN1_0 0x0400 144#define PCIE_MB_TOPCIE_FN1_1 0x0800 145#define PCIE_MB_TOPCIE_FN2_0 0x1000 146#define PCIE_MB_TOPCIE_FN2_1 0x2000 147#define PCIE_MB_TOPCIE_FN3_0 0x4000 148#define PCIE_MB_TOPCIE_FN3_1 0x8000 149 150/* SB to PCIE translation masks */ 151#define SBTOPCIE0_MASK 0xfc000000 152#define SBTOPCIE1_MASK 0xfc000000 153#define SBTOPCIE2_MASK 0xc0000000 154 155/* Access type bits (0:1) */ 156#define SBTOPCIE_MEM 0 157#define SBTOPCIE_IO 1 158#define SBTOPCIE_CFG0 2 159#define SBTOPCIE_CFG1 3 160 161/* Prefetch enable bit 2 */ 162#define SBTOPCIE_PF 4 163 164/* Write Burst enable for memory write bit 3 */ 165#define SBTOPCIE_WR_BURST 8 166 167/* config access */ 168#define CONFIGADDR_FUNC_MASK 0x7000 169#define CONFIGADDR_FUNC_SHF 12 170#define CONFIGADDR_REG_MASK 0x0FFF 171#define CONFIGADDR_REG_SHF 0 172 173#define PCIE_CONFIG_INDADDR(f, r) ((((f) & CONFIGADDR_FUNC_MASK) << CONFIGADDR_FUNC_SHF) | \ 174 (((r) & CONFIGADDR_REG_MASK) << CONFIGADDR_REG_SHF)) 175 176/* PCIE protocol regs Indirect Address */ 177#define PCIEADDR_PROT_MASK 0x300 178#define PCIEADDR_PROT_SHF 8 179#define PCIEADDR_PL_TLP 0 180#define PCIEADDR_PL_DLLP 1 181#define PCIEADDR_PL_PLP 2 182 183/* PCIE protocol PHY diagnostic registers */ 184#define PCIE_PLP_MODEREG 0x200 /* Mode */ 185#define PCIE_PLP_STATUSREG 0x204 /* Status */ 186#define PCIE_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */ 187#define PCIE_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */ 188#define PCIE_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */ 189#define PCIE_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */ 190#define PCIE_PLP_ATTNREG 0x218 /* Attention */ 191#define PCIE_PLP_ATTNMASKREG 0x21C /* Attention Mask */ 192#define PCIE_PLP_RXERRCTR 0x220 /* Rx Error */ 193#define PCIE_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */ 194#define PCIE_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */ 195#define PCIE_PLP_TESTCTRLREG 0x22C /* Test Control reg */ 196#define PCIE_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */ 197#define PCIE_PLP_TIMINGOVRDREG 0x234 /* Timing param override */ 198#define PCIE_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */ 199#define PCIE_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */ 200 201/* PCIE protocol DLLP diagnostic registers */ 202#define PCIE_DLLP_LCREG 0x100 /* Link Control */ 203#define PCIE_DLLP_LSREG 0x104 /* Link Status */ 204#define PCIE_DLLP_LAREG 0x108 /* Link Attention */ 205#define PCIE_DLLP_LAMASKREG 0x10C /* Link Attention Mask */ 206#define PCIE_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */ 207#define PCIE_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */ 208#define PCIE_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */ 209#define PCIE_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */ 210#define PCIE_DLLP_LRREG 0x120 /* Link Replay */ 211#define PCIE_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */ 212#define PCIE_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */ 213#define PCIE_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */ 214#define PCIE_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */ 215#define PCIE_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */ 216#define PCIE_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */ 217#define PCIE_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */ 218#define PCIE_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */ 219#define PCIE_DLLP_ERRCTRREG 0x144 /* Error Counter */ 220#define PCIE_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */ 221#define PCIE_DLLP_TESTREG 0x14C /* Test */ 222#define PCIE_DLLP_PKTBIST 0x150 /* Packet BIST */ 223#define PCIE_DLLP_PCIE11 0x154 /* DLLP PCIE 1.1 reg */ 224 225#define PCIE_DLLP_LSREG_LINKUP (1 << 16) 226 227/* PCIE protocol TLP diagnostic registers */ 228#define PCIE_TLP_CONFIGREG 0x000 /* Configuration */ 229#define PCIE_TLP_WORKAROUNDSREG 0x004 /* TLP Workarounds */ 230#define PCIE_TLP_WRDMAUPPER 0x010 /* Write DMA Upper Address */ 231#define PCIE_TLP_WRDMALOWER 0x014 /* Write DMA Lower Address */ 232#define PCIE_TLP_WRDMAREQ_LBEREG 0x018 /* Write DMA Len/ByteEn Req */ 233#define PCIE_TLP_RDDMAUPPER 0x01C /* Read DMA Upper Address */ 234#define PCIE_TLP_RDDMALOWER 0x020 /* Read DMA Lower Address */ 235#define PCIE_TLP_RDDMALENREG 0x024 /* Read DMA Len Req */ 236#define PCIE_TLP_MSIDMAUPPER 0x028 /* MSI DMA Upper Address */ 237#define PCIE_TLP_MSIDMALOWER 0x02C /* MSI DMA Lower Address */ 238#define PCIE_TLP_MSIDMALENREG 0x030 /* MSI DMA Len Req */ 239#define PCIE_TLP_SLVREQLENREG 0x034 /* Slave Request Len */ 240#define PCIE_TLP_FCINPUTSREQ 0x038 /* Flow Control Inputs */ 241#define PCIE_TLP_TXSMGRSREQ 0x03C /* Tx StateMachine and Gated Req */ 242#define PCIE_TLP_ADRACKCNTARBLEN 0x040 /* Address Ack XferCnt and ARB Len */ 243#define PCIE_TLP_DMACPLHDR0 0x044 /* DMA Completion Hdr 0 */ 244#define PCIE_TLP_DMACPLHDR1 0x048 /* DMA Completion Hdr 1 */ 245#define PCIE_TLP_DMACPLHDR2 0x04C /* DMA Completion Hdr 2 */ 246#define PCIE_TLP_DMACPLMISC0 0x050 /* DMA Completion Misc0 */ 247#define PCIE_TLP_DMACPLMISC1 0x054 /* DMA Completion Misc1 */ 248#define PCIE_TLP_DMACPLMISC2 0x058 /* DMA Completion Misc2 */ 249#define PCIE_TLP_SPTCTRLLEN 0x05C /* Split Controller Req len */ 250#define PCIE_TLP_SPTCTRLMSIC0 0x060 /* Split Controller Misc 0 */ 251#define PCIE_TLP_SPTCTRLMSIC1 0x064 /* Split Controller Misc 1 */ 252#define PCIE_TLP_BUSDEVFUNC 0x068 /* Bus/Device/Func */ 253#define PCIE_TLP_RESETCTR 0x06C /* Reset Counter */ 254#define PCIE_TLP_RTRYBUF 0x070 /* Retry Buffer value */ 255#define PCIE_TLP_TGTDEBUG1 0x074 /* Target Debug Reg1 */ 256#define PCIE_TLP_TGTDEBUG2 0x078 /* Target Debug Reg2 */ 257#define PCIE_TLP_TGTDEBUG3 0x07C /* Target Debug Reg3 */ 258#define PCIE_TLP_TGTDEBUG4 0x080 /* Target Debug Reg4 */ 259 260/* MDIO control */ 261#define MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */ 262#define MDIOCTL_DIVISOR_VAL 0x2 263#define MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */ 264#define MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */ 265 266/* MDIO Data */ 267#define MDIODATA_MASK 0x0000ffff /* data 2 bytes */ 268#define MDIODATA_TA 0x00020000 /* Turnaround */ 269#define MDIODATA_REGADDR_SHF_OLD 18 /* Regaddr shift (rev < 10) */ 270#define MDIODATA_REGADDR_MASK_OLD 0x003c0000 /* Regaddr Mask (rev < 10) */ 271#define MDIODATA_DEVADDR_SHF_OLD 22 /* Physmedia devaddr shift (rev < 10) */ 272#define MDIODATA_DEVADDR_MASK_OLD 0x0fc00000 /* Physmedia devaddr Mask (rev < 10) */ 273#define MDIODATA_REGADDR_SHF 18 /* Regaddr shift */ 274#define MDIODATA_REGADDR_MASK 0x007c0000 /* Regaddr Mask */ 275#define MDIODATA_DEVADDR_SHF 23 /* Physmedia devaddr shift */ 276#define MDIODATA_DEVADDR_MASK 0x0f800000 /* Physmedia devaddr Mask */ 277#define MDIODATA_WRITE 0x10000000 /* write Transaction */ 278#define MDIODATA_READ 0x20000000 /* Read Transaction */ 279#define MDIODATA_START 0x40000000 /* start of Transaction */ 280 281#define MDIODATA_DEV_ADDR 0x0 /* dev address for serdes */ 282#define MDIODATA_BLK_ADDR 0x1F /* blk address for serdes */ 283 284/* MDIO control/wrData/rdData register defines for PCIE Gen 2 */ 285#define MDIOCTL2_DIVISOR_MASK 0x7f /* clock to be used on MDIO */ 286#define MDIOCTL2_DIVISOR_VAL 0x2 287#define MDIOCTL2_REGADDR_SHF 8 /* Regaddr shift */ 288#define MDIOCTL2_REGADDR_MASK 0x00FFFF00 /* Regaddr Mask */ 289#define MDIOCTL2_DEVADDR_SHF 24 /* Physmedia devaddr shift */ 290#define MDIOCTL2_DEVADDR_MASK 0x0f000000 /* Physmedia devaddr Mask */ 291#define MDIOCTL2_SLAVE_BYPASS 0x10000000 /* IP slave bypass */ 292#define MDIOCTL2_READ 0x20000000 /* IP slave bypass */ 293 294#define MDIODATA2_DONE 0x80000000 /* rd/wr transaction done */ 295#define MDIODATA2_MASK 0x7FFFFFFF /* rd/wr transaction data */ 296#define MDIODATA2_DEVADDR_SHF 4 /* Physmedia devaddr shift */ 297 298 299/* MDIO devices (SERDES modules) 300 * unlike old pcie cores (rev < 10), rev10 pcie serde organizes registers into a few blocks. 301 * two layers mapping (blockidx, register offset) is required 302 */ 303#define MDIO_DEV_IEEE0 0x000 304#define MDIO_DEV_IEEE1 0x001 305#define MDIO_DEV_BLK0 0x800 306#define MDIO_DEV_BLK1 0x801 307#define MDIO_DEV_BLK2 0x802 308#define MDIO_DEV_BLK3 0x803 309#define MDIO_DEV_BLK4 0x804 310#define MDIO_DEV_TXPLL 0x808 /* TXPLL register block idx */ 311#define MDIO_DEV_TXCTRL0 0x820 312#define MDIO_DEV_SERDESID 0x831 313#define MDIO_DEV_RXCTRL0 0x840 314 315 316/* XgxsBlk1_A Register Offsets */ 317#define BLK1_PWR_MGMT0 0x16 318#define BLK1_PWR_MGMT1 0x17 319#define BLK1_PWR_MGMT2 0x18 320#define BLK1_PWR_MGMT3 0x19 321#define BLK1_PWR_MGMT4 0x1A 322 323/* serdes regs (rev < 10) */ 324#define MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */ 325#define MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */ 326#define MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */ 327 /* SERDES RX registers */ 328#define SERDES_RX_CTRL 1 /* Rx cntrl */ 329#define SERDES_RX_TIMER1 2 /* Rx Timer1 */ 330#define SERDES_RX_CDR 6 /* CDR */ 331#define SERDES_RX_CDRBW 7 /* CDR BW */ 332 333 /* SERDES RX control register */ 334#define SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */ 335#define SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */ 336 337 /* SERDES PLL registers */ 338#define SERDES_PLL_CTRL 1 /* PLL control reg */ 339#define PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */ 340 341/* Power management threshold */ 342#define PCIE_L0THRESHOLDTIME_MASK 0xFF00 /* bits 0 - 7 */ 343#define PCIE_L1THRESHOLDTIME_MASK 0xFF00 /* bits 8 - 15 */ 344#define PCIE_L1THRESHOLDTIME_SHIFT 8 /* PCIE_L1THRESHOLDTIME_SHIFT */ 345#define PCIE_L1THRESHOLD_WARVAL 0x72 /* WAR value */ 346#define PCIE_ASPMTIMER_EXTEND 0x01000000 /* > rev7: enable extend ASPM timer */ 347 348/* SPROM offsets */ 349#define SRSH_ASPM_OFFSET 4 /* word 4 */ 350#define SRSH_ASPM_ENB 0x18 /* bit 3, 4 */ 351#define SRSH_ASPM_L1_ENB 0x10 /* bit 4 */ 352#define SRSH_ASPM_L0s_ENB 0x8 /* bit 3 */ 353#define SRSH_PCIE_MISC_CONFIG 5 /* word 5 */ 354#define SRSH_L23READY_EXIT_NOPERST 0x8000 /* bit 15 */ 355#define SRSH_CLKREQ_OFFSET_REV5 20 /* word 20 for srom rev <= 5 */ 356#define SRSH_CLKREQ_OFFSET_REV8 52 /* word 52 for srom rev 8 */ 357#define SRSH_CLKREQ_ENB 0x0800 /* bit 11 */ 358#define SRSH_BD_OFFSET 6 /* word 6 */ 359#define SRSH_AUTOINIT_OFFSET 18 /* auto initialization enable */ 360 361/* Linkcontrol reg offset in PCIE Cap */ 362#define PCIE_CAP_LINKCTRL_OFFSET 16 /* linkctrl offset in pcie cap */ 363#define PCIE_CAP_LCREG_ASPML0s 0x01 /* ASPM L0s in linkctrl */ 364#define PCIE_CAP_LCREG_ASPML1 0x02 /* ASPM L1 in linkctrl */ 365#define PCIE_CLKREQ_ENAB 0x100 /* CLKREQ Enab in linkctrl */ 366#define PCIE_LINKSPEED_MASK 0xF0000 /* bits 0 - 3 of high word */ 367#define PCIE_LINKSPEED_SHIFT 16 /* PCIE_LINKSPEED_SHIFT */ 368 369/* Devcontrol reg offset in PCIE Cap */ 370#define PCIE_CAP_DEVCTRL_OFFSET 8 /* devctrl offset in pcie cap */ 371#define PCIE_CAP_DEVCTRL_MRRS_MASK 0x7000 /* Max read request size mask */ 372#define PCIE_CAP_DEVCTRL_MRRS_SHIFT 12 /* Max read request size shift */ 373#define PCIE_CAP_DEVCTRL_MRRS_128B 0 /* 128 Byte */ 374#define PCIE_CAP_DEVCTRL_MRRS_256B 1 /* 256 Byte */ 375#define PCIE_CAP_DEVCTRL_MRRS_512B 2 /* 512 Byte */ 376#define PCIE_CAP_DEVCTRL_MRRS_1024B 3 /* 1024 Byte */ 377#define PCIE_CAP_DEVCTRL_MPS_MASK 0x00e0 /* Max payload size mask */ 378#define PCIE_CAP_DEVCTRL_MPS_SHIFT 5 /* Max payload size shift */ 379#define PCIE_CAP_DEVCTRL_MPS_128B 0 /* 128 Byte */ 380#define PCIE_CAP_DEVCTRL_MPS_256B 1 /* 256 Byte */ 381#define PCIE_CAP_DEVCTRL_MPS_512B 2 /* 512 Byte */ 382#define PCIE_CAP_DEVCTRL_MPS_1024B 3 /* 1024 Byte */ 383 384#define PCIE_ASPM_ENAB 3 /* ASPM L0s & L1 in linkctrl */ 385#define PCIE_ASPM_L1_ENAB 2 /* ASPM L0s & L1 in linkctrl */ 386#define PCIE_ASPM_L0s_ENAB 1 /* ASPM L0s & L1 in linkctrl */ 387#define PCIE_ASPM_DISAB 0 /* ASPM L0s & L1 in linkctrl */ 388 389#define PCIE_ASPM_L11_ENAB 8 /* ASPM L1.1 in PML1_sub_control2 */ 390#define PCIE_ASPM_L12_ENAB 4 /* ASPM L1.2 in PML1_sub_control2 */ 391 392/* Devcontrol2 reg offset in PCIE Cap */ 393#define PCIE_CAP_DEVCTRL2_OFFSET 0x28 /* devctrl2 offset in pcie cap */ 394#define PCIE_CAP_DEVCTRL2_LTR_ENAB_MASK 0x400 /* Latency Tolerance Reporting Enable */ 395#define PCIE_CAP_DEVCTRL2_OBFF_ENAB_SHIFT 13 /* Enable OBFF mechanism, select signaling method */ 396#define PCIE_CAP_DEVCTRL2_OBFF_ENAB_MASK 0x6000 /* Enable OBFF mechanism, select signaling method */ 397 398/* LTR registers in PCIE Cap */ 399#define PCIE_CAP_LTR0_REG_OFFSET 0x798 /* ltr0_reg offset in pcie cap */ 400#define PCIE_CAP_LTR1_REG_OFFSET 0x79C /* ltr1_reg offset in pcie cap */ 401#define PCIE_CAP_LTR2_REG_OFFSET 0x7A0 /* ltr2_reg offset in pcie cap */ 402#define PCIE_CAP_LTR0_REG 0 /* ltr0_reg */ 403#define PCIE_CAP_LTR1_REG 1 /* ltr1_reg */ 404#define PCIE_CAP_LTR2_REG 2 /* ltr2_reg */ 405 406/* Status reg PCIE_PLP_STATUSREG */ 407#define PCIE_PLP_POLARITYINV_STAT 0x10 408 409 410/* PCIE BRCM Vendor CAP REVID reg bits */ 411#define BRCMCAP_PCIEREV_CT_MASK 0xF00 412#define BRCMCAP_PCIEREV_CT_SHIFT 8 413#define BRCMCAP_PCIEREV_REVID_MASK 0xFF 414#define BRCMCAP_PCIEREV_REVID_SHIFT 0 415 416#define PCIE_REVREG_CT_PCIE1 0 417#define PCIE_REVREG_CT_PCIE2 1 418 419/* PCIE GEN2 specific defines */ 420/* PCIE BRCM Vendor Cap offsets w.r.t to vendor cap ptr */ 421#define PCIE2R0_BRCMCAP_REVID_OFFSET 4 422#define PCIE2R0_BRCMCAP_BAR0_WIN0_WRAP_OFFSET 8 423#define PCIE2R0_BRCMCAP_BAR0_WIN2_OFFSET 12 424#define PCIE2R0_BRCMCAP_BAR0_WIN2_WRAP_OFFSET 16 425#define PCIE2R0_BRCMCAP_BAR0_WIN_OFFSET 20 426#define PCIE2R0_BRCMCAP_BAR1_WIN_OFFSET 24 427#define PCIE2R0_BRCMCAP_SPROM_CTRL_OFFSET 28 428#define PCIE2R0_BRCMCAP_BAR2_WIN_OFFSET 32 429#define PCIE2R0_BRCMCAP_INTSTATUS_OFFSET 36 430#define PCIE2R0_BRCMCAP_INTMASK_OFFSET 40 431#define PCIE2R0_BRCMCAP_PCIE2SB_MB_OFFSET 44 432#define PCIE2R0_BRCMCAP_BPADDR_OFFSET 48 433#define PCIE2R0_BRCMCAP_BPDATA_OFFSET 52 434#define PCIE2R0_BRCMCAP_CLKCTLSTS_OFFSET 56 435 436/* definition of configuration space registers of PCIe gen2 437 * http://hwnbu-twiki.sj.broadcom.com/twiki/pub/Mwgroup/CurrentPcieGen2ProgramGuide/pcie_ep.htm 438 */ 439#define PCIECFGREG_PML1_SUB_CTRL1 0x248 440#define PCI_PM_L1_2_ENA_MASK 0x00000001 /* PCI-PM L1.2 Enabled */ 441#define PCI_PM_L1_1_ENA_MASK 0x00000002 /* PCI-PM L1.1 Enabled */ 442#define ASPM_L1_2_ENA_MASK 0x00000004 /* ASPM L1.2 Enabled */ 443#define ASPM_L1_1_ENA_MASK 0x00000008 /* ASPM L1.1 Enabled */ 444 445#define PCIECFGREG_PDL_CTRL1 0x1004 446#define PCIECFGREG_REG_PHY_CTL7 0x181c 447 448 449#endif /* _PCIE_CORE_H */ 450