1/* 2 * Broadcom SDIO/PCMCIA 3 * Software-specific definitions shared between device and host side 4 * 5 * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 14 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 16 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 17 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 * $Id: bcmsdpcm.h 314495 2012-02-12 07:56:39Z $ 20 */ 21 22#ifndef _bcmsdpcm_h_ 23#define _bcmsdpcm_h_ 24 25/* 26 * Software allocation of To SB Mailbox resources 27 */ 28 29/* intstatus bits */ 30#define I_SMB_NAK I_SMB_SW0 /* To SB Mailbox Frame NAK */ 31#define I_SMB_INT_ACK I_SMB_SW1 /* To SB Mailbox Host Interrupt ACK */ 32#define I_SMB_USE_OOB I_SMB_SW2 /* To SB Mailbox Use OOB Wakeup */ 33#define I_SMB_DEV_INT I_SMB_SW3 /* To SB Mailbox Miscellaneous Interrupt */ 34 35#define I_TOSBMAIL (I_SMB_NAK | I_SMB_INT_ACK | I_SMB_USE_OOB | I_SMB_DEV_INT) 36 37/* tosbmailbox bits corresponding to intstatus bits */ 38#define SMB_NAK (1 << 0) /* To SB Mailbox Frame NAK */ 39#define SMB_INT_ACK (1 << 1) /* To SB Mailbox Host Interrupt ACK */ 40#define SMB_USE_OOB (1 << 2) /* To SB Mailbox Use OOB Wakeup */ 41#define SMB_DEV_INT (1 << 3) /* To SB Mailbox Miscellaneous Interrupt */ 42#define SMB_MASK 0x0000000f /* To SB Mailbox Mask */ 43 44/* tosbmailboxdata */ 45#define SMB_DATA_VERSION_MASK 0x00ff0000 /* host protocol version (sent with F2 enable) */ 46#define SMB_DATA_VERSION_SHIFT 16 /* host protocol version (sent with F2 enable) */ 47 48/* 49 * Software allocation of To Host Mailbox resources 50 */ 51 52/* intstatus bits */ 53#define I_HMB_FC_STATE I_HMB_SW0 /* To Host Mailbox Flow Control State */ 54#define I_HMB_FC_CHANGE I_HMB_SW1 /* To Host Mailbox Flow Control State Changed */ 55#define I_HMB_FRAME_IND I_HMB_SW2 /* To Host Mailbox Frame Indication */ 56#define I_HMB_HOST_INT I_HMB_SW3 /* To Host Mailbox Miscellaneous Interrupt */ 57 58#define I_TOHOSTMAIL (I_HMB_FC_CHANGE | I_HMB_FRAME_IND | I_HMB_HOST_INT) 59 60/* tohostmailbox bits corresponding to intstatus bits */ 61#define HMB_FC_ON (1 << 0) /* To Host Mailbox Flow Control State */ 62#define HMB_FC_CHANGE (1 << 1) /* To Host Mailbox Flow Control State Changed */ 63#define HMB_FRAME_IND (1 << 2) /* To Host Mailbox Frame Indication */ 64#define HMB_HOST_INT (1 << 3) /* To Host Mailbox Miscellaneous Interrupt */ 65#define HMB_MASK 0x0000000f /* To Host Mailbox Mask */ 66 67/* tohostmailboxdata */ 68#define HMB_DATA_NAKHANDLED 0x01 /* we're ready to retransmit NAK'd frame to host */ 69#define HMB_DATA_DEVREADY 0x02 /* we're ready to to talk to host after enable */ 70#define HMB_DATA_FC 0x04 /* per prio flowcontrol update flag to host */ 71#define HMB_DATA_FWREADY 0x08 /* firmware is ready for protocol activity */ 72#define HMB_DATA_FWHALT 0x10 /* firmware has halted operation */ 73 74#define HMB_DATA_FCDATA_MASK 0xff000000 /* per prio flowcontrol data */ 75#define HMB_DATA_FCDATA_SHIFT 24 /* per prio flowcontrol data */ 76 77#define HMB_DATA_VERSION_MASK 0x00ff0000 /* device protocol version (with devready) */ 78#define HMB_DATA_VERSION_SHIFT 16 /* device protocol version (with devready) */ 79 80/* 81 * Software-defined protocol header 82 */ 83 84/* Current protocol version */ 85#define SDPCM_PROT_VERSION 4 86 87/* SW frame header */ 88#define SDPCM_SEQUENCE_MASK 0x000000ff /* Sequence Number Mask */ 89#define SDPCM_PACKET_SEQUENCE(p) (((uint8 *)p)[0] & 0xff) /* p starts w/SW Header */ 90 91#define SDPCM_CHANNEL_MASK 0x00000f00 /* Channel Number Mask */ 92#define SDPCM_CHANNEL_SHIFT 8 /* Channel Number Shift */ 93#define SDPCM_PACKET_CHANNEL(p) (((uint8 *)p)[1] & 0x0f) /* p starts w/SW Header */ 94 95#define SDPCM_FLAGS_MASK 0x0000f000 /* Mask of flag bits */ 96#define SDPCM_FLAGS_SHIFT 12 /* Flag bits shift */ 97#define SDPCM_PACKET_FLAGS(p) ((((uint8 *)p)[1] & 0xf0) >> 4) /* p starts w/SW Header */ 98 99/* Next Read Len: lookahead length of next frame, in 16-byte units (rounded up) */ 100#define SDPCM_NEXTLEN_MASK 0x00ff0000 /* Next Read Len Mask */ 101#define SDPCM_NEXTLEN_SHIFT 16 /* Next Read Len Shift */ 102#define SDPCM_NEXTLEN_VALUE(p) ((((uint8 *)p)[2] & 0xff) << 4) /* p starts w/SW Header */ 103#define SDPCM_NEXTLEN_OFFSET 2 104 105/* Data Offset from SOF (HW Tag, SW Tag, Pad) */ 106#define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */ 107#define SDPCM_DOFFSET_VALUE(p) (((uint8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff) 108#define SDPCM_DOFFSET_MASK 0xff000000 109#define SDPCM_DOFFSET_SHIFT 24 110 111#define SDPCM_FCMASK_OFFSET 4 /* Flow control */ 112#define SDPCM_FCMASK_VALUE(p) (((uint8 *)p)[SDPCM_FCMASK_OFFSET ] & 0xff) 113#define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */ 114#define SDPCM_WINDOW_VALUE(p) (((uint8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff) 115#define SDPCM_VERSION_OFFSET 6 /* Version # */ 116#define SDPCM_VERSION_VALUE(p) (((uint8 *)p)[SDPCM_VERSION_OFFSET] & 0xff) 117#define SDPCM_UNUSED_OFFSET 7 /* Spare */ 118#define SDPCM_UNUSED_VALUE(p) (((uint8 *)p)[SDPCM_UNUSED_OFFSET] & 0xff) 119 120#define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */ 121 122/* logical channel numbers */ 123#define SDPCM_CONTROL_CHANNEL 0 /* Control Request/Response Channel Id */ 124#define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */ 125#define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */ 126#define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets (superframes) */ 127#define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */ 128#define SDPCM_MAX_CHANNEL 15 129 130#define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for eight-bit frame seq number */ 131 132#define SDPCM_FLAG_RESVD0 0x01 133#define SDPCM_FLAG_RESVD1 0x02 134#define SDPCM_FLAG_GSPI_TXENAB 0x04 135#define SDPCM_FLAG_GLOMDESC 0x08 /* Superframe descriptor mask */ 136 137/* For GLOM_CHANNEL frames, use a flag to indicate descriptor frame */ 138#define SDPCM_GLOMDESC_FLAG (SDPCM_FLAG_GLOMDESC << SDPCM_FLAGS_SHIFT) 139 140#define SDPCM_GLOMDESC(p) (((uint8 *)p)[1] & 0x80) 141 142/* For TEST_CHANNEL packets, define another 4-byte header */ 143#define SDPCM_TEST_HDRLEN 4 /* Generally: Cmd(1), Ext(1), Len(2); 144 * Semantics of Ext byte depend on command. 145 * Len is current or requested frame length, not 146 * including test header; sent little-endian. 147 */ 148#define SDPCM_TEST_DISCARD 0x01 /* Receiver discards. Ext is a pattern id. */ 149#define SDPCM_TEST_ECHOREQ 0x02 /* Echo request. Ext is a pattern id. */ 150#define SDPCM_TEST_ECHORSP 0x03 /* Echo response. Ext is a pattern id. */ 151#define SDPCM_TEST_BURST 0x04 /* Receiver to send a burst. Ext is a frame count */ 152#define SDPCM_TEST_SEND 0x05 /* Receiver sets send mode. Ext is boolean on/off */ 153 154/* Handy macro for filling in datagen packets with a pattern */ 155#define SDPCM_TEST_FILL(byteno, id) ((uint8)(id + byteno)) 156 157/* 158 * Software counters (first part matches hardware counters) 159 */ 160 161typedef volatile struct { 162 uint32 cmd52rd; /* Cmd52RdCount, SDIO: cmd52 reads */ 163 uint32 cmd52wr; /* Cmd52WrCount, SDIO: cmd52 writes */ 164 uint32 cmd53rd; /* Cmd53RdCount, SDIO: cmd53 reads */ 165 uint32 cmd53wr; /* Cmd53WrCount, SDIO: cmd53 writes */ 166 uint32 abort; /* AbortCount, SDIO: aborts */ 167 uint32 datacrcerror; /* DataCrcErrorCount, SDIO: frames w/CRC error */ 168 uint32 rdoutofsync; /* RdOutOfSyncCount, SDIO/PCMCIA: Rd Frm out of sync */ 169 uint32 wroutofsync; /* RdOutOfSyncCount, SDIO/PCMCIA: Wr Frm out of sync */ 170 uint32 writebusy; /* WriteBusyCount, SDIO: device asserted "busy" */ 171 uint32 readwait; /* ReadWaitCount, SDIO: no data ready for a read cmd */ 172 uint32 readterm; /* ReadTermCount, SDIO: read frame termination cmds */ 173 uint32 writeterm; /* WriteTermCount, SDIO: write frames termination cmds */ 174 uint32 rxdescuflo; /* receive descriptor underflows */ 175 uint32 rxfifooflo; /* receive fifo overflows */ 176 uint32 txfifouflo; /* transmit fifo underflows */ 177 uint32 runt; /* runt (too short) frames recv'd from bus */ 178 uint32 badlen; /* frame's rxh len does not match its hw tag len */ 179 uint32 badcksum; /* frame's hw tag chksum doesn't agree with len value */ 180 uint32 seqbreak; /* break in sequence # space from one rx frame to the next */ 181 uint32 rxfcrc; /* frame rx header indicates crc error */ 182 uint32 rxfwoos; /* frame rx header indicates write out of sync */ 183 uint32 rxfwft; /* frame rx header indicates write frame termination */ 184 uint32 rxfabort; /* frame rx header indicates frame aborted */ 185 uint32 woosint; /* write out of sync interrupt */ 186 uint32 roosint; /* read out of sync interrupt */ 187 uint32 rftermint; /* read frame terminate interrupt */ 188 uint32 wftermint; /* write frame terminate interrupt */ 189} sdpcmd_cnt_t; 190 191/* 192 * Register Access Macros 193 */ 194 195#define SDIODREV_IS(var, val) ((var) == (val)) 196#define SDIODREV_GE(var, val) ((var) >= (val)) 197#define SDIODREV_GT(var, val) ((var) > (val)) 198#define SDIODREV_LT(var, val) ((var) < (val)) 199#define SDIODREV_LE(var, val) ((var) <= (val)) 200 201#define SDIODDMAREG32(h, dir, chnl) \ 202 ((dir) == DMA_TX ? \ 203 (void *)(uintptr)&((h)->regs->dma.sdiod32.dma32regs[chnl].xmt) : \ 204 (void *)(uintptr)&((h)->regs->dma.sdiod32.dma32regs[chnl].rcv)) 205 206#define SDIODDMAREG64(h, dir, chnl) \ 207 ((dir) == DMA_TX ? \ 208 (void *)(uintptr)&((h)->regs->dma.sdiod64.dma64regs[chnl].xmt) : \ 209 (void *)(uintptr)&((h)->regs->dma.sdiod64.dma64regs[chnl].rcv)) 210 211#define SDIODDMAREG(h, dir, chnl) \ 212 (SDIODREV_LT((h)->corerev, 1) ? \ 213 SDIODDMAREG32((h), (dir), (chnl)) : \ 214 SDIODDMAREG64((h), (dir), (chnl))) 215 216#define PCMDDMAREG(h, dir, chnl) \ 217 ((dir) == DMA_TX ? \ 218 (void *)(uintptr)&((h)->regs->dma.pcm32.dmaregs.xmt) : \ 219 (void *)(uintptr)&((h)->regs->dma.pcm32.dmaregs.rcv)) 220 221#define SDPCMDMAREG(h, dir, chnl, coreid) \ 222 ((coreid) == SDIOD_CORE_ID ? \ 223 SDIODDMAREG(h, dir, chnl) : \ 224 PCMDDMAREG(h, dir, chnl)) 225 226#define SDIODFIFOREG(h, corerev) \ 227 (SDIODREV_LT((corerev), 1) ? \ 228 ((dma32diag_t *)(uintptr)&((h)->regs->dma.sdiod32.dmafifo)) : \ 229 ((dma32diag_t *)(uintptr)&((h)->regs->dma.sdiod64.dmafifo))) 230 231#define PCMDFIFOREG(h) \ 232 ((dma32diag_t *)(uintptr)&((h)->regs->dma.pcm32.dmafifo)) 233 234#define SDPCMFIFOREG(h, coreid, corerev) \ 235 ((coreid) == SDIOD_CORE_ID ? \ 236 SDIODFIFOREG(h, corerev) : \ 237 PCMDFIFOREG(h)) 238 239/* 240 * Shared structure between dongle and the host. 241 * The structure contains pointers to trap or assert information. 242 */ 243#define SDPCM_SHARED_VERSION 0x0001 244#define SDPCM_SHARED_VERSION_MASK 0x00FF 245#define SDPCM_SHARED_ASSERT_BUILT 0x0100 246#define SDPCM_SHARED_ASSERT 0x0200 247#define SDPCM_SHARED_TRAP 0x0400 248#define SDPCM_SHARED_IN_BRPT 0x0800 249#define SDPCM_SHARED_SET_BRPT 0x1000 250#define SDPCM_SHARED_PENDING_BRPT 0x2000 251 252typedef struct { 253 uint32 flags; 254 uint32 trap_addr; 255 uint32 assert_exp_addr; 256 uint32 assert_file_addr; 257 uint32 assert_line; 258 uint32 console_addr; /* Address of hndrte_cons_t */ 259 uint32 msgtrace_addr; 260 uint32 fwid; 261} sdpcm_shared_t; 262 263extern sdpcm_shared_t sdpcm_shared; 264 265/* Function can be used to notify host of FW halt */ 266extern void sdpcmd_fwhalt(void); 267 268#endif /* _bcmsdpcm_h_ */ 269