1/* 2 * Hardware-specific definitions for 3 * Broadcom BCM47XX 10/100 Mbps Ethernet cores. 4 * 5 * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 14 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 16 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 17 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * $Id: bcmenet47xx.h 376344 2012-12-24 21:10:09Z $ 19 */ 20 21#ifndef _bcmenet_47xx_h_ 22#define _bcmenet_47xx_h_ 23 24#include <bcmenetmib.h> 25#include <bcmenetrxh.h> 26#include <bcmenetphy.h> 27 28#define BCMENET_NFILTERS 64 /* # ethernet address filter entries */ 29#define BCMENET_MCHASHBASE 0x200 /* multicast hash filter base address */ 30#define BCMENET_MCHASHSIZE 256 /* multicast hash filter size in bytes */ 31#define BCMENET_MAX_DMA 4096 /* chip has 12 bits of DMA addressing */ 32 33/* power management event wakeup pattern constants */ 34#define BCMENET_NPMP 4 /* chip supports 4 wakeup patterns */ 35#define BCMENET_PMPBASE 0x400 /* wakeup pattern base address */ 36#define BCMENET_PMPSIZE 0x80 /* 128bytes each pattern */ 37#define BCMENET_PMMBASE 0x600 /* wakeup mask base address */ 38#define BCMENET_PMMSIZE 0x10 /* 128bits each mask */ 39 40/* cpp contortions to concatenate w/arg prescan */ 41#ifndef PAD 42#define _PADLINE(line) pad ## line 43#define _XSTR(line) _PADLINE(line) 44#define PAD _XSTR(__LINE__) 45#endif /* PAD */ 46 47/* 48 * Host Interface Registers 49 */ 50typedef volatile struct _bcmenettregs { 51 /* Device and Power Control */ 52 uint32 devcontrol; 53 uint32 PAD[2]; 54 uint32 biststatus; 55 uint32 wakeuplength; 56 uint32 PAD[3]; 57 58 /* Interrupt Control */ 59 uint32 intstatus; 60 uint32 intmask; 61 uint32 gptimer; 62 uint32 PAD[23]; 63 64 /* Ethernet MAC Address Filtering Control */ 65 uint32 PAD[2]; 66 uint32 enetftaddr; 67 uint32 enetftdata; 68 uint32 PAD[2]; 69 70 /* Ethernet MAC Control */ 71 uint32 emactxmaxburstlen; 72 uint32 emacrxmaxburstlen; 73 uint32 emaccontrol; 74 uint32 emacflowcontrol; 75 76 uint32 PAD[20]; 77 78 /* DMA Lazy Interrupt Control */ 79 uint32 intrecvlazy; 80 uint32 PAD[63]; 81 82 /* DMA engine */ 83 dma32regp_t dmaregs; 84 dma32diag_t dmafifo; 85 uint32 PAD[116]; 86 87 /* EMAC Registers */ 88 uint32 rxconfig; 89 uint32 rxmaxlength; 90 uint32 txmaxlength; 91 uint32 PAD; 92 uint32 mdiocontrol; 93 uint32 mdiodata; 94 uint32 emacintmask; 95 uint32 emacintstatus; 96 uint32 camdatalo; 97 uint32 camdatahi; 98 uint32 camcontrol; 99 uint32 enetcontrol; 100 uint32 txcontrol; 101 uint32 txwatermark; 102 uint32 mibcontrol; 103 uint32 PAD[49]; 104 105 /* EMAC MIB counters */ 106 bcmenetmib_t mib; 107 108 uint32 PAD[585]; 109 110 /* Sonics SiliconBackplane config registers */ 111 sbconfig_t sbconfig; 112} bcmenetregs_t; 113 114/* device control */ 115#define DC_PM ((uint32)1 << 7) /* pattern filtering enable */ 116#define DC_IP ((uint32)1 << 10) /* internal ephy present (rev >= 1) */ 117#define DC_ER ((uint32)1 << 15) /* ephy reset */ 118#define DC_MP ((uint32)1 << 16) /* mii phy mode enable */ 119#define DC_CO ((uint32)1 << 17) /* mii phy mode: enable clocks */ 120#define DC_PA_MASK 0x7c0000 /* mii phy mode: mdc/mdio phy address */ 121#define DC_PA_SHIFT 18 122#define DC_FS_MASK 0x03800000 /* fifo size (rev >= 8) */ 123#define DC_FS_SHIFT 23 124#define DC_FS_4K 0 /* 4Kbytes */ 125#define DC_FS_512 1 /* 512bytes */ 126 127/* wakeup length */ 128#define WL_P0_MASK 0x7f /* pattern 0 */ 129#define WL_D0 ((uint32)1 << 7) 130#define WL_P1_MASK 0x7f00 /* pattern 1 */ 131#define WL_P1_SHIFT 8 132#define WL_D1 ((uint32)1 << 15) 133#define WL_P2_MASK 0x7f0000 /* pattern 2 */ 134#define WL_P2_SHIFT 16 135#define WL_D2 ((uint32)1 << 23) 136#define WL_P3_MASK 0x7f000000 /* pattern 3 */ 137#define WL_P3_SHIFT 24 138#define WL_D3 ((uint32)1 << 31) 139 140/* intstatus and intmask */ 141#define I_PME ((uint32)1 << 6) /* power management event */ 142#define I_TO ((uint32)1 << 7) /* general purpose timeout */ 143#define I_PC ((uint32)1 << 10) /* descriptor error */ 144#define I_PD ((uint32)1 << 11) /* data error */ 145#define I_DE ((uint32)1 << 12) /* descriptor protocol error */ 146#define I_RU ((uint32)1 << 13) /* receive descriptor underflow */ 147#define I_RO ((uint32)1 << 14) /* receive fifo overflow */ 148#define I_XU ((uint32)1 << 15) /* transmit fifo underflow */ 149#define I_RI ((uint32)1 << 16) /* receive interrupt */ 150#define I_XI ((uint32)1 << 24) /* transmit interrupt */ 151#define I_EM ((uint32)1 << 26) /* emac interrupt */ 152#define I_MW ((uint32)1 << 27) /* mii write */ 153#define I_MR ((uint32)1 << 28) /* mii read */ 154 155/* emaccontrol */ 156#define EMC_CG ((uint32)1 << 0) /* crc32 generation enable */ 157#define EMC_EP ((uint32)1 << 2) /* onchip ephy: powerdown (rev >= 1) */ 158#define EMC_ED ((uint32)1 << 3) /* onchip ephy: energy detected (rev >= 1) */ 159#define EMC_LC_MASK 0xe0 /* onchip ephy: led control (rev >= 1) */ 160#define EMC_LC_SHIFT 5 161 162/* emacflowcontrol */ 163#define EMF_RFH_MASK 0xff /* rx fifo hi water mark */ 164#define EMF_PG ((uint32)1 << 15) /* enable pause frame generation */ 165 166/* interrupt receive lazy */ 167#define IRL_TO_MASK 0x00ffffff /* timeout */ 168#define IRL_FC_MASK 0xff000000 /* frame count */ 169#define IRL_FC_SHIFT 24 /* frame count */ 170 171/* emac receive config */ 172#define ERC_DB ((uint32)1 << 0) /* disable broadcast */ 173#define ERC_AM ((uint32)1 << 1) /* accept all multicast */ 174#define ERC_RDT ((uint32)1 << 2) /* receive disable while transmitting */ 175#define ERC_PE ((uint32)1 << 3) /* promiscuous enable */ 176#define ERC_LE ((uint32)1 << 4) /* loopback enable */ 177#define ERC_FE ((uint32)1 << 5) /* enable flow control */ 178#define ERC_UF ((uint32)1 << 6) /* accept unicast flow control frame */ 179#define ERC_RF ((uint32)1 << 7) /* reject filter */ 180#define ERC_CA ((uint32)1 << 8) /* cam absent */ 181 182/* emac mdio control */ 183#define MC_MF_MASK 0x7f /* mdc frequency */ 184#define MC_PE ((uint32)1 << 7) /* mii preamble enable */ 185 186/* emac mdio data */ 187#define MD_DATA_MASK 0xffff /* r/w data */ 188#define MD_TA_MASK 0x30000 /* turnaround value */ 189#define MD_TA_SHIFT 16 190#define MD_TA_VALID (2 << MD_TA_SHIFT) /* valid ta */ 191#define MD_RA_MASK 0x7c0000 /* register address */ 192#define MD_RA_SHIFT 18 193#define MD_PMD_MASK 0xf800000 /* physical media device */ 194#define MD_PMD_SHIFT 23 195#define MD_OP_MASK 0x30000000 /* opcode */ 196#define MD_OP_SHIFT 28 197#define MD_OP_WRITE (1 << MD_OP_SHIFT) /* write op */ 198#define MD_OP_READ (2 << MD_OP_SHIFT) /* read op */ 199#define MD_SB_MASK 0xc0000000 /* start bits */ 200#define MD_SB_SHIFT 30 201#define MD_SB_START (0x1 << MD_SB_SHIFT) /* start of frame */ 202 203/* emac intstatus and intmask */ 204#define EI_MII ((uint32)1 << 0) /* mii mdio interrupt */ 205#define EI_MIB ((uint32)1 << 1) /* mib interrupt */ 206#define EI_FLOW ((uint32)1 << 2) /* flow control interrupt */ 207 208/* emac cam data high */ 209#define CD_V ((uint32)1 << 16) /* valid bit */ 210 211/* emac cam control */ 212#define CC_CE ((uint32)1 << 0) /* cam enable */ 213#define CC_MS ((uint32)1 << 1) /* mask select */ 214#define CC_RD ((uint32)1 << 2) /* read */ 215#define CC_WR ((uint32)1 << 3) /* write */ 216#define CC_INDEX_MASK 0x3f0000 /* index */ 217#define CC_INDEX_SHIFT 16 218#define CC_CB ((uint32)1 << 31) /* cam busy */ 219 220/* emac ethernet control */ 221#define EC_EE ((uint32)1 << 0) /* emac enable */ 222#define EC_ED ((uint32)1 << 1) /* emac disable */ 223#define EC_ES ((uint32)1 << 2) /* emac soft reset */ 224#define EC_EP ((uint32)1 << 3) /* external phy select */ 225 226/* emac transmit control */ 227#define EXC_FD ((uint32)1 << 0) /* full duplex */ 228#define EXC_FM ((uint32)1 << 1) /* flowmode */ 229#define EXC_SB ((uint32)1 << 2) /* single backoff enable */ 230#define EXC_SS ((uint32)1 << 3) /* small slottime */ 231 232/* emac mib control */ 233#define EMC_RZ ((uint32)1 << 0) /* autoclear on read */ 234 235#endif /* _bcmenet_47xx_h_ */ 236