1/* 2 * Include file private to the SOC Interconnect support files. 3 * 4 * Copyright (C) 2010, Broadcom Corporation. All Rights Reserved. 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 13 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 15 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 16 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * 18 * $Id: siutils_priv.h,v 1.17 2009/10/30 21:23:33 Exp $ 19 */ 20 21#ifndef _siutils_priv_h_ 22#define _siutils_priv_h_ 23 24#define SI_ERROR(args) 25 26#define SI_MSG(args) 27 28/* Define SI_VMSG to printf for verbose debugging, but don't check it in */ 29#define SI_VMSG(args) 30 31#define IS_SIM(chippkg) ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID)) 32 33 34typedef uint32 (*si_intrsoff_t)(void *intr_arg); 35typedef void (*si_intrsrestore_t)(void *intr_arg, uint32 arg); 36typedef bool (*si_intrsenabled_t)(void *intr_arg); 37 38typedef struct gpioh_item { 39 void *arg; 40 bool level; 41 gpio_handler_t handler; 42 uint32 event; 43 struct gpioh_item *next; 44} gpioh_item_t; 45 46/* misc si info needed by some of the routines */ 47typedef struct si_info { 48 struct si_pub pub; /* back plane public state (must be first field) */ 49 50 void *osh; /* osl os handle */ 51 void *sdh; /* bcmsdh handle */ 52 53 uint dev_coreid; /* the core provides driver functions */ 54 void *intr_arg; /* interrupt callback function arg */ 55 si_intrsoff_t intrsoff_fn; /* turns chip interrupts off */ 56 si_intrsrestore_t intrsrestore_fn; /* restore chip interrupts */ 57 si_intrsenabled_t intrsenabled_fn; /* check if interrupts are enabled */ 58 59 void *pch; /* PCI/E core handle */ 60 61 gpioh_item_t *gpioh_head; /* GPIO event handlers list */ 62 63 bool memseg; /* flag to toggle MEM_SEG register */ 64 65 char *vars; 66 uint varsz; 67 68 void *curmap; /* current regs va */ 69 void *regs[SI_MAXCORES]; /* other regs va */ 70 71 uint curidx; /* current core index */ 72 uint numcores; /* # discovered cores */ 73 uint coreid[SI_MAXCORES]; /* id of each core */ 74 uint32 coresba[SI_MAXCORES]; /* backplane address of each core */ 75 void *regs2[SI_MAXCORES]; /* va of each core second register set (usbh20) */ 76 uint32 coresba2[SI_MAXCORES]; /* address of each core second register set (usbh20) */ 77 uint32 coresba_size[SI_MAXCORES]; /* backplane address space size */ 78 uint32 coresba2_size[SI_MAXCORES]; /* second address space size */ 79 80 void *curwrap; /* current wrapper va */ 81 void *wrappers[SI_MAXCORES]; /* other cores wrapper va */ 82 uint32 wrapba[SI_MAXCORES]; /* address of controlling wrapper */ 83 84 uint32 cia[SI_MAXCORES]; /* erom cia entry for each core */ 85 uint32 cib[SI_MAXCORES]; /* erom cia entry for each core */ 86 uint32 oob_router; /* oob router registers for axi */ 87} si_info_t; 88 89#define SI_INFO(sih) (si_info_t *)(uintptr)sih 90 91#define GOODCOREADDR(x, b) (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \ 92 ISALIGNED((x), SI_CORE_SIZE)) 93#define GOODREGS(regs) ((regs) != NULL && ISALIGNED((uintptr)(regs), SI_CORE_SIZE)) 94#define BADCOREADDR 0 95#define GOODIDX(idx) (((uint)idx) < SI_MAXCORES) 96#define NOREV -1 /* Invalid rev */ 97 98#define PCI(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \ 99 ((si)->pub.buscoretype == PCI_CORE_ID)) 100#define PCIE(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \ 101 ((si)->pub.buscoretype == PCIE_CORE_ID)) 102#define PCMCIA(si) ((BUSTYPE((si)->pub.bustype) == PCMCIA_BUS) && ((si)->memseg == TRUE)) 103 104/* Newer chips can access PCI/PCIE and CC core without requiring to change 105 * PCI BAR0 WIN 106 */ 107#define SI_FAST(si) (((si)->pub.buscoretype == PCIE_CORE_ID) || \ 108 (((si)->pub.buscoretype == PCI_CORE_ID) && (si)->pub.buscorerev >= 13)) 109 110#define PCIEREGS(si) (((char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET)) 111#define CCREGS_FAST(si) (((char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET)) 112 113/* 114 * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/ 115 * after core switching to avoid invalid register accesss inside ISR. 116 */ 117#define INTR_OFF(si, intr_val) \ 118 if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \ 119 intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); } 120#define INTR_RESTORE(si, intr_val) \ 121 if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \ 122 (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); } 123 124/* dynamic clock control defines */ 125#define LPOMINFREQ 25000 /* low power oscillator min */ 126#define LPOMAXFREQ 43000 /* low power oscillator max */ 127#define XTALMINFREQ 19800000 /* 20 MHz - 1% */ 128#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */ 129#define PCIMINFREQ 25000000 /* 25 MHz */ 130#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */ 131 132#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */ 133#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */ 134 135#define PCI_FORCEHT(si) \ 136 (((PCIE(si)) && (si->pub.chip == BCM4311_CHIP_ID) && ((si->pub.chiprev <= 1))) || \ 137 ((PCI(si) || PCIE(si)) && (si->pub.chip == BCM4321_CHIP_ID)) || \ 138 (PCIE(si) && (si->pub.chip == BCM4716_CHIP_ID))) 139 140/* GPIO Based LED powersave defines */ 141#define DEFAULT_GPIO_ONTIME 10 /* Default: 10% on */ 142#define DEFAULT_GPIO_OFFTIME 90 /* Default: 10% on */ 143 144#ifndef DEFAULT_GPIOTIMERVAL 145#define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME) 146#endif 147 148/* Silicon Backplane externs */ 149extern void sb_scan(si_t *sih, void *regs, uint devid); 150extern uint sb_coreid(si_t *sih); 151extern uint sb_intflag(si_t *sih); 152extern uint sb_flag(si_t *sih); 153extern void sb_setint(si_t *sih, int siflag); 154extern uint sb_corevendor(si_t *sih); 155extern uint sb_corerev(si_t *sih); 156extern uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val); 157extern bool sb_iscoreup(si_t *sih); 158extern void *sb_setcoreidx(si_t *sih, uint coreidx); 159extern uint32 sb_core_cflags(si_t *sih, uint32 mask, uint32 val); 160extern void sb_core_cflags_wo(si_t *sih, uint32 mask, uint32 val); 161extern uint32 sb_core_sflags(si_t *sih, uint32 mask, uint32 val); 162extern void sb_commit(si_t *sih); 163extern uint32 sb_base(uint32 admatch); 164extern uint32 sb_size(uint32 admatch); 165extern void sb_core_reset(si_t *sih, uint32 bits, uint32 resetbits); 166extern void sb_core_disable(si_t *sih, uint32 bits); 167extern uint32 sb_addrspace(si_t *sih, uint asidx); 168extern uint32 sb_addrspacesize(si_t *sih, uint asidx); 169extern int sb_numaddrspaces(si_t *sih); 170 171extern uint32 sb_set_initiator_to(si_t *sih, uint32 to, uint idx); 172 173extern bool sb_taclear(si_t *sih, bool details); 174 175#if defined(BCMDBG_DUMP) 176extern void sb_dump(si_t *sih, struct bcmstrbuf *b); 177#endif 178#if defined(BCMDBG_DUMP) 179extern void sb_dumpregs(si_t *sih, struct bcmstrbuf *b); 180#endif 181 182/* Wake-on-wireless-LAN (WOWL) */ 183extern bool sb_pci_pmecap(si_t *sih); 184struct osl_info; 185extern bool sb_pci_fastpmecap(struct osl_info *osh); 186extern bool sb_pci_pmeclr(si_t *sih); 187extern void sb_pci_pmeen(si_t *sih); 188extern uint sb_pcie_readreg(void *sih, uint addrtype, uint offset); 189 190/* AMBA Interconnect exported externs */ 191extern si_t *ai_attach(uint pcidev, osl_t *osh, void *regs, uint bustype, 192 void *sdh, char **vars, uint *varsz); 193extern si_t *ai_kattach(osl_t *osh); 194extern void ai_scan(si_t *sih, void *regs, uint devid); 195 196extern uint ai_flag(si_t *sih); 197extern void ai_setint(si_t *sih, int siflag); 198extern uint ai_coreidx(si_t *sih); 199extern uint ai_corevendor(si_t *sih); 200extern uint ai_corerev(si_t *sih); 201extern bool ai_iscoreup(si_t *sih); 202extern void *ai_setcoreidx(si_t *sih, uint coreidx); 203extern uint32 ai_core_cflags(si_t *sih, uint32 mask, uint32 val); 204extern void ai_core_cflags_wo(si_t *sih, uint32 mask, uint32 val); 205extern uint32 ai_core_sflags(si_t *sih, uint32 mask, uint32 val); 206extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val); 207extern void ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits); 208extern void ai_core_disable(si_t *sih, uint32 bits); 209extern int ai_numaddrspaces(si_t *sih); 210extern uint32 ai_addrspace(si_t *sih, uint asidx); 211extern uint32 ai_addrspacesize(si_t *sih, uint asidx); 212extern void ai_write_wrap_reg(si_t *sih, uint32 offset, uint32 val); 213 214#if defined(BCMDBG_DUMP) 215extern void ai_dumpregs(si_t *sih, struct bcmstrbuf *b); 216#endif 217 218#ifdef SI_ENUM_BASE_VARIABLE 219extern void si_enum_base_init(si_t *sih, uint bustype); 220#endif /* SI_ENUM_BASE_VARIABLE */ 221 222#define ub_scan(a, b, c) do {} while (0) 223#define ub_flag(a) (0) 224#define ub_setint(a, b) do {} while (0) 225#define ub_coreidx(a) (0) 226#define ub_corevendor(a) (0) 227#define ub_corerev(a) (0) 228#define ub_iscoreup(a) (0) 229#define ub_setcoreidx(a, b) (0) 230#define ub_core_cflags(a, b, c) (0) 231#define ub_core_cflags_wo(a, b, c) do {} while (0) 232#define ub_core_sflags(a, b, c) (0) 233#define ub_corereg(a, b, c, d, e) (0) 234#define ub_core_reset(a, b, c) do {} while (0) 235#define ub_core_disable(a, b) do {} while (0) 236#define ub_numaddrspaces(a) (0) 237#define ub_addrspace(a, b) (0) 238#define ub_addrspacesize(a, b) (0) 239#define ub_view(a, b) do {} while (0) 240#define ub_dumpregs(a, b) do {} while (0) 241 242#endif /* _siutils_priv_h_ */ 243