1/* 2 * at91-ssc.c -- ALSA SoC AT91 SSC Audio Layer Platform driver 3 * 4 * Author: Frank Mandarino <fmandarino@endrelia.com> 5 * Endrelia Technologies Inc. 6 * 7 * Based on pxa2xx Platform drivers by 8 * Liam Girdwood <liam.girdwood@wolfsonmicro.com> 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 * 15 */ 16 17#include <linux/init.h> 18#include <linux/module.h> 19#include <linux/interrupt.h> 20#include <linux/device.h> 21#include <linux/delay.h> 22#include <linux/clk.h> 23#include <linux/atmel_pdc.h> 24 25#include <sound/driver.h> 26#include <sound/core.h> 27#include <sound/pcm.h> 28#include <sound/pcm_params.h> 29#include <sound/initval.h> 30#include <sound/soc.h> 31 32#include <asm/arch/hardware.h> 33#include <asm/arch/at91_pmc.h> 34#include <asm/arch/at91_ssc.h> 35 36#include "at91-pcm.h" 37#include "at91-ssc.h" 38 39#define DBG(x...) 40 41#if defined(CONFIG_ARCH_AT91SAM9260) 42#define NUM_SSC_DEVICES 1 43#else 44#define NUM_SSC_DEVICES 3 45#endif 46 47 48/* 49 * SSC PDC registers required by the PCM DMA engine. 50 */ 51static struct at91_pdc_regs pdc_tx_reg = { 52 .xpr = ATMEL_PDC_TPR, 53 .xcr = ATMEL_PDC_TCR, 54 .xnpr = ATMEL_PDC_TNPR, 55 .xncr = ATMEL_PDC_TNCR, 56}; 57 58static struct at91_pdc_regs pdc_rx_reg = { 59 .xpr = ATMEL_PDC_RPR, 60 .xcr = ATMEL_PDC_RCR, 61 .xnpr = ATMEL_PDC_RNPR, 62 .xncr = ATMEL_PDC_RNCR, 63}; 64 65/* 66 * SSC & PDC status bits for transmit and receive. 67 */ 68static struct at91_ssc_mask ssc_tx_mask = { 69 .ssc_enable = AT91_SSC_TXEN, 70 .ssc_disable = AT91_SSC_TXDIS, 71 .ssc_endx = AT91_SSC_ENDTX, 72 .ssc_endbuf = AT91_SSC_TXBUFE, 73 .pdc_enable = ATMEL_PDC_TXTEN, 74 .pdc_disable = ATMEL_PDC_TXTDIS, 75}; 76 77static struct at91_ssc_mask ssc_rx_mask = { 78 .ssc_enable = AT91_SSC_RXEN, 79 .ssc_disable = AT91_SSC_RXDIS, 80 .ssc_endx = AT91_SSC_ENDRX, 81 .ssc_endbuf = AT91_SSC_RXBUFF, 82 .pdc_enable = ATMEL_PDC_RXTEN, 83 .pdc_disable = ATMEL_PDC_RXTDIS, 84}; 85 86 87/* 88 * DMA parameters. 89 */ 90static struct at91_pcm_dma_params ssc_dma_params[NUM_SSC_DEVICES][2] = { 91 {{ 92 .name = "SSC0 PCM out", 93 .pdc = &pdc_tx_reg, 94 .mask = &ssc_tx_mask, 95 }, 96 { 97 .name = "SSC0 PCM in", 98 .pdc = &pdc_rx_reg, 99 .mask = &ssc_rx_mask, 100 }}, 101#if NUM_SSC_DEVICES == 3 102 {{ 103 .name = "SSC1 PCM out", 104 .pdc = &pdc_tx_reg, 105 .mask = &ssc_tx_mask, 106 }, 107 { 108 .name = "SSC1 PCM in", 109 .pdc = &pdc_rx_reg, 110 .mask = &ssc_rx_mask, 111 }}, 112 {{ 113 .name = "SSC2 PCM out", 114 .pdc = &pdc_tx_reg, 115 .mask = &ssc_tx_mask, 116 }, 117 { 118 .name = "SSC2 PCM in", 119 .pdc = &pdc_rx_reg, 120 .mask = &ssc_rx_mask, 121 }}, 122#endif 123}; 124 125struct at91_ssc_state { 126 u32 ssc_cmr; 127 u32 ssc_rcmr; 128 u32 ssc_rfmr; 129 u32 ssc_tcmr; 130 u32 ssc_tfmr; 131 u32 ssc_sr; 132 u32 ssc_imr; 133}; 134 135static struct at91_ssc_info { 136 char *name; 137 struct at91_ssc_periph ssc; 138 spinlock_t lock; /* lock for dir_mask */ 139 unsigned short dir_mask; /* 0=unused, 1=playback, 2=capture */ 140 unsigned short initialized; /* 1=SSC has been initialized */ 141 unsigned short daifmt; 142 unsigned short cmr_div; 143 unsigned short tcmr_period; 144 unsigned short rcmr_period; 145 struct at91_pcm_dma_params *dma_params[2]; 146 struct at91_ssc_state ssc_state; 147 148} ssc_info[NUM_SSC_DEVICES] = { 149 { 150 .name = "ssc0", 151 .lock = __SPIN_LOCK_UNLOCKED(ssc_info[0].lock), 152 .dir_mask = 0, 153 .initialized = 0, 154 }, 155#if NUM_SSC_DEVICES == 3 156 { 157 .name = "ssc1", 158 .lock = __SPIN_LOCK_UNLOCKED(ssc_info[1].lock), 159 .dir_mask = 0, 160 .initialized = 0, 161 }, 162 { 163 .name = "ssc2", 164 .lock = __SPIN_LOCK_UNLOCKED(ssc_info[2].lock), 165 .dir_mask = 0, 166 .initialized = 0, 167 }, 168#endif 169}; 170 171static unsigned int at91_ssc_sysclk; 172 173/* 174 * SSC interrupt handler. Passes PDC interrupts to the DMA 175 * interrupt handler in the PCM driver. 176 */ 177static irqreturn_t at91_ssc_interrupt(int irq, void *dev_id) 178{ 179 struct at91_ssc_info *ssc_p = dev_id; 180 struct at91_pcm_dma_params *dma_params; 181 u32 ssc_sr; 182 int i; 183 184 ssc_sr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_SR) 185 & at91_ssc_read(ssc_p->ssc.base + AT91_SSC_IMR); 186 187 /* 188 * Loop through the substreams attached to this SSC. If 189 * a DMA-related interrupt occurred on that substream, call 190 * the DMA interrupt handler function, if one has been 191 * registered in the dma_params structure by the PCM driver. 192 */ 193 for (i = 0; i < ARRAY_SIZE(ssc_p->dma_params); i++) { 194 dma_params = ssc_p->dma_params[i]; 195 196 if (dma_params != NULL && dma_params->dma_intr_handler != NULL && 197 (ssc_sr & 198 (dma_params->mask->ssc_endx | dma_params->mask->ssc_endbuf))) 199 200 dma_params->dma_intr_handler(ssc_sr, dma_params->substream); 201 } 202 203 return IRQ_HANDLED; 204} 205 206/* 207 * Startup. Only that one substream allowed in each direction. 208 */ 209static int at91_ssc_startup(struct snd_pcm_substream *substream) 210{ 211 struct snd_soc_pcm_runtime *rtd = substream->private_data; 212 struct at91_ssc_info *ssc_p = &ssc_info[rtd->dai->cpu_dai->id]; 213 int dir_mask; 214 215 DBG("ssc_startup: SSC_SR=0x%08lx\n", 216 at91_ssc_read(ssc_p->ssc.base + AT91_SSC_SR)); 217 dir_mask = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0x1 : 0x2; 218 219 spin_lock_irq(&ssc_p->lock); 220 if (ssc_p->dir_mask & dir_mask) { 221 spin_unlock_irq(&ssc_p->lock); 222 return -EBUSY; 223 } 224 ssc_p->dir_mask |= dir_mask; 225 spin_unlock_irq(&ssc_p->lock); 226 227 return 0; 228} 229 230/* 231 * Shutdown. Clear DMA parameters and shutdown the SSC if there 232 * are no other substreams open. 233 */ 234static void at91_ssc_shutdown(struct snd_pcm_substream *substream) 235{ 236 struct snd_soc_pcm_runtime *rtd = substream->private_data; 237 struct at91_ssc_info *ssc_p = &ssc_info[rtd->dai->cpu_dai->id]; 238 struct at91_pcm_dma_params *dma_params; 239 int dir, dir_mask; 240 241 dir = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1; 242 dma_params = ssc_p->dma_params[dir]; 243 244 if (dma_params != NULL) { 245 at91_ssc_write(dma_params->ssc_base + AT91_SSC_CR, 246 dma_params->mask->ssc_disable); 247 DBG("%s disabled SSC_SR=0x%08lx\n", (dir ? "receive" : "transmit"), 248 at91_ssc_read(ssc_p->ssc.base + AT91_SSC_SR)); 249 250 dma_params->ssc_base = NULL; 251 dma_params->substream = NULL; 252 ssc_p->dma_params[dir] = NULL; 253 } 254 255 dir_mask = 1 << dir; 256 257 spin_lock_irq(&ssc_p->lock); 258 ssc_p->dir_mask &= ~dir_mask; 259 if (!ssc_p->dir_mask) { 260 /* Shutdown the SSC clock. */ 261 DBG("Stopping pid %d clock\n", ssc_p->ssc.pid); 262 at91_sys_write(AT91_PMC_PCDR, 1<<ssc_p->ssc.pid); 263 264 if (ssc_p->initialized) { 265 free_irq(ssc_p->ssc.pid, ssc_p); 266 ssc_p->initialized = 0; 267 } 268 269 /* Reset the SSC */ 270 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_CR, AT91_SSC_SWRST); 271 272 /* Clear the SSC dividers */ 273 ssc_p->cmr_div = ssc_p->tcmr_period = ssc_p->rcmr_period = 0; 274 } 275 spin_unlock_irq(&ssc_p->lock); 276} 277 278/* 279 * Record the SSC system clock rate. 280 */ 281static int at91_ssc_set_dai_sysclk(struct snd_soc_cpu_dai *cpu_dai, 282 int clk_id, unsigned int freq, int dir) 283{ 284 /* 285 * The only clock supplied to the SSC is the AT91 master clock, 286 * which is only used if the SSC is generating BCLK and/or 287 * LRC clocks. 288 */ 289 switch (clk_id) { 290 case AT91_SYSCLK_MCK: 291 at91_ssc_sysclk = freq; 292 break; 293 default: 294 return -EINVAL; 295 } 296 297 return 0; 298} 299 300/* 301 * Record the DAI format for use in hw_params(). 302 */ 303static int at91_ssc_set_dai_fmt(struct snd_soc_cpu_dai *cpu_dai, 304 unsigned int fmt) 305{ 306 struct at91_ssc_info *ssc_p = &ssc_info[cpu_dai->id]; 307 308 ssc_p->daifmt = fmt; 309 return 0; 310} 311 312/* 313 * Record SSC clock dividers for use in hw_params(). 314 */ 315static int at91_ssc_set_dai_clkdiv(struct snd_soc_cpu_dai *cpu_dai, 316 int div_id, int div) 317{ 318 struct at91_ssc_info *ssc_p = &ssc_info[cpu_dai->id]; 319 320 switch (div_id) { 321 case AT91SSC_CMR_DIV: 322 /* 323 * The same master clock divider is used for both 324 * transmit and receive, so if a value has already 325 * been set, it must match this value. 326 */ 327 if (ssc_p->cmr_div == 0) 328 ssc_p->cmr_div = div; 329 else 330 if (div != ssc_p->cmr_div) 331 return -EBUSY; 332 break; 333 334 case AT91SSC_TCMR_PERIOD: 335 ssc_p->tcmr_period = div; 336 break; 337 338 case AT91SSC_RCMR_PERIOD: 339 ssc_p->rcmr_period = div; 340 break; 341 342 default: 343 return -EINVAL; 344 } 345 346 return 0; 347} 348 349/* 350 * Configure the SSC. 351 */ 352static int at91_ssc_hw_params(struct snd_pcm_substream *substream, 353 struct snd_pcm_hw_params *params) 354{ 355 struct snd_soc_pcm_runtime *rtd = substream->private_data; 356 int id = rtd->dai->cpu_dai->id; 357 struct at91_ssc_info *ssc_p = &ssc_info[id]; 358 struct at91_pcm_dma_params *dma_params; 359 int dir, channels, bits; 360 u32 tfmr, rfmr, tcmr, rcmr; 361 int start_event; 362 int ret; 363 364 /* 365 * Currently, there is only one set of dma params for 366 * each direction. If more are added, this code will 367 * have to be changed to select the proper set. 368 */ 369 dir = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1; 370 371 dma_params = &ssc_dma_params[id][dir]; 372 dma_params->ssc_base = ssc_p->ssc.base; 373 dma_params->substream = substream; 374 375 ssc_p->dma_params[dir] = dma_params; 376 377 /* 378 * The cpu_dai->dma_data field is only used to communicate the 379 * appropriate DMA parameters to the pcm driver hw_params() 380 * function. It should not be used for other purposes 381 * as it is common to all substreams. 382 */ 383 rtd->dai->cpu_dai->dma_data = dma_params; 384 385 channels = params_channels(params); 386 387 /* 388 * Determine sample size in bits and the PDC increment. 389 */ 390 switch(params_format(params)) { 391 case SNDRV_PCM_FORMAT_S8: 392 bits = 8; 393 dma_params->pdc_xfer_size = 1; 394 break; 395 case SNDRV_PCM_FORMAT_S16_LE: 396 bits = 16; 397 dma_params->pdc_xfer_size = 2; 398 break; 399 case SNDRV_PCM_FORMAT_S24_LE: 400 bits = 24; 401 dma_params->pdc_xfer_size = 4; 402 break; 403 case SNDRV_PCM_FORMAT_S32_LE: 404 bits = 32; 405 dma_params->pdc_xfer_size = 4; 406 break; 407 default: 408 printk(KERN_WARNING "at91-ssc: unsupported PCM format"); 409 return -EINVAL; 410 } 411 412 /* 413 * The SSC only supports up to 16-bit samples in I2S format, due 414 * to the size of the Frame Mode Register FSLEN field. 415 */ 416 if ((ssc_p->daifmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_I2S 417 && bits > 16) { 418 printk(KERN_WARNING 419 "at91-ssc: sample size %d is too large for I2S\n", bits); 420 return -EINVAL; 421 } 422 423 /* 424 * Compute SSC register settings. 425 */ 426 switch (ssc_p->daifmt 427 & (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_MASTER_MASK)) { 428 429 case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS: 430 /* 431 * I2S format, SSC provides BCLK and LRC clocks. 432 * 433 * The SSC transmit and receive clocks are generated from the 434 * MCK divider, and the BCLK signal is output on the SSC TK line. 435 */ 436 rcmr = (( ssc_p->rcmr_period << 24) & AT91_SSC_PERIOD) 437 | (( 1 << 16) & AT91_SSC_STTDLY) 438 | (( AT91_SSC_START_FALLING_RF ) & AT91_SSC_START) 439 | (( AT91_SSC_CK_RISING ) & AT91_SSC_CKI) 440 | (( AT91_SSC_CKO_NONE ) & AT91_SSC_CKO) 441 | (( AT91_SSC_CKS_DIV ) & AT91_SSC_CKS); 442 443 rfmr = (( AT91_SSC_FSEDGE_POSITIVE ) & AT91_SSC_FSEDGE) 444 | (( AT91_SSC_FSOS_NEGATIVE ) & AT91_SSC_FSOS) 445 | (((bits - 1) << 16) & AT91_SSC_FSLEN) 446 | (((channels - 1) << 8) & AT91_SSC_DATNB) 447 | (( 1 << 7) & AT91_SSC_MSBF) 448 | (( 0 << 5) & AT91_SSC_LOOP) 449 | (((bits - 1) << 0) & AT91_SSC_DATALEN); 450 451 tcmr = (( ssc_p->tcmr_period << 24) & AT91_SSC_PERIOD) 452 | (( 1 << 16) & AT91_SSC_STTDLY) 453 | (( AT91_SSC_START_FALLING_RF ) & AT91_SSC_START) 454 | (( AT91_SSC_CKI_FALLING ) & AT91_SSC_CKI) 455 | (( AT91_SSC_CKO_CONTINUOUS ) & AT91_SSC_CKO) 456 | (( AT91_SSC_CKS_DIV ) & AT91_SSC_CKS); 457 458 tfmr = (( AT91_SSC_FSEDGE_POSITIVE ) & AT91_SSC_FSEDGE) 459 | (( 0 << 23) & AT91_SSC_FSDEN) 460 | (( AT91_SSC_FSOS_NEGATIVE ) & AT91_SSC_FSOS) 461 | (((bits - 1) << 16) & AT91_SSC_FSLEN) 462 | (((channels - 1) << 8) & AT91_SSC_DATNB) 463 | (( 1 << 7) & AT91_SSC_MSBF) 464 | (( 0 << 5) & AT91_SSC_DATDEF) 465 | (((bits - 1) << 0) & AT91_SSC_DATALEN); 466 break; 467 468 case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM: 469 /* 470 * I2S format, CODEC supplies BCLK and LRC clocks. 471 * 472 * The SSC transmit clock is obtained from the BCLK signal on 473 * on the TK line, and the SSC receive clock is generated from the 474 * transmit clock. 475 * 476 * For single channel data, one sample is transferred on the falling 477 * edge of the LRC clock. For two channel data, one sample is 478 * transferred on both edges of the LRC clock. 479 */ 480 start_event = channels == 1 481 ? AT91_SSC_START_FALLING_RF 482 : AT91_SSC_START_EDGE_RF; 483 484 rcmr = (( 0 << 24) & AT91_SSC_PERIOD) 485 | (( 1 << 16) & AT91_SSC_STTDLY) 486 | (( start_event ) & AT91_SSC_START) 487 | (( AT91_SSC_CK_RISING ) & AT91_SSC_CKI) 488 | (( AT91_SSC_CKO_NONE ) & AT91_SSC_CKO) 489 | (( AT91_SSC_CKS_CLOCK ) & AT91_SSC_CKS); 490 491 rfmr = (( AT91_SSC_FSEDGE_POSITIVE ) & AT91_SSC_FSEDGE) 492 | (( AT91_SSC_FSOS_NONE ) & AT91_SSC_FSOS) 493 | (( 0 << 16) & AT91_SSC_FSLEN) 494 | (( 0 << 8) & AT91_SSC_DATNB) 495 | (( 1 << 7) & AT91_SSC_MSBF) 496 | (( 0 << 5) & AT91_SSC_LOOP) 497 | (((bits - 1) << 0) & AT91_SSC_DATALEN); 498 499 tcmr = (( 0 << 24) & AT91_SSC_PERIOD) 500 | (( 1 << 16) & AT91_SSC_STTDLY) 501 | (( start_event ) & AT91_SSC_START) 502 | (( AT91_SSC_CKI_FALLING ) & AT91_SSC_CKI) 503 | (( AT91_SSC_CKO_NONE ) & AT91_SSC_CKO) 504 | (( AT91_SSC_CKS_PIN ) & AT91_SSC_CKS); 505 506 tfmr = (( AT91_SSC_FSEDGE_POSITIVE ) & AT91_SSC_FSEDGE) 507 | (( 0 << 23) & AT91_SSC_FSDEN) 508 | (( AT91_SSC_FSOS_NONE ) & AT91_SSC_FSOS) 509 | (( 0 << 16) & AT91_SSC_FSLEN) 510 | (( 0 << 8) & AT91_SSC_DATNB) 511 | (( 1 << 7) & AT91_SSC_MSBF) 512 | (( 0 << 5) & AT91_SSC_DATDEF) 513 | (((bits - 1) << 0) & AT91_SSC_DATALEN); 514 break; 515 516 case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBS_CFS: 517 /* 518 * DSP/PCM Mode A format, SSC provides BCLK and LRC clocks. 519 * 520 * The SSC transmit and receive clocks are generated from the 521 * MCK divider, and the BCLK signal is output on the SSC TK line. 522 */ 523 rcmr = (( ssc_p->rcmr_period << 24) & AT91_SSC_PERIOD) 524 | (( 1 << 16) & AT91_SSC_STTDLY) 525 | (( AT91_SSC_START_RISING_RF ) & AT91_SSC_START) 526 | (( AT91_SSC_CK_RISING ) & AT91_SSC_CKI) 527 | (( AT91_SSC_CKO_NONE ) & AT91_SSC_CKO) 528 | (( AT91_SSC_CKS_DIV ) & AT91_SSC_CKS); 529 530 rfmr = (( AT91_SSC_FSEDGE_POSITIVE ) & AT91_SSC_FSEDGE) 531 | (( AT91_SSC_FSOS_POSITIVE ) & AT91_SSC_FSOS) 532 | (( 0 << 16) & AT91_SSC_FSLEN) 533 | (((channels - 1) << 8) & AT91_SSC_DATNB) 534 | (( 1 << 7) & AT91_SSC_MSBF) 535 | (( 0 << 5) & AT91_SSC_LOOP) 536 | (((bits - 1) << 0) & AT91_SSC_DATALEN); 537 538 tcmr = (( ssc_p->tcmr_period << 24) & AT91_SSC_PERIOD) 539 | (( 1 << 16) & AT91_SSC_STTDLY) 540 | (( AT91_SSC_START_RISING_RF ) & AT91_SSC_START) 541 | (( AT91_SSC_CK_RISING ) & AT91_SSC_CKI) 542 | (( AT91_SSC_CKO_CONTINUOUS ) & AT91_SSC_CKO) 543 | (( AT91_SSC_CKS_DIV ) & AT91_SSC_CKS); 544 545 tfmr = (( AT91_SSC_FSEDGE_POSITIVE ) & AT91_SSC_FSEDGE) 546 | (( 0 << 23) & AT91_SSC_FSDEN) 547 | (( AT91_SSC_FSOS_POSITIVE ) & AT91_SSC_FSOS) 548 | (( 0 << 16) & AT91_SSC_FSLEN) 549 | (((channels - 1) << 8) & AT91_SSC_DATNB) 550 | (( 1 << 7) & AT91_SSC_MSBF) 551 | (( 0 << 5) & AT91_SSC_DATDEF) 552 | (((bits - 1) << 0) & AT91_SSC_DATALEN); 553 554 555 556 break; 557 558 case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM: 559 default: 560 printk(KERN_WARNING "at91-ssc: unsupported DAI format 0x%x.\n", 561 ssc_p->daifmt); 562 return -EINVAL; 563 break; 564 } 565 DBG("RCMR=%08x RFMR=%08x TCMR=%08x TFMR=%08x\n", rcmr, rfmr, tcmr, tfmr); 566 567 if (!ssc_p->initialized) { 568 569 /* Enable PMC peripheral clock for this SSC */ 570 DBG("Starting pid %d clock\n", ssc_p->ssc.pid); 571 at91_sys_write(AT91_PMC_PCER, 1<<ssc_p->ssc.pid); 572 573 /* Reset the SSC and its PDC registers */ 574 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_CR, AT91_SSC_SWRST); 575 576 at91_ssc_write(ssc_p->ssc.base + ATMEL_PDC_RPR, 0); 577 at91_ssc_write(ssc_p->ssc.base + ATMEL_PDC_RCR, 0); 578 at91_ssc_write(ssc_p->ssc.base + ATMEL_PDC_RNPR, 0); 579 at91_ssc_write(ssc_p->ssc.base + ATMEL_PDC_RNCR, 0); 580 at91_ssc_write(ssc_p->ssc.base + ATMEL_PDC_TPR, 0); 581 at91_ssc_write(ssc_p->ssc.base + ATMEL_PDC_TCR, 0); 582 at91_ssc_write(ssc_p->ssc.base + ATMEL_PDC_TNPR, 0); 583 at91_ssc_write(ssc_p->ssc.base + ATMEL_PDC_TNCR, 0); 584 585 if ((ret = request_irq(ssc_p->ssc.pid, at91_ssc_interrupt, 586 0, ssc_p->name, ssc_p)) < 0) { 587 printk(KERN_WARNING "at91-ssc: request_irq failure\n"); 588 589 DBG("Stopping pid %d clock\n", ssc_p->ssc.pid); 590 at91_sys_write(AT91_PMC_PCER, 1<<ssc_p->ssc.pid); 591 return ret; 592 } 593 594 ssc_p->initialized = 1; 595 } 596 597 /* set SSC clock mode register */ 598 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_CMR, ssc_p->cmr_div); 599 600 /* set receive clock mode and format */ 601 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_RCMR, rcmr); 602 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_RFMR, rfmr); 603 604 /* set transmit clock mode and format */ 605 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_TCMR, tcmr); 606 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_TFMR, tfmr); 607 608 DBG("hw_params: SSC initialized\n"); 609 return 0; 610} 611 612 613static int at91_ssc_prepare(struct snd_pcm_substream *substream) 614{ 615 struct snd_soc_pcm_runtime *rtd = substream->private_data; 616 struct at91_ssc_info *ssc_p = &ssc_info[rtd->dai->cpu_dai->id]; 617 struct at91_pcm_dma_params *dma_params; 618 int dir; 619 620 dir = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1; 621 dma_params = ssc_p->dma_params[dir]; 622 623 at91_ssc_write(dma_params->ssc_base + AT91_SSC_CR, 624 dma_params->mask->ssc_enable); 625 626 DBG("%s enabled SSC_SR=0x%08lx\n", dir ? "receive" : "transmit", 627 at91_ssc_read(dma_params->ssc_base + AT91_SSC_SR)); 628 return 0; 629} 630 631 632#ifdef CONFIG_PM 633static int at91_ssc_suspend(struct platform_device *pdev, 634 struct snd_soc_cpu_dai *cpu_dai) 635{ 636 struct at91_ssc_info *ssc_p; 637 638 if(!cpu_dai->active) 639 return 0; 640 641 ssc_p = &ssc_info[cpu_dai->id]; 642 643 /* Save the status register before disabling transmit and receive. */ 644 ssc_p->ssc_state.ssc_sr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_SR); 645 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_CR, 646 AT91_SSC_TXDIS | AT91_SSC_RXDIS); 647 648 /* Save the current interrupt mask, then disable unmasked interrupts. */ 649 ssc_p->ssc_state.ssc_imr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_IMR); 650 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_IDR, ssc_p->ssc_state.ssc_imr); 651 652 ssc_p->ssc_state.ssc_cmr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_CMR); 653 ssc_p->ssc_state.ssc_rcmr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_RCMR); 654 ssc_p->ssc_state.ssc_rfmr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_RFMR); 655 ssc_p->ssc_state.ssc_tcmr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_TCMR); 656 ssc_p->ssc_state.ssc_tfmr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_TFMR); 657 658 return 0; 659} 660 661static int at91_ssc_resume(struct platform_device *pdev, 662 struct snd_soc_cpu_dai *cpu_dai) 663{ 664 struct at91_ssc_info *ssc_p; 665 666 if(!cpu_dai->active) 667 return 0; 668 669 ssc_p = &ssc_info[cpu_dai->id]; 670 671 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_TFMR, ssc_p->ssc_state.ssc_tfmr); 672 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_TCMR, ssc_p->ssc_state.ssc_tcmr); 673 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_RFMR, ssc_p->ssc_state.ssc_rfmr); 674 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_RCMR, ssc_p->ssc_state.ssc_rcmr); 675 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_CMR, ssc_p->ssc_state.ssc_cmr); 676 677 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_IER, ssc_p->ssc_state.ssc_imr); 678 679 at91_ssc_write(ssc_p->ssc.base + AT91_SSC_CR, 680 ((ssc_p->ssc_state.ssc_sr & AT91_SSC_RXENA) ? AT91_SSC_RXEN : 0) | 681 ((ssc_p->ssc_state.ssc_sr & AT91_SSC_TXENA) ? AT91_SSC_TXEN : 0)); 682 683 return 0; 684} 685 686#else 687#define at91_ssc_suspend NULL 688#define at91_ssc_resume NULL 689#endif 690 691#define AT91_SSC_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ 692 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\ 693 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\ 694 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |\ 695 SNDRV_PCM_RATE_96000) 696 697#define AT91_SSC_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\ 698 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 699 700struct snd_soc_cpu_dai at91_ssc_dai[NUM_SSC_DEVICES] = { 701 { .name = "at91-ssc0", 702 .id = 0, 703 .type = SND_SOC_DAI_PCM, 704 .suspend = at91_ssc_suspend, 705 .resume = at91_ssc_resume, 706 .playback = { 707 .channels_min = 1, 708 .channels_max = 2, 709 .rates = AT91_SSC_RATES, 710 .formats = AT91_SSC_FORMATS,}, 711 .capture = { 712 .channels_min = 1, 713 .channels_max = 2, 714 .rates = AT91_SSC_RATES, 715 .formats = AT91_SSC_FORMATS,}, 716 .ops = { 717 .startup = at91_ssc_startup, 718 .shutdown = at91_ssc_shutdown, 719 .prepare = at91_ssc_prepare, 720 .hw_params = at91_ssc_hw_params,}, 721 .dai_ops = { 722 .set_sysclk = at91_ssc_set_dai_sysclk, 723 .set_fmt = at91_ssc_set_dai_fmt, 724 .set_clkdiv = at91_ssc_set_dai_clkdiv,}, 725 .private_data = &ssc_info[0].ssc, 726 }, 727#if NUM_SSC_DEVICES == 3 728 { .name = "at91-ssc1", 729 .id = 1, 730 .type = SND_SOC_DAI_PCM, 731 .suspend = at91_ssc_suspend, 732 .resume = at91_ssc_resume, 733 .playback = { 734 .channels_min = 1, 735 .channels_max = 2, 736 .rates = AT91_SSC_RATES, 737 .formats = AT91_SSC_FORMATS,}, 738 .capture = { 739 .channels_min = 1, 740 .channels_max = 2, 741 .rates = AT91_SSC_RATES, 742 .formats = AT91_SSC_FORMATS,}, 743 .ops = { 744 .startup = at91_ssc_startup, 745 .shutdown = at91_ssc_shutdown, 746 .prepare = at91_ssc_prepare, 747 .hw_params = at91_ssc_hw_params,}, 748 .dai_ops = { 749 .set_sysclk = at91_ssc_set_dai_sysclk, 750 .set_fmt = at91_ssc_set_dai_fmt, 751 .set_clkdiv = at91_ssc_set_dai_clkdiv,}, 752 .private_data = &ssc_info[1].ssc, 753 }, 754 { .name = "at91-ssc2", 755 .id = 2, 756 .type = SND_SOC_DAI_PCM, 757 .suspend = at91_ssc_suspend, 758 .resume = at91_ssc_resume, 759 .playback = { 760 .channels_min = 1, 761 .channels_max = 2, 762 .rates = AT91_SSC_RATES, 763 .formats = AT91_SSC_FORMATS,}, 764 .capture = { 765 .channels_min = 1, 766 .channels_max = 2, 767 .rates = AT91_SSC_RATES, 768 .formats = AT91_SSC_FORMATS,}, 769 .ops = { 770 .startup = at91_ssc_startup, 771 .shutdown = at91_ssc_shutdown, 772 .prepare = at91_ssc_prepare, 773 .hw_params = at91_ssc_hw_params,}, 774 .dai_ops = { 775 .set_sysclk = at91_ssc_set_dai_sysclk, 776 .set_fmt = at91_ssc_set_dai_fmt, 777 .set_clkdiv = at91_ssc_set_dai_clkdiv,}, 778 .private_data = &ssc_info[2].ssc, 779 }, 780#endif 781}; 782 783EXPORT_SYMBOL_GPL(at91_ssc_dai); 784 785/* Module information */ 786MODULE_AUTHOR("Frank Mandarino, fmandarino@endrelia.com, www.endrelia.com"); 787MODULE_DESCRIPTION("AT91 SSC ASoC Interface"); 788MODULE_LICENSE("GPL"); 789