1/* 2 * Driver for Digigram pcxhr compatible soundcards 3 * 4 * main file with alsa callbacks 5 * 6 * Copyright (c) 2004 by Digigram <alsa@digigram.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 23 24#include <sound/driver.h> 25#include <linux/init.h> 26#include <linux/interrupt.h> 27#include <linux/slab.h> 28#include <linux/pci.h> 29#include <linux/dma-mapping.h> 30#include <linux/delay.h> 31#include <linux/moduleparam.h> 32#include <linux/mutex.h> 33 34#include <sound/core.h> 35#include <sound/initval.h> 36#include <sound/info.h> 37#include <sound/control.h> 38#include <sound/pcm.h> 39#include <sound/pcm_params.h> 40#include "pcxhr.h" 41#include "pcxhr_mixer.h" 42#include "pcxhr_hwdep.h" 43#include "pcxhr_core.h" 44 45#define DRIVER_NAME "pcxhr" 46 47MODULE_AUTHOR("Markus Bollinger <bollinger@digigram.com>"); 48MODULE_DESCRIPTION("Digigram " DRIVER_NAME " " PCXHR_DRIVER_VERSION_STRING); 49MODULE_LICENSE("GPL"); 50MODULE_SUPPORTED_DEVICE("{{Digigram," DRIVER_NAME "}}"); 51 52static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 53static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 54static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ 55static int mono[SNDRV_CARDS]; /* capture in mono only */ 56 57module_param_array(index, int, NULL, 0444); 58MODULE_PARM_DESC(index, "Index value for Digigram " DRIVER_NAME " soundcard"); 59module_param_array(id, charp, NULL, 0444); 60MODULE_PARM_DESC(id, "ID string for Digigram " DRIVER_NAME " soundcard"); 61module_param_array(enable, bool, NULL, 0444); 62MODULE_PARM_DESC(enable, "Enable Digigram " DRIVER_NAME " soundcard"); 63module_param_array(mono, bool, NULL, 0444); 64MODULE_PARM_DESC(mono, "Mono capture mode (default is stereo)"); 65 66enum { 67 PCI_ID_VX882HR, 68 PCI_ID_PCX882HR, 69 PCI_ID_VX881HR, 70 PCI_ID_PCX881HR, 71 PCI_ID_PCX1222HR, 72 PCI_ID_PCX1221HR, 73 PCI_ID_LAST 74}; 75 76static struct pci_device_id pcxhr_ids[] = { 77 { 0x10b5, 0x9656, 0x1369, 0xb001, 0, 0, PCI_ID_VX882HR, }, /* VX882HR */ 78 { 0x10b5, 0x9656, 0x1369, 0xb101, 0, 0, PCI_ID_PCX882HR, }, /* PCX882HR */ 79 { 0x10b5, 0x9656, 0x1369, 0xb201, 0, 0, PCI_ID_VX881HR, }, /* VX881HR */ 80 { 0x10b5, 0x9656, 0x1369, 0xb301, 0, 0, PCI_ID_PCX881HR, }, /* PCX881HR */ 81 { 0x10b5, 0x9656, 0x1369, 0xb501, 0, 0, PCI_ID_PCX1222HR, }, /* PCX1222HR */ 82 { 0x10b5, 0x9656, 0x1369, 0xb701, 0, 0, PCI_ID_PCX1221HR, }, /* PCX1221HR */ 83 { 0, } 84}; 85 86MODULE_DEVICE_TABLE(pci, pcxhr_ids); 87 88struct board_parameters { 89 char* board_name; 90 short playback_chips; 91 short capture_chips; 92 short firmware_num; 93}; 94static struct board_parameters pcxhr_board_params[] = { 95[PCI_ID_VX882HR] = { "VX882HR", 4, 4, 41, }, 96[PCI_ID_PCX882HR] = { "PCX882HR", 4, 4, 41, }, 97[PCI_ID_VX881HR] = { "VX881HR", 4, 4, 41, }, 98[PCI_ID_PCX881HR] = { "PCX881HR", 4, 4, 41, }, 99[PCI_ID_PCX1222HR] = { "PCX1222HR", 6, 1, 42, }, 100[PCI_ID_PCX1221HR] = { "PCX1221HR", 6, 1, 42, }, 101}; 102 103 104static int pcxhr_pll_freq_register(unsigned int freq, unsigned int* pllreg, 105 unsigned int* realfreq) 106{ 107 unsigned int reg; 108 109 if (freq < 6900 || freq > 110250) 110 return -EINVAL; 111 reg = (28224000 * 10) / freq; 112 reg = (reg + 5) / 10; 113 if (reg < 0x200) 114 *pllreg = reg + 0x800; 115 else if (reg < 0x400) 116 *pllreg = reg & 0x1ff; 117 else if (reg < 0x800) { 118 *pllreg = ((reg >> 1) & 0x1ff) + 0x200; 119 reg &= ~1; 120 } else { 121 *pllreg = ((reg >> 2) & 0x1ff) + 0x400; 122 reg &= ~3; 123 } 124 if (realfreq) 125 *realfreq = ((28224000 * 10) / reg + 5) / 10; 126 return 0; 127} 128 129 130#define PCXHR_FREQ_REG_MASK 0x1f 131#define PCXHR_FREQ_QUARTZ_48000 0x00 132#define PCXHR_FREQ_QUARTZ_24000 0x01 133#define PCXHR_FREQ_QUARTZ_12000 0x09 134#define PCXHR_FREQ_QUARTZ_32000 0x08 135#define PCXHR_FREQ_QUARTZ_16000 0x04 136#define PCXHR_FREQ_QUARTZ_8000 0x0c 137#define PCXHR_FREQ_QUARTZ_44100 0x02 138#define PCXHR_FREQ_QUARTZ_22050 0x0a 139#define PCXHR_FREQ_QUARTZ_11025 0x06 140#define PCXHR_FREQ_PLL 0x05 141#define PCXHR_FREQ_QUARTZ_192000 0x10 142#define PCXHR_FREQ_QUARTZ_96000 0x18 143#define PCXHR_FREQ_QUARTZ_176400 0x14 144#define PCXHR_FREQ_QUARTZ_88200 0x1c 145#define PCXHR_FREQ_QUARTZ_128000 0x12 146#define PCXHR_FREQ_QUARTZ_64000 0x1a 147 148#define PCXHR_FREQ_WORD_CLOCK 0x0f 149#define PCXHR_FREQ_SYNC_AES 0x0e 150#define PCXHR_FREQ_AES_1 0x07 151#define PCXHR_FREQ_AES_2 0x0b 152#define PCXHR_FREQ_AES_3 0x03 153#define PCXHR_FREQ_AES_4 0x0d 154 155#define PCXHR_MODIFY_CLOCK_S_BIT 0x04 156 157#define PCXHR_IRQ_TIMER_FREQ 92000 158#define PCXHR_IRQ_TIMER_PERIOD 48 159 160static int pcxhr_get_clock_reg(struct pcxhr_mgr *mgr, unsigned int rate, 161 unsigned int *reg, unsigned int *freq) 162{ 163 unsigned int val, realfreq, pllreg; 164 struct pcxhr_rmh rmh; 165 int err; 166 167 realfreq = rate; 168 switch (mgr->use_clock_type) { 169 case PCXHR_CLOCK_TYPE_INTERNAL : /* clock by quartz or pll */ 170 switch (rate) { 171 case 48000 : val = PCXHR_FREQ_QUARTZ_48000; break; 172 case 24000 : val = PCXHR_FREQ_QUARTZ_24000; break; 173 case 12000 : val = PCXHR_FREQ_QUARTZ_12000; break; 174 case 32000 : val = PCXHR_FREQ_QUARTZ_32000; break; 175 case 16000 : val = PCXHR_FREQ_QUARTZ_16000; break; 176 case 8000 : val = PCXHR_FREQ_QUARTZ_8000; break; 177 case 44100 : val = PCXHR_FREQ_QUARTZ_44100; break; 178 case 22050 : val = PCXHR_FREQ_QUARTZ_22050; break; 179 case 11025 : val = PCXHR_FREQ_QUARTZ_11025; break; 180 case 192000 : val = PCXHR_FREQ_QUARTZ_192000; break; 181 case 96000 : val = PCXHR_FREQ_QUARTZ_96000; break; 182 case 176400 : val = PCXHR_FREQ_QUARTZ_176400; break; 183 case 88200 : val = PCXHR_FREQ_QUARTZ_88200; break; 184 case 128000 : val = PCXHR_FREQ_QUARTZ_128000; break; 185 case 64000 : val = PCXHR_FREQ_QUARTZ_64000; break; 186 default : 187 val = PCXHR_FREQ_PLL; 188 /* get the value for the pll register */ 189 err = pcxhr_pll_freq_register(rate, &pllreg, &realfreq); 190 if (err) 191 return err; 192 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); 193 rmh.cmd[0] |= IO_NUM_REG_GENCLK; 194 rmh.cmd[1] = pllreg & MASK_DSP_WORD; 195 rmh.cmd[2] = pllreg >> 24; 196 rmh.cmd_len = 3; 197 err = pcxhr_send_msg(mgr, &rmh); 198 if (err < 0) { 199 snd_printk(KERN_ERR 200 "error CMD_ACCESS_IO_WRITE for PLL register : %x!\n", 201 err ); 202 return err; 203 } 204 } 205 break; 206 case PCXHR_CLOCK_TYPE_WORD_CLOCK : val = PCXHR_FREQ_WORD_CLOCK; break; 207 case PCXHR_CLOCK_TYPE_AES_SYNC : val = PCXHR_FREQ_SYNC_AES; break; 208 case PCXHR_CLOCK_TYPE_AES_1 : val = PCXHR_FREQ_AES_1; break; 209 case PCXHR_CLOCK_TYPE_AES_2 : val = PCXHR_FREQ_AES_2; break; 210 case PCXHR_CLOCK_TYPE_AES_3 : val = PCXHR_FREQ_AES_3; break; 211 case PCXHR_CLOCK_TYPE_AES_4 : val = PCXHR_FREQ_AES_4; break; 212 default : return -EINVAL; 213 } 214 *reg = val; 215 *freq = realfreq; 216 return 0; 217} 218 219 220int pcxhr_set_clock(struct pcxhr_mgr *mgr, unsigned int rate) 221{ 222 unsigned int val, realfreq, speed; 223 struct pcxhr_rmh rmh; 224 int err, changed; 225 226 if (rate == 0) 227 return 0; /* nothing to do */ 228 229 err = pcxhr_get_clock_reg(mgr, rate, &val, &realfreq); 230 if (err) 231 return err; 232 233 /* codec speed modes */ 234 if (rate < 55000) 235 speed = 0; /* single speed */ 236 else if (rate < 100000) 237 speed = 1; /* dual speed */ 238 else 239 speed = 2; /* quad speed */ 240 if (mgr->codec_speed != speed) { 241 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* mute outputs */ 242 rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT; 243 err = pcxhr_send_msg(mgr, &rmh); 244 if (err) 245 return err; 246 247 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* set speed ratio */ 248 rmh.cmd[0] |= IO_NUM_SPEED_RATIO; 249 rmh.cmd[1] = speed; 250 rmh.cmd_len = 2; 251 err = pcxhr_send_msg(mgr, &rmh); 252 if (err) 253 return err; 254 } 255 /* set the new frequency */ 256 snd_printdd("clock register : set %x\n", val); 257 err = pcxhr_write_io_num_reg_cont(mgr, PCXHR_FREQ_REG_MASK, val, &changed); 258 if (err) 259 return err; 260 mgr->sample_rate_real = realfreq; 261 mgr->cur_clock_type = mgr->use_clock_type; 262 263 /* unmute after codec speed modes */ 264 if (mgr->codec_speed != speed) { 265 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ); /* unmute outputs */ 266 rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT; 267 err = pcxhr_send_msg(mgr, &rmh); 268 if (err) 269 return err; 270 mgr->codec_speed = speed; /* save new codec speed */ 271 } 272 273 if (changed) { 274 pcxhr_init_rmh(&rmh, CMD_MODIFY_CLOCK); 275 rmh.cmd[0] |= PCXHR_MODIFY_CLOCK_S_BIT; /* resync fifos */ 276 if (rate < PCXHR_IRQ_TIMER_FREQ) 277 rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD; 278 else 279 rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD * 2; 280 rmh.cmd[2] = rate; 281 rmh.cmd_len = 3; 282 err = pcxhr_send_msg(mgr, &rmh); 283 if (err) 284 return err; 285 } 286 snd_printdd("pcxhr_set_clock to %dHz (realfreq=%d)\n", rate, realfreq); 287 return 0; 288} 289 290 291int pcxhr_get_external_clock(struct pcxhr_mgr *mgr, enum pcxhr_clock_type clock_type, 292 int *sample_rate) 293{ 294 struct pcxhr_rmh rmh; 295 unsigned char reg; 296 int err, rate; 297 298 switch (clock_type) { 299 case PCXHR_CLOCK_TYPE_WORD_CLOCK : reg = REG_STATUS_WORD_CLOCK; break; 300 case PCXHR_CLOCK_TYPE_AES_SYNC : reg = REG_STATUS_AES_SYNC; break; 301 case PCXHR_CLOCK_TYPE_AES_1 : reg = REG_STATUS_AES_1; break; 302 case PCXHR_CLOCK_TYPE_AES_2 : reg = REG_STATUS_AES_2; break; 303 case PCXHR_CLOCK_TYPE_AES_3 : reg = REG_STATUS_AES_3; break; 304 case PCXHR_CLOCK_TYPE_AES_4 : reg = REG_STATUS_AES_4; break; 305 default : return -EINVAL; 306 } 307 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ); 308 rmh.cmd_len = 2; 309 rmh.cmd[0] |= IO_NUM_REG_STATUS; 310 if (mgr->last_reg_stat != reg) { 311 rmh.cmd[1] = reg; 312 err = pcxhr_send_msg(mgr, &rmh); 313 if (err) 314 return err; 315 udelay(100); /* wait minimum 2 sample_frames at 32kHz ! */ 316 mgr->last_reg_stat = reg; 317 } 318 rmh.cmd[1] = REG_STATUS_CURRENT; 319 err = pcxhr_send_msg(mgr, &rmh); 320 if (err) 321 return err; 322 switch (rmh.stat[1] & 0x0f) { 323 case REG_STATUS_SYNC_32000 : rate = 32000; break; 324 case REG_STATUS_SYNC_44100 : rate = 44100; break; 325 case REG_STATUS_SYNC_48000 : rate = 48000; break; 326 case REG_STATUS_SYNC_64000 : rate = 64000; break; 327 case REG_STATUS_SYNC_88200 : rate = 88200; break; 328 case REG_STATUS_SYNC_96000 : rate = 96000; break; 329 case REG_STATUS_SYNC_128000 : rate = 128000; break; 330 case REG_STATUS_SYNC_176400 : rate = 176400; break; 331 case REG_STATUS_SYNC_192000 : rate = 192000; break; 332 default: rate = 0; 333 } 334 snd_printdd("External clock is at %d Hz\n", rate); 335 *sample_rate = rate; 336 return 0; 337} 338 339 340/* 341 * start or stop playback/capture substream 342 */ 343static int pcxhr_set_stream_state(struct pcxhr_stream *stream) 344{ 345 int err; 346 struct snd_pcxhr *chip; 347 struct pcxhr_rmh rmh; 348 int stream_mask, start; 349 350 if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN) 351 start = 1; 352 else { 353 if (stream->status != PCXHR_STREAM_STATUS_SCHEDULE_STOP) { 354 snd_printk(KERN_ERR "ERROR pcxhr_set_stream_state CANNOT be stopped\n"); 355 return -EINVAL; 356 } 357 start = 0; 358 } 359 if (!stream->substream) 360 return -EINVAL; 361 362 stream->timer_abs_periods = 0; 363 stream->timer_period_frag = 0; /* reset theoretical stream pos */ 364 stream->timer_buf_periods = 0; 365 stream->timer_is_synced = 0; 366 367 stream_mask = stream->pipe->is_capture ? 1 : 1<<stream->substream->number; 368 369 pcxhr_init_rmh(&rmh, start ? CMD_START_STREAM : CMD_STOP_STREAM); 370 pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture, 371 stream->pipe->first_audio, 0, stream_mask); 372 373 chip = snd_pcm_substream_chip(stream->substream); 374 375 err = pcxhr_send_msg(chip->mgr, &rmh); 376 if (err) 377 snd_printk(KERN_ERR "ERROR pcxhr_set_stream_state err=%x;\n", err); 378 stream->status = start ? PCXHR_STREAM_STATUS_STARTED : PCXHR_STREAM_STATUS_STOPPED; 379 return err; 380} 381 382#define HEADER_FMT_BASE_LIN 0xfed00000 383#define HEADER_FMT_BASE_FLOAT 0xfad00000 384#define HEADER_FMT_INTEL 0x00008000 385#define HEADER_FMT_24BITS 0x00004000 386#define HEADER_FMT_16BITS 0x00002000 387#define HEADER_FMT_UPTO11 0x00000200 388#define HEADER_FMT_UPTO32 0x00000100 389#define HEADER_FMT_MONO 0x00000080 390 391static int pcxhr_set_format(struct pcxhr_stream *stream) 392{ 393 int err, is_capture, sample_rate, stream_num; 394 struct snd_pcxhr *chip; 395 struct pcxhr_rmh rmh; 396 unsigned int header; 397 398 switch (stream->format) { 399 case SNDRV_PCM_FORMAT_U8: 400 header = HEADER_FMT_BASE_LIN; 401 break; 402 case SNDRV_PCM_FORMAT_S16_LE: 403 header = HEADER_FMT_BASE_LIN | HEADER_FMT_16BITS | HEADER_FMT_INTEL; 404 break; 405 case SNDRV_PCM_FORMAT_S16_BE: 406 header = HEADER_FMT_BASE_LIN | HEADER_FMT_16BITS; 407 break; 408 case SNDRV_PCM_FORMAT_S24_3LE: 409 header = HEADER_FMT_BASE_LIN | HEADER_FMT_24BITS | HEADER_FMT_INTEL; 410 break; 411 case SNDRV_PCM_FORMAT_S24_3BE: 412 header = HEADER_FMT_BASE_LIN | HEADER_FMT_24BITS; 413 break; 414 case SNDRV_PCM_FORMAT_FLOAT_LE: 415 header = HEADER_FMT_BASE_FLOAT | HEADER_FMT_INTEL; 416 break; 417 default: 418 snd_printk(KERN_ERR "error pcxhr_set_format() : unknown format\n"); 419 return -EINVAL; 420 } 421 chip = snd_pcm_substream_chip(stream->substream); 422 423 sample_rate = chip->mgr->sample_rate; 424 if (sample_rate <= 32000 && sample_rate !=0) { 425 if (sample_rate <= 11025) 426 header |= HEADER_FMT_UPTO11; 427 else 428 header |= HEADER_FMT_UPTO32; 429 } 430 if (stream->channels == 1) 431 header |= HEADER_FMT_MONO; 432 433 is_capture = stream->pipe->is_capture; 434 stream_num = is_capture ? 0 : stream->substream->number; 435 436 pcxhr_init_rmh(&rmh, is_capture ? CMD_FORMAT_STREAM_IN : CMD_FORMAT_STREAM_OUT); 437 pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio, stream_num, 0); 438 if (is_capture) 439 rmh.cmd[0] |= 1<<12; 440 rmh.cmd[1] = 0; 441 rmh.cmd[2] = header >> 8; 442 rmh.cmd[3] = (header & 0xff) << 16; 443 rmh.cmd_len = 4; 444 err = pcxhr_send_msg(chip->mgr, &rmh); 445 if (err) 446 snd_printk(KERN_ERR "ERROR pcxhr_set_format err=%x;\n", err); 447 return err; 448} 449 450static int pcxhr_update_r_buffer(struct pcxhr_stream *stream) 451{ 452 int err, is_capture, stream_num; 453 struct pcxhr_rmh rmh; 454 struct snd_pcm_substream *subs = stream->substream; 455 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs); 456 457 is_capture = (subs->stream == SNDRV_PCM_STREAM_CAPTURE); 458 stream_num = is_capture ? 0 : subs->number; 459 460 snd_printdd("pcxhr_update_r_buffer(pcm%c%d) : addr(%p) bytes(%zx) subs(%d)\n", 461 is_capture ? 'c' : 'p', 462 chip->chip_idx, (void*)subs->runtime->dma_addr, 463 subs->runtime->dma_bytes, subs->number); 464 465 pcxhr_init_rmh(&rmh, CMD_UPDATE_R_BUFFERS); 466 pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio, stream_num, 0); 467 468 snd_assert(subs->runtime->dma_bytes < 0x200000); /* max buffer size is 2 MByte */ 469 rmh.cmd[1] = subs->runtime->dma_bytes * 8; /* size in bits */ 470 rmh.cmd[2] = subs->runtime->dma_addr >> 24; /* most significant byte */ 471 rmh.cmd[2] |= 1<<19; /* this is a circular buffer */ 472 rmh.cmd[3] = subs->runtime->dma_addr & MASK_DSP_WORD; /* least 3 significant bytes */ 473 rmh.cmd_len = 4; 474 err = pcxhr_send_msg(chip->mgr, &rmh); 475 if (err) 476 snd_printk(KERN_ERR "ERROR CMD_UPDATE_R_BUFFERS err=%x;\n", err); 477 return err; 478} 479 480 481 482static inline int pcxhr_stream_scheduled_get_pipe(struct pcxhr_stream *stream, 483 struct pcxhr_pipe **pipe) 484{ 485 if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN) { 486 *pipe = stream->pipe; 487 return 1; 488 } 489 return 0; 490} 491 492static void pcxhr_trigger_tasklet(unsigned long arg) 493{ 494 unsigned long flags; 495 int i, j, err; 496 struct pcxhr_pipe *pipe; 497 struct snd_pcxhr *chip; 498 struct pcxhr_mgr *mgr = (struct pcxhr_mgr*)(arg); 499 int capture_mask = 0; 500 int playback_mask = 0; 501 502#ifdef CONFIG_SND_DEBUG_DETECT 503 struct timeval my_tv1, my_tv2; 504 do_gettimeofday(&my_tv1); 505#endif 506 mutex_lock(&mgr->setup_mutex); 507 508 /* check the pipes concerned and build pipe_array */ 509 for (i = 0; i < mgr->num_cards; i++) { 510 chip = mgr->chip[i]; 511 for (j = 0; j < chip->nb_streams_capt; j++) { 512 if (pcxhr_stream_scheduled_get_pipe(&chip->capture_stream[j], &pipe)) 513 capture_mask |= (1 << pipe->first_audio); 514 } 515 for (j = 0; j < chip->nb_streams_play; j++) { 516 if (pcxhr_stream_scheduled_get_pipe(&chip->playback_stream[j], &pipe)) { 517 playback_mask |= (1 << pipe->first_audio); 518 break; /* add only once, as all playback streams of 519 * one chip use the same pipe 520 */ 521 } 522 } 523 } 524 if (capture_mask == 0 && playback_mask == 0) { 525 mutex_unlock(&mgr->setup_mutex); 526 snd_printk(KERN_ERR "pcxhr_trigger_tasklet : no pipes\n"); 527 return; 528 } 529 530 snd_printdd("pcxhr_trigger_tasklet : playback_mask=%x capture_mask=%x\n", 531 playback_mask, capture_mask); 532 533 /* synchronous stop of all the pipes concerned */ 534 err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 0); 535 if (err) { 536 mutex_unlock(&mgr->setup_mutex); 537 snd_printk(KERN_ERR "pcxhr_trigger_tasklet : error stop pipes (P%x C%x)\n", 538 playback_mask, capture_mask); 539 return; 540 } 541 542 /* unfortunately the dsp lost format and buffer info with the stop pipe */ 543 for (i = 0; i < mgr->num_cards; i++) { 544 struct pcxhr_stream *stream; 545 chip = mgr->chip[i]; 546 for (j = 0; j < chip->nb_streams_capt; j++) { 547 stream = &chip->capture_stream[j]; 548 if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) { 549 err = pcxhr_set_format(stream); 550 err = pcxhr_update_r_buffer(stream); 551 } 552 } 553 for (j = 0; j < chip->nb_streams_play; j++) { 554 stream = &chip->playback_stream[j]; 555 if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) { 556 err = pcxhr_set_format(stream); 557 err = pcxhr_update_r_buffer(stream); 558 } 559 } 560 } 561 /* start all the streams */ 562 for (i = 0; i < mgr->num_cards; i++) { 563 struct pcxhr_stream *stream; 564 chip = mgr->chip[i]; 565 for (j = 0; j < chip->nb_streams_capt; j++) { 566 stream = &chip->capture_stream[j]; 567 if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) 568 err = pcxhr_set_stream_state(stream); 569 } 570 for (j = 0; j < chip->nb_streams_play; j++) { 571 stream = &chip->playback_stream[j]; 572 if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) 573 err = pcxhr_set_stream_state(stream); 574 } 575 } 576 577 /* synchronous start of all the pipes concerned */ 578 err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 1); 579 if (err) { 580 mutex_unlock(&mgr->setup_mutex); 581 snd_printk(KERN_ERR "pcxhr_trigger_tasklet : error start pipes (P%x C%x)\n", 582 playback_mask, capture_mask); 583 return; 584 } 585 586 /* put the streams into the running state now (increment pointer by interrupt) */ 587 spin_lock_irqsave(&mgr->lock, flags); 588 for ( i =0; i < mgr->num_cards; i++) { 589 struct pcxhr_stream *stream; 590 chip = mgr->chip[i]; 591 for(j = 0; j < chip->nb_streams_capt; j++) { 592 stream = &chip->capture_stream[j]; 593 if(stream->status == PCXHR_STREAM_STATUS_STARTED) 594 stream->status = PCXHR_STREAM_STATUS_RUNNING; 595 } 596 for (j = 0; j < chip->nb_streams_play; j++) { 597 stream = &chip->playback_stream[j]; 598 if (stream->status == PCXHR_STREAM_STATUS_STARTED) { 599 /* playback will already have advanced ! */ 600 stream->timer_period_frag += PCXHR_GRANULARITY; 601 stream->status = PCXHR_STREAM_STATUS_RUNNING; 602 } 603 } 604 } 605 spin_unlock_irqrestore(&mgr->lock, flags); 606 607 mutex_unlock(&mgr->setup_mutex); 608 609#ifdef CONFIG_SND_DEBUG_DETECT 610 do_gettimeofday(&my_tv2); 611 snd_printdd("***TRIGGER TASKLET*** TIME = %ld (err = %x)\n", 612 my_tv2.tv_usec - my_tv1.tv_usec, err); 613#endif 614} 615 616 617/* 618 * trigger callback 619 */ 620static int pcxhr_trigger(struct snd_pcm_substream *subs, int cmd) 621{ 622 struct pcxhr_stream *stream; 623 struct snd_pcm_substream *s; 624 625 switch (cmd) { 626 case SNDRV_PCM_TRIGGER_START: 627 snd_printdd("SNDRV_PCM_TRIGGER_START\n"); 628 if (snd_pcm_stream_linked(subs)) { 629 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs); 630 snd_pcm_group_for_each_entry(s, subs) { 631 stream = s->runtime->private_data; 632 stream->status = 633 PCXHR_STREAM_STATUS_SCHEDULE_RUN; 634 snd_pcm_trigger_done(s, subs); 635 } 636 tasklet_hi_schedule(&chip->mgr->trigger_taskq); 637 } else { 638 stream = subs->runtime->private_data; 639 snd_printdd("Only one Substream %c %d\n", 640 stream->pipe->is_capture ? 'C' : 'P', 641 stream->pipe->first_audio); 642 if (pcxhr_set_format(stream)) 643 return -EINVAL; 644 if (pcxhr_update_r_buffer(stream)) 645 return -EINVAL; 646 647 if (pcxhr_set_stream_state(stream)) 648 return -EINVAL; 649 stream->status = PCXHR_STREAM_STATUS_RUNNING; 650 } 651 break; 652 case SNDRV_PCM_TRIGGER_STOP: 653 snd_printdd("SNDRV_PCM_TRIGGER_STOP\n"); 654 snd_pcm_group_for_each_entry(s, subs) { 655 stream = s->runtime->private_data; 656 stream->status = PCXHR_STREAM_STATUS_SCHEDULE_STOP; 657 if (pcxhr_set_stream_state(stream)) 658 return -EINVAL; 659 snd_pcm_trigger_done(s, subs); 660 } 661 break; 662 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 663 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 664 /* TODO */ 665 default: 666 return -EINVAL; 667 } 668 return 0; 669} 670 671 672static int pcxhr_hardware_timer(struct pcxhr_mgr *mgr, int start) 673{ 674 struct pcxhr_rmh rmh; 675 int err; 676 677 pcxhr_init_rmh(&rmh, CMD_SET_TIMER_INTERRUPT); 678 if (start) { 679 mgr->dsp_time_last = PCXHR_DSP_TIME_INVALID; /* last dsp time invalid */ 680 rmh.cmd[0] |= PCXHR_GRANULARITY; 681 } 682 err = pcxhr_send_msg(mgr, &rmh); 683 if (err < 0) 684 snd_printk(KERN_ERR "error pcxhr_hardware_timer err(%x)\n", err); 685 return err; 686} 687 688/* 689 * prepare callback for all pcms 690 */ 691static int pcxhr_prepare(struct snd_pcm_substream *subs) 692{ 693 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs); 694 struct pcxhr_mgr *mgr = chip->mgr; 695 /* 696 struct pcxhr_stream *stream = (pcxhr_stream_t*)subs->runtime->private_data; 697 */ 698 int err = 0; 699 700 snd_printdd("pcxhr_prepare : period_size(%lx) periods(%x) buffer_size(%lx)\n", 701 subs->runtime->period_size, subs->runtime->periods, 702 subs->runtime->buffer_size); 703 704 /* 705 if(subs->runtime->period_size <= PCXHR_GRANULARITY) { 706 snd_printk(KERN_ERR "pcxhr_prepare : error period_size too small (%x)\n", 707 (unsigned int)subs->runtime->period_size); 708 return -EINVAL; 709 } 710 */ 711 712 mutex_lock(&mgr->setup_mutex); 713 714 do { 715 /* if the stream was stopped before, format and buffer were reset */ 716 /* 717 if(stream->status == PCXHR_STREAM_STATUS_STOPPED) { 718 err = pcxhr_set_format(stream); 719 if(err) break; 720 err = pcxhr_update_r_buffer(stream); 721 if(err) break; 722 } 723 */ 724 725 /* only the first stream can choose the sample rate */ 726 /* the further opened streams will be limited to its frequency (see open) */ 727 /* set the clock only once (first stream) */ 728 if (mgr->sample_rate != subs->runtime->rate) { 729 err = pcxhr_set_clock(mgr, subs->runtime->rate); 730 if (err) 731 break; 732 if (mgr->sample_rate == 0) 733 /* start the DSP-timer */ 734 err = pcxhr_hardware_timer(mgr, 1); 735 mgr->sample_rate = subs->runtime->rate; 736 } 737 } while(0); /* do only once (so we can use break instead of goto) */ 738 739 mutex_unlock(&mgr->setup_mutex); 740 741 return err; 742} 743 744 745/* 746 * HW_PARAMS callback for all pcms 747 */ 748static int pcxhr_hw_params(struct snd_pcm_substream *subs, 749 struct snd_pcm_hw_params *hw) 750{ 751 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs); 752 struct pcxhr_mgr *mgr = chip->mgr; 753 struct pcxhr_stream *stream = subs->runtime->private_data; 754 snd_pcm_format_t format; 755 int err; 756 int channels; 757 758 /* set up channels */ 759 channels = params_channels(hw); 760 761 /* set up format for the stream */ 762 format = params_format(hw); 763 764 mutex_lock(&mgr->setup_mutex); 765 766 stream->channels = channels; 767 stream->format = format; 768 769 /* set the format to the board */ 770 /* 771 err = pcxhr_set_format(stream); 772 if(err) { 773 mutex_unlock(&mgr->setup_mutex); 774 return err; 775 } 776 */ 777 /* allocate buffer */ 778 err = snd_pcm_lib_malloc_pages(subs, params_buffer_bytes(hw)); 779 780 /* 781 if (err > 0) { 782 err = pcxhr_update_r_buffer(stream); 783 } 784 */ 785 mutex_unlock(&mgr->setup_mutex); 786 787 return err; 788} 789 790static int pcxhr_hw_free(struct snd_pcm_substream *subs) 791{ 792 snd_pcm_lib_free_pages(subs); 793 return 0; 794} 795 796 797/* 798 * CONFIGURATION SPACE for all pcms, mono pcm must update channels_max 799 */ 800static struct snd_pcm_hardware pcxhr_caps = 801{ 802 .info = ( SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 803 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START | 804 0 /*SNDRV_PCM_INFO_PAUSE*/), 805 .formats = ( SNDRV_PCM_FMTBIT_U8 | 806 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE | 807 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_3BE | 808 SNDRV_PCM_FMTBIT_FLOAT_LE ), 809 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_192000, 810 .rate_min = 8000, 811 .rate_max = 192000, 812 .channels_min = 1, 813 .channels_max = 2, 814 .buffer_bytes_max = (32*1024), 815 /* 1 byte == 1 frame U8 mono (PCXHR_GRANULARITY is frames!) */ 816 .period_bytes_min = (2*PCXHR_GRANULARITY), 817 .period_bytes_max = (16*1024), 818 .periods_min = 2, 819 .periods_max = (32*1024/PCXHR_GRANULARITY), 820}; 821 822 823static int pcxhr_open(struct snd_pcm_substream *subs) 824{ 825 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs); 826 struct pcxhr_mgr *mgr = chip->mgr; 827 struct snd_pcm_runtime *runtime = subs->runtime; 828 struct pcxhr_stream *stream; 829 int is_capture; 830 831 mutex_lock(&mgr->setup_mutex); 832 833 /* copy the struct snd_pcm_hardware struct */ 834 runtime->hw = pcxhr_caps; 835 836 if( subs->stream == SNDRV_PCM_STREAM_PLAYBACK ) { 837 snd_printdd("pcxhr_open playback chip%d subs%d\n", 838 chip->chip_idx, subs->number); 839 is_capture = 0; 840 stream = &chip->playback_stream[subs->number]; 841 } else { 842 snd_printdd("pcxhr_open capture chip%d subs%d\n", 843 chip->chip_idx, subs->number); 844 is_capture = 1; 845 if (mgr->mono_capture) 846 runtime->hw.channels_max = 1; 847 else 848 runtime->hw.channels_min = 2; 849 stream = &chip->capture_stream[subs->number]; 850 } 851 if (stream->status != PCXHR_STREAM_STATUS_FREE){ 852 /* streams in use */ 853 snd_printk(KERN_ERR "pcxhr_open chip%d subs%d in use\n", 854 chip->chip_idx, subs->number); 855 mutex_unlock(&mgr->setup_mutex); 856 return -EBUSY; 857 } 858 859 /* if a sample rate is already used or fixed by external clock, 860 * the stream cannot change 861 */ 862 if (mgr->sample_rate) 863 runtime->hw.rate_min = runtime->hw.rate_max = mgr->sample_rate; 864 else { 865 if (mgr->use_clock_type != PCXHR_CLOCK_TYPE_INTERNAL) { 866 int external_rate; 867 if (pcxhr_get_external_clock(mgr, mgr->use_clock_type, 868 &external_rate) || 869 external_rate == 0) { 870 /* cannot detect the external clock rate */ 871 mutex_unlock(&mgr->setup_mutex); 872 return -EBUSY; 873 } 874 runtime->hw.rate_min = runtime->hw.rate_max = external_rate; 875 } 876 } 877 878 stream->status = PCXHR_STREAM_STATUS_OPEN; 879 stream->substream = subs; 880 stream->channels = 0; /* not configured yet */ 881 882 runtime->private_data = stream; 883 884 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 4); 885 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 4); 886 887 mgr->ref_count_rate++; 888 889 mutex_unlock(&mgr->setup_mutex); 890 return 0; 891} 892 893 894static int pcxhr_close(struct snd_pcm_substream *subs) 895{ 896 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs); 897 struct pcxhr_mgr *mgr = chip->mgr; 898 struct pcxhr_stream *stream = subs->runtime->private_data; 899 900 mutex_lock(&mgr->setup_mutex); 901 902 snd_printdd("pcxhr_close chip%d subs%d\n", chip->chip_idx, subs->number); 903 904 /* sample rate released */ 905 if (--mgr->ref_count_rate == 0) { 906 mgr->sample_rate = 0; /* the sample rate is no more locked */ 907 pcxhr_hardware_timer(mgr, 0); /* stop the DSP-timer */ 908 } 909 910 stream->status = PCXHR_STREAM_STATUS_FREE; 911 stream->substream = NULL; 912 913 mutex_unlock(&mgr->setup_mutex); 914 915 return 0; 916} 917 918 919static snd_pcm_uframes_t pcxhr_stream_pointer(struct snd_pcm_substream *subs) 920{ 921 unsigned long flags; 922 u_int32_t timer_period_frag; 923 int timer_buf_periods; 924 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs); 925 struct snd_pcm_runtime *runtime = subs->runtime; 926 struct pcxhr_stream *stream = runtime->private_data; 927 928 spin_lock_irqsave(&chip->mgr->lock, flags); 929 930 /* get the period fragment and the nb of periods in the buffer */ 931 timer_period_frag = stream->timer_period_frag; 932 timer_buf_periods = stream->timer_buf_periods; 933 934 spin_unlock_irqrestore(&chip->mgr->lock, flags); 935 936 return (snd_pcm_uframes_t)((timer_buf_periods * runtime->period_size) + 937 timer_period_frag); 938} 939 940 941static struct snd_pcm_ops pcxhr_ops = { 942 .open = pcxhr_open, 943 .close = pcxhr_close, 944 .ioctl = snd_pcm_lib_ioctl, 945 .prepare = pcxhr_prepare, 946 .hw_params = pcxhr_hw_params, 947 .hw_free = pcxhr_hw_free, 948 .trigger = pcxhr_trigger, 949 .pointer = pcxhr_stream_pointer, 950}; 951 952/* 953 */ 954int pcxhr_create_pcm(struct snd_pcxhr *chip) 955{ 956 int err; 957 struct snd_pcm *pcm; 958 char name[32]; 959 960 sprintf(name, "pcxhr %d", chip->chip_idx); 961 if ((err = snd_pcm_new(chip->card, name, 0, 962 chip->nb_streams_play, 963 chip->nb_streams_capt, &pcm)) < 0) { 964 snd_printk(KERN_ERR "cannot create pcm %s\n", name); 965 return err; 966 } 967 pcm->private_data = chip; 968 969 if (chip->nb_streams_play) 970 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &pcxhr_ops); 971 if (chip->nb_streams_capt) 972 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &pcxhr_ops); 973 974 pcm->info_flags = 0; 975 strcpy(pcm->name, name); 976 977 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 978 snd_dma_pci_data(chip->mgr->pci), 979 32*1024, 32*1024); 980 chip->pcm = pcm; 981 return 0; 982} 983 984static int pcxhr_chip_free(struct snd_pcxhr *chip) 985{ 986 kfree(chip); 987 return 0; 988} 989 990static int pcxhr_chip_dev_free(struct snd_device *device) 991{ 992 struct snd_pcxhr *chip = device->device_data; 993 return pcxhr_chip_free(chip); 994} 995 996 997/* 998 */ 999static int __devinit pcxhr_create(struct pcxhr_mgr *mgr, struct snd_card *card, int idx) 1000{ 1001 int err; 1002 struct snd_pcxhr *chip; 1003 static struct snd_device_ops ops = { 1004 .dev_free = pcxhr_chip_dev_free, 1005 }; 1006 1007 mgr->chip[idx] = chip = kzalloc(sizeof(*chip), GFP_KERNEL); 1008 if (! chip) { 1009 snd_printk(KERN_ERR "cannot allocate chip\n"); 1010 return -ENOMEM; 1011 } 1012 1013 chip->card = card; 1014 chip->chip_idx = idx; 1015 chip->mgr = mgr; 1016 1017 if (idx < mgr->playback_chips) 1018 /* stereo or mono streams */ 1019 chip->nb_streams_play = PCXHR_PLAYBACK_STREAMS; 1020 1021 if (idx < mgr->capture_chips) { 1022 if (mgr->mono_capture) 1023 chip->nb_streams_capt = 2; /* 2 mono streams (left+right) */ 1024 else 1025 chip->nb_streams_capt = 1; /* or 1 stereo stream */ 1026 } 1027 1028 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { 1029 pcxhr_chip_free(chip); 1030 return err; 1031 } 1032 1033 snd_card_set_dev(card, &mgr->pci->dev); 1034 1035 return 0; 1036} 1037 1038/* proc interface */ 1039static void pcxhr_proc_info(struct snd_info_entry *entry, struct snd_info_buffer *buffer) 1040{ 1041 struct snd_pcxhr *chip = entry->private_data; 1042 struct pcxhr_mgr *mgr = chip->mgr; 1043 1044 snd_iprintf(buffer, "\n%s\n", mgr->longname); 1045 1046 /* stats available when embedded DSP is running */ 1047 if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) { 1048 struct pcxhr_rmh rmh; 1049 short ver_maj = (mgr->dsp_version >> 16) & 0xff; 1050 short ver_min = (mgr->dsp_version >> 8) & 0xff; 1051 short ver_build = mgr->dsp_version & 0xff; 1052 snd_iprintf(buffer, "module version %s\n", PCXHR_DRIVER_VERSION_STRING); 1053 snd_iprintf(buffer, "dsp version %d.%d.%d\n", ver_maj, ver_min, ver_build); 1054 if (mgr->board_has_analog) 1055 snd_iprintf(buffer, "analog io available\n"); 1056 else 1057 snd_iprintf(buffer, "digital only board\n"); 1058 1059 /* calc cpu load of the dsp */ 1060 pcxhr_init_rmh(&rmh, CMD_GET_DSP_RESOURCES); 1061 if( ! pcxhr_send_msg(mgr, &rmh) ) { 1062 int cur = rmh.stat[0]; 1063 int ref = rmh.stat[1]; 1064 if (ref > 0) { 1065 if (mgr->sample_rate_real != 0 && 1066 mgr->sample_rate_real != 48000) { 1067 ref = (ref * 48000) / mgr->sample_rate_real; 1068 if (mgr->sample_rate_real >= PCXHR_IRQ_TIMER_FREQ) 1069 ref *= 2; 1070 } 1071 cur = 100 - (100 * cur) / ref; 1072 snd_iprintf(buffer, "cpu load %d%%\n", cur); 1073 snd_iprintf(buffer, "buffer pool %d/%d kWords\n", 1074 rmh.stat[2], rmh.stat[3]); 1075 } 1076 } 1077 snd_iprintf(buffer, "dma granularity : %d\n", PCXHR_GRANULARITY); 1078 snd_iprintf(buffer, "dsp time errors : %d\n", mgr->dsp_time_err); 1079 snd_iprintf(buffer, "dsp async pipe xrun errors : %d\n", 1080 mgr->async_err_pipe_xrun); 1081 snd_iprintf(buffer, "dsp async stream xrun errors : %d\n", 1082 mgr->async_err_stream_xrun); 1083 snd_iprintf(buffer, "dsp async last other error : %x\n", 1084 mgr->async_err_other_last); 1085 /* debug zone dsp */ 1086 rmh.cmd[0] = 0x4200 + PCXHR_SIZE_MAX_STATUS; 1087 rmh.cmd_len = 1; 1088 rmh.stat_len = PCXHR_SIZE_MAX_STATUS; 1089 rmh.dsp_stat = 0; 1090 rmh.cmd_idx = CMD_LAST_INDEX; 1091 if( ! pcxhr_send_msg(mgr, &rmh) ) { 1092 int i; 1093 for (i = 0; i < rmh.stat_len; i++) 1094 snd_iprintf(buffer, "debug[%02d] = %06x\n", i, rmh.stat[i]); 1095 } 1096 } else 1097 snd_iprintf(buffer, "no firmware loaded\n"); 1098 snd_iprintf(buffer, "\n"); 1099} 1100static void pcxhr_proc_sync(struct snd_info_entry *entry, struct snd_info_buffer *buffer) 1101{ 1102 struct snd_pcxhr *chip = entry->private_data; 1103 struct pcxhr_mgr *mgr = chip->mgr; 1104 static char *texts[7] = { 1105 "Internal", "Word", "AES Sync", "AES 1", "AES 2", "AES 3", "AES 4" 1106 }; 1107 1108 snd_iprintf(buffer, "\n%s\n", mgr->longname); 1109 snd_iprintf(buffer, "Current Sample Clock\t: %s\n", texts[mgr->cur_clock_type]); 1110 snd_iprintf(buffer, "Current Sample Rate\t= %d\n", mgr->sample_rate_real); 1111 1112 /* commands available when embedded DSP is running */ 1113 if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) { 1114 int i, err, sample_rate; 1115 for (i = PCXHR_CLOCK_TYPE_WORD_CLOCK; i< (3 + mgr->capture_chips); i++) { 1116 err = pcxhr_get_external_clock(mgr, i, &sample_rate); 1117 if (err) 1118 break; 1119 snd_iprintf(buffer, "%s Clock\t\t= %d\n", texts[i], sample_rate); 1120 } 1121 } else 1122 snd_iprintf(buffer, "no firmware loaded\n"); 1123 snd_iprintf(buffer, "\n"); 1124} 1125 1126static void __devinit pcxhr_proc_init(struct snd_pcxhr *chip) 1127{ 1128 struct snd_info_entry *entry; 1129 1130 if (! snd_card_proc_new(chip->card, "info", &entry)) 1131 snd_info_set_text_ops(entry, chip, pcxhr_proc_info); 1132 if (! snd_card_proc_new(chip->card, "sync", &entry)) 1133 snd_info_set_text_ops(entry, chip, pcxhr_proc_sync); 1134} 1135/* end of proc interface */ 1136 1137/* 1138 * release all the cards assigned to a manager instance 1139 */ 1140static int pcxhr_free(struct pcxhr_mgr *mgr) 1141{ 1142 unsigned int i; 1143 1144 for (i = 0; i < mgr->num_cards; i++) { 1145 if (mgr->chip[i]) 1146 snd_card_free(mgr->chip[i]->card); 1147 } 1148 1149 /* reset board if some firmware was loaded */ 1150 if(mgr->dsp_loaded) { 1151 pcxhr_reset_board(mgr); 1152 snd_printdd("reset pcxhr !\n"); 1153 } 1154 1155 /* release irq */ 1156 if (mgr->irq >= 0) 1157 free_irq(mgr->irq, mgr); 1158 1159 pci_release_regions(mgr->pci); 1160 1161 /* free hostport purgebuffer */ 1162 if (mgr->hostport.area) { 1163 snd_dma_free_pages(&mgr->hostport); 1164 mgr->hostport.area = NULL; 1165 } 1166 1167 kfree(mgr->prmh); 1168 1169 pci_disable_device(mgr->pci); 1170 kfree(mgr); 1171 return 0; 1172} 1173 1174/* 1175 * probe function - creates the card manager 1176 */ 1177static int __devinit pcxhr_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) 1178{ 1179 static int dev; 1180 struct pcxhr_mgr *mgr; 1181 unsigned int i; 1182 int err; 1183 size_t size; 1184 char *card_name; 1185 1186 if (dev >= SNDRV_CARDS) 1187 return -ENODEV; 1188 if (! enable[dev]) { 1189 dev++; 1190 return -ENOENT; 1191 } 1192 1193 /* enable PCI device */ 1194 if ((err = pci_enable_device(pci)) < 0) 1195 return err; 1196 pci_set_master(pci); 1197 1198 /* check if we can restrict PCI DMA transfers to 32 bits */ 1199 if (pci_set_dma_mask(pci, DMA_32BIT_MASK) < 0) { 1200 snd_printk(KERN_ERR "architecture does not support 32bit PCI busmaster DMA\n"); 1201 pci_disable_device(pci); 1202 return -ENXIO; 1203 } 1204 1205 /* alloc card manager */ 1206 mgr = kzalloc(sizeof(*mgr), GFP_KERNEL); 1207 if (! mgr) { 1208 pci_disable_device(pci); 1209 return -ENOMEM; 1210 } 1211 1212 snd_assert(pci_id->driver_data < PCI_ID_LAST, return -ENODEV); 1213 card_name = pcxhr_board_params[pci_id->driver_data].board_name; 1214 mgr->playback_chips = pcxhr_board_params[pci_id->driver_data].playback_chips; 1215 mgr->capture_chips = pcxhr_board_params[pci_id->driver_data].capture_chips; 1216 mgr->firmware_num = pcxhr_board_params[pci_id->driver_data].firmware_num; 1217 mgr->mono_capture = mono[dev]; 1218 1219 /* resource assignment */ 1220 if ((err = pci_request_regions(pci, card_name)) < 0) { 1221 kfree(mgr); 1222 pci_disable_device(pci); 1223 return err; 1224 } 1225 for (i = 0; i < 3; i++) 1226 mgr->port[i] = pci_resource_start(pci, i); 1227 1228 mgr->pci = pci; 1229 mgr->irq = -1; 1230 1231 if (request_irq(pci->irq, pcxhr_interrupt, IRQF_SHARED, 1232 card_name, mgr)) { 1233 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); 1234 pcxhr_free(mgr); 1235 return -EBUSY; 1236 } 1237 mgr->irq = pci->irq; 1238 1239 sprintf(mgr->shortname, "Digigram %s", card_name); 1240 sprintf(mgr->longname, "%s at 0x%lx & 0x%lx, 0x%lx irq %i", mgr->shortname, 1241 mgr->port[0], mgr->port[1], mgr->port[2], mgr->irq); 1242 1243 /* ISR spinlock */ 1244 spin_lock_init(&mgr->lock); 1245 spin_lock_init(&mgr->msg_lock); 1246 1247 /* init setup mutex*/ 1248 mutex_init(&mgr->setup_mutex); 1249 1250 /* init taslket */ 1251 tasklet_init(&mgr->msg_taskq, pcxhr_msg_tasklet, (unsigned long) mgr); 1252 tasklet_init(&mgr->trigger_taskq, pcxhr_trigger_tasklet, (unsigned long) mgr); 1253 mgr->prmh = kmalloc(sizeof(*mgr->prmh) + 1254 sizeof(u32) * (PCXHR_SIZE_MAX_LONG_STATUS - PCXHR_SIZE_MAX_STATUS), 1255 GFP_KERNEL); 1256 if (! mgr->prmh) { 1257 pcxhr_free(mgr); 1258 return -ENOMEM; 1259 } 1260 1261 for (i=0; i < PCXHR_MAX_CARDS; i++) { 1262 struct snd_card *card; 1263 char tmpid[16]; 1264 int idx; 1265 1266 if (i >= max(mgr->playback_chips, mgr->capture_chips)) 1267 break; 1268 mgr->num_cards++; 1269 1270 if (index[dev] < 0) 1271 idx = index[dev]; 1272 else 1273 idx = index[dev] + i; 1274 1275 snprintf(tmpid, sizeof(tmpid), "%s-%d", id[dev] ? id[dev] : card_name, i); 1276 card = snd_card_new(idx, tmpid, THIS_MODULE, 0); 1277 1278 if (! card) { 1279 snd_printk(KERN_ERR "cannot allocate the card %d\n", i); 1280 pcxhr_free(mgr); 1281 return -ENOMEM; 1282 } 1283 1284 strcpy(card->driver, DRIVER_NAME); 1285 sprintf(card->shortname, "%s [PCM #%d]", mgr->shortname, i); 1286 sprintf(card->longname, "%s [PCM #%d]", mgr->longname, i); 1287 1288 if ((err = pcxhr_create(mgr, card, i)) < 0) { 1289 pcxhr_free(mgr); 1290 return err; 1291 } 1292 1293 if (i == 0) 1294 /* init proc interface only for chip0 */ 1295 pcxhr_proc_init(mgr->chip[i]); 1296 1297 if ((err = snd_card_register(card)) < 0) { 1298 pcxhr_free(mgr); 1299 return err; 1300 } 1301 } 1302 1303 /* create hostport purgebuffer */ 1304 size = PAGE_ALIGN(sizeof(struct pcxhr_hostport)); 1305 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci), 1306 size, &mgr->hostport) < 0) { 1307 pcxhr_free(mgr); 1308 return -ENOMEM; 1309 } 1310 /* init purgebuffer */ 1311 memset(mgr->hostport.area, 0, size); 1312 1313 /* create a DSP loader */ 1314 err = pcxhr_setup_firmware(mgr); 1315 if (err < 0) { 1316 pcxhr_free(mgr); 1317 return err; 1318 } 1319 1320 pci_set_drvdata(pci, mgr); 1321 dev++; 1322 return 0; 1323} 1324 1325static void __devexit pcxhr_remove(struct pci_dev *pci) 1326{ 1327 pcxhr_free(pci_get_drvdata(pci)); 1328 pci_set_drvdata(pci, NULL); 1329} 1330 1331static struct pci_driver driver = { 1332 .name = "Digigram pcxhr", 1333 .id_table = pcxhr_ids, 1334 .probe = pcxhr_probe, 1335 .remove = __devexit_p(pcxhr_remove), 1336}; 1337 1338static int __init pcxhr_module_init(void) 1339{ 1340 return pci_register_driver(&driver); 1341} 1342 1343static void __exit pcxhr_module_exit(void) 1344{ 1345 pci_unregister_driver(&driver); 1346} 1347 1348module_init(pcxhr_module_init) 1349module_exit(pcxhr_module_exit) 1350