1/* 2 * Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard 3 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>, 4 * Thomas Sailer <sailer@ife.ee.ethz.ch> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 * 20 */ 21 22 23#include <sound/driver.h> 24#include <asm/io.h> 25#include <linux/delay.h> 26#include <linux/interrupt.h> 27#include <linux/init.h> 28#include <linux/pci.h> 29#include <linux/slab.h> 30#include <linux/gameport.h> 31#include <linux/moduleparam.h> 32#include <linux/mutex.h> 33 34#include <sound/core.h> 35#include <sound/control.h> 36#include <sound/pcm.h> 37#include <sound/rawmidi.h> 38#ifdef CHIP1371 39#include <sound/ac97_codec.h> 40#else 41#include <sound/ak4531_codec.h> 42#endif 43#include <sound/initval.h> 44#include <sound/asoundef.h> 45 46#ifndef CHIP1371 47#undef CHIP1370 48#define CHIP1370 49#endif 50 51#ifdef CHIP1370 52#define DRIVER_NAME "ENS1370" 53#else 54#define DRIVER_NAME "ENS1371" 55#endif 56 57 58MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>, Thomas Sailer <sailer@ife.ee.ethz.ch>"); 59MODULE_LICENSE("GPL"); 60#ifdef CHIP1370 61MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370"); 62MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI-97 ES1370}," 63 "{Creative Labs,SB PCI64/128 (ES1370)}}"); 64#endif 65#ifdef CHIP1371 66MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+"); 67MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI ES1371/73}," 68 "{Ensoniq,AudioPCI ES1373}," 69 "{Creative Labs,Ectiva EV1938}," 70 "{Creative Labs,SB PCI64/128 (ES1371/73)}," 71 "{Creative Labs,Vibra PCI128}," 72 "{Ectiva,EV1938}}"); 73#endif 74 75#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE)) 76#define SUPPORT_JOYSTICK 77#endif 78 79static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 80static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 81static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */ 82#ifdef SUPPORT_JOYSTICK 83#ifdef CHIP1371 84static int joystick_port[SNDRV_CARDS]; 85#else 86static int joystick[SNDRV_CARDS]; 87#endif 88#endif 89#ifdef CHIP1371 90static int spdif[SNDRV_CARDS]; 91static int lineio[SNDRV_CARDS]; 92#endif 93 94module_param_array(index, int, NULL, 0444); 95MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard."); 96module_param_array(id, charp, NULL, 0444); 97MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard."); 98module_param_array(enable, bool, NULL, 0444); 99MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard."); 100#ifdef SUPPORT_JOYSTICK 101#ifdef CHIP1371 102module_param_array(joystick_port, int, NULL, 0444); 103MODULE_PARM_DESC(joystick_port, "Joystick port address."); 104#else 105module_param_array(joystick, bool, NULL, 0444); 106MODULE_PARM_DESC(joystick, "Enable joystick."); 107#endif 108#endif /* SUPPORT_JOYSTICK */ 109#ifdef CHIP1371 110module_param_array(spdif, int, NULL, 0444); 111MODULE_PARM_DESC(spdif, "S/PDIF output (-1 = none, 0 = auto, 1 = force)."); 112module_param_array(lineio, int, NULL, 0444); 113MODULE_PARM_DESC(lineio, "Line In to Rear Out (0 = auto, 1 = force)."); 114#endif 115 116/* ES1371 chip ID */ 117/* This is a little confusing because all ES1371 compatible chips have the 118 same DEVICE_ID, the only thing differentiating them is the REV_ID field. 119 This is only significant if you want to enable features on the later parts. 120 Yes, I know it's stupid and why didn't we use the sub IDs? 121*/ 122#define ES1371REV_ES1373_A 0x04 123#define ES1371REV_ES1373_B 0x06 124#define ES1371REV_CT5880_A 0x07 125#define CT5880REV_CT5880_C 0x02 126#define CT5880REV_CT5880_D 0x03 /* ??? -jk */ 127#define CT5880REV_CT5880_E 0x04 /* mw */ 128#define ES1371REV_ES1371_B 0x09 129#define EV1938REV_EV1938_A 0x00 130#define ES1371REV_ES1373_8 0x08 131 132/* 133 * Direct registers 134 */ 135 136#define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x) 137 138#define ES_REG_CONTROL 0x00 /* R/W: Interrupt/Chip select control register */ 139#define ES_1370_ADC_STOP (1<<31) /* disable capture buffer transfers */ 140#define ES_1370_XCTL1 (1<<30) /* general purpose output bit */ 141#define ES_1373_BYPASS_P1 (1<<31) /* bypass SRC for PB1 */ 142#define ES_1373_BYPASS_P2 (1<<30) /* bypass SRC for PB2 */ 143#define ES_1373_BYPASS_R (1<<29) /* bypass SRC for REC */ 144#define ES_1373_TEST_BIT (1<<28) /* should be set to 0 for normal operation */ 145#define ES_1373_RECEN_B (1<<27) /* mix record with playback for I2S/SPDIF out */ 146#define ES_1373_SPDIF_THRU (1<<26) /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */ 147#define ES_1371_JOY_ASEL(o) (((o)&0x03)<<24)/* joystick port mapping */ 148#define ES_1371_JOY_ASELM (0x03<<24) /* mask for above */ 149#define ES_1371_JOY_ASELI(i) (((i)>>24)&0x03) 150#define ES_1371_GPIO_IN(i) (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */ 151#define ES_1370_PCLKDIVO(o) (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */ 152#define ES_1370_PCLKDIVM ((0x1fff)<<16) /* mask for above */ 153#define ES_1370_PCLKDIVI(i) (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */ 154#define ES_1371_GPIO_OUT(o) (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */ 155#define ES_1371_GPIO_OUTM (0x0f<<16) /* mask for above */ 156#define ES_MSFMTSEL (1<<15) /* MPEG serial data format; 0 = SONY, 1 = I2S */ 157#define ES_1370_M_SBB (1<<14) /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */ 158#define ES_1371_SYNC_RES (1<<14) /* Warm AC97 reset */ 159#define ES_1370_WTSRSEL(o) (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */ 160#define ES_1370_WTSRSELM (0x03<<12) /* mask for above */ 161#define ES_1371_ADC_STOP (1<<13) /* disable CCB transfer capture information */ 162#define ES_1371_PWR_INTRM (1<<12) /* power level change interrupts enable */ 163#define ES_1370_DAC_SYNC (1<<11) /* DAC's are synchronous */ 164#define ES_1371_M_CB (1<<11) /* capture clock source; 0 = AC'97 ADC; 1 = I2S */ 165#define ES_CCB_INTRM (1<<10) /* CCB voice interrupts enable */ 166#define ES_1370_M_CB (1<<9) /* capture clock source; 0 = ADC; 1 = MPEG */ 167#define ES_1370_XCTL0 (1<<8) /* generap purpose output bit */ 168#define ES_1371_PDLEV(o) (((o)&0x03)<<8) /* current power down level */ 169#define ES_1371_PDLEVM (0x03<<8) /* mask for above */ 170#define ES_BREQ (1<<7) /* memory bus request enable */ 171#define ES_DAC1_EN (1<<6) /* DAC1 playback channel enable */ 172#define ES_DAC2_EN (1<<5) /* DAC2 playback channel enable */ 173#define ES_ADC_EN (1<<4) /* ADC capture channel enable */ 174#define ES_UART_EN (1<<3) /* UART enable */ 175#define ES_JYSTK_EN (1<<2) /* Joystick module enable */ 176#define ES_1370_CDC_EN (1<<1) /* Codec interface enable */ 177#define ES_1371_XTALCKDIS (1<<1) /* Xtal clock disable */ 178#define ES_1370_SERR_DISABLE (1<<0) /* PCI serr signal disable */ 179#define ES_1371_PCICLKDIS (1<<0) /* PCI clock disable */ 180#define ES_REG_STATUS 0x04 /* R/O: Interrupt/Chip select status register */ 181#define ES_INTR (1<<31) /* Interrupt is pending */ 182#define ES_1371_ST_AC97_RST (1<<29) /* CT5880 AC'97 Reset bit */ 183#define ES_1373_REAR_BIT27 (1<<27) /* rear bits: 000 - front, 010 - mirror, 101 - separate */ 184#define ES_1373_REAR_BIT26 (1<<26) 185#define ES_1373_REAR_BIT24 (1<<24) 186#define ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */ 187#define ES_1373_SPDIF_EN (1<<18) /* SPDIF enable */ 188#define ES_1373_SPDIF_TEST (1<<17) /* SPDIF test */ 189#define ES_1371_TEST (1<<16) /* test ASIC */ 190#define ES_1373_GPIO_INT(i) (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */ 191#define ES_1370_CSTAT (1<<10) /* CODEC is busy or register write in progress */ 192#define ES_1370_CBUSY (1<<9) /* CODEC is busy */ 193#define ES_1370_CWRIP (1<<8) /* CODEC register write in progress */ 194#define ES_1371_SYNC_ERR (1<<8) /* CODEC synchronization error occurred */ 195#define ES_1371_VC(i) (((i)>>6)&0x03) /* voice code from CCB module */ 196#define ES_1370_VC(i) (((i)>>5)&0x03) /* voice code from CCB module */ 197#define ES_1371_MPWR (1<<5) /* power level interrupt pending */ 198#define ES_MCCB (1<<4) /* CCB interrupt pending */ 199#define ES_UART (1<<3) /* UART interrupt pending */ 200#define ES_DAC1 (1<<2) /* DAC1 channel interrupt pending */ 201#define ES_DAC2 (1<<1) /* DAC2 channel interrupt pending */ 202#define ES_ADC (1<<0) /* ADC channel interrupt pending */ 203#define ES_REG_UART_DATA 0x08 /* R/W: UART data register */ 204#define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */ 205#define ES_RXINT (1<<7) /* RX interrupt occurred */ 206#define ES_TXINT (1<<2) /* TX interrupt occurred */ 207#define ES_TXRDY (1<<1) /* transmitter ready */ 208#define ES_RXRDY (1<<0) /* receiver ready */ 209#define ES_REG_UART_CONTROL 0x09 /* W/O: UART control register */ 210#define ES_RXINTEN (1<<7) /* RX interrupt enable */ 211#define ES_TXINTENO(o) (((o)&0x03)<<5) /* TX interrupt enable */ 212#define ES_TXINTENM (0x03<<5) /* mask for above */ 213#define ES_TXINTENI(i) (((i)>>5)&0x03) 214#define ES_CNTRL(o) (((o)&0x03)<<0) /* control */ 215#define ES_CNTRLM (0x03<<0) /* mask for above */ 216#define ES_REG_UART_RES 0x0a /* R/W: UART reserver register */ 217#define ES_TEST_MODE (1<<0) /* test mode enabled */ 218#define ES_REG_MEM_PAGE 0x0c /* R/W: Memory page register */ 219#define ES_MEM_PAGEO(o) (((o)&0x0f)<<0) /* memory page select - out */ 220#define ES_MEM_PAGEM (0x0f<<0) /* mask for above */ 221#define ES_MEM_PAGEI(i) (((i)>>0)&0x0f) /* memory page select - in */ 222#define ES_REG_1370_CODEC 0x10 /* W/O: Codec write register address */ 223#define ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0)) 224#define ES_REG_1371_CODEC 0x14 /* W/R: Codec Read/Write register address */ 225#define ES_1371_CODEC_RDY (1<<31) /* codec ready */ 226#define ES_1371_CODEC_WIP (1<<30) /* codec register access in progress */ 227#define ES_1371_CODEC_PIRD (1<<23) /* codec read/write select register */ 228#define ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0)) 229#define ES_1371_CODEC_READS(a) ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD) 230#define ES_1371_CODEC_READ(i) (((i)>>0)&0xffff) 231 232#define ES_REG_1371_SMPRATE 0x10 /* W/R: Codec rate converter interface register */ 233#define ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */ 234#define ES_1371_SRC_RAM_ADDRM (0x7f<<25) /* mask for above */ 235#define ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */ 236#define ES_1371_SRC_RAM_WE (1<<24) /* R/W: read/write control for sample rate converter */ 237#define ES_1371_SRC_RAM_BUSY (1<<23) /* R/O: sample rate memory is busy */ 238#define ES_1371_SRC_DISABLE (1<<22) /* sample rate converter disable */ 239#define ES_1371_DIS_P1 (1<<21) /* playback channel 1 accumulator update disable */ 240#define ES_1371_DIS_P2 (1<<20) /* playback channel 1 accumulator update disable */ 241#define ES_1371_DIS_R1 (1<<19) /* capture channel accumulator update disable */ 242#define ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */ 243#define ES_1371_SRC_RAM_DATAM (0xffff<<0) /* mask for above */ 244#define ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */ 245 246#define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */ 247#define ES_1371_JFAST (1<<31) /* fast joystick timing */ 248#define ES_1371_HIB (1<<30) /* host interrupt blocking enable */ 249#define ES_1371_VSB (1<<29) /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */ 250#define ES_1371_VMPUO(o) (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */ 251#define ES_1371_VMPUM (0x03<<27) /* mask for above */ 252#define ES_1371_VMPUI(i) (((i)>>27)&0x03)/* base register address */ 253#define ES_1371_VCDCO(o) (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */ 254#define ES_1371_VCDCM (0x03<<25) /* mask for above */ 255#define ES_1371_VCDCI(i) (((i)>>25)&0x03)/* CODEC address */ 256#define ES_1371_FIRQ (1<<24) /* force an interrupt */ 257#define ES_1371_SDMACAP (1<<23) /* enable event capture for slave DMA controller */ 258#define ES_1371_SPICAP (1<<22) /* enable event capture for slave IRQ controller */ 259#define ES_1371_MDMACAP (1<<21) /* enable event capture for master DMA controller */ 260#define ES_1371_MPICAP (1<<20) /* enable event capture for master IRQ controller */ 261#define ES_1371_ADCAP (1<<19) /* enable event capture for ADLIB register; 0x388xH */ 262#define ES_1371_SVCAP (1<<18) /* enable event capture for SB registers */ 263#define ES_1371_CDCCAP (1<<17) /* enable event capture for CODEC registers */ 264#define ES_1371_BACAP (1<<16) /* enable event capture for SoundScape base address */ 265#define ES_1371_EXI(i) (((i)>>8)&0x07) /* event number */ 266#define ES_1371_AI(i) (((i)>>3)&0x1f) /* event significant I/O address */ 267#define ES_1371_WR (1<<2) /* event capture; 0 = read; 1 = write */ 268#define ES_1371_LEGINT (1<<0) /* interrupt for legacy events; 0 = interrupt did occur */ 269 270#define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */ 271 272#define ES_REG_SERIAL 0x20 /* R/W: Serial interface control register */ 273#define ES_1371_DAC_TEST (1<<22) /* DAC test mode enable */ 274#define ES_P2_END_INCO(o) (((o)&0x07)<<19)/* binary offset value to increment / loop end */ 275#define ES_P2_END_INCM (0x07<<19) /* mask for above */ 276#define ES_P2_END_INCI(i) (((i)>>16)&0x07)/* binary offset value to increment / loop end */ 277#define ES_P2_ST_INCO(o) (((o)&0x07)<<16)/* binary offset value to increment / start */ 278#define ES_P2_ST_INCM (0x07<<16) /* mask for above */ 279#define ES_P2_ST_INCI(i) (((i)<<16)&0x07)/* binary offset value to increment / start */ 280#define ES_R1_LOOP_SEL (1<<15) /* ADC; 0 - loop mode; 1 = stop mode */ 281#define ES_P2_LOOP_SEL (1<<14) /* DAC2; 0 - loop mode; 1 = stop mode */ 282#define ES_P1_LOOP_SEL (1<<13) /* DAC1; 0 - loop mode; 1 = stop mode */ 283#define ES_P2_PAUSE (1<<12) /* DAC2; 0 - play mode; 1 = pause mode */ 284#define ES_P1_PAUSE (1<<11) /* DAC1; 0 - play mode; 1 = pause mode */ 285#define ES_R1_INT_EN (1<<10) /* ADC interrupt enable */ 286#define ES_P2_INT_EN (1<<9) /* DAC2 interrupt enable */ 287#define ES_P1_INT_EN (1<<8) /* DAC1 interrupt enable */ 288#define ES_P1_SCT_RLD (1<<7) /* force sample counter reload for DAC1 */ 289#define ES_P2_DAC_SEN (1<<6) /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */ 290#define ES_R1_MODEO(o) (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */ 291#define ES_R1_MODEM (0x03<<4) /* mask for above */ 292#define ES_R1_MODEI(i) (((i)>>4)&0x03) 293#define ES_P2_MODEO(o) (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */ 294#define ES_P2_MODEM (0x03<<2) /* mask for above */ 295#define ES_P2_MODEI(i) (((i)>>2)&0x03) 296#define ES_P1_MODEO(o) (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */ 297#define ES_P1_MODEM (0x03<<0) /* mask for above */ 298#define ES_P1_MODEI(i) (((i)>>0)&0x03) 299 300#define ES_REG_DAC1_COUNT 0x24 /* R/W: DAC1 sample count register */ 301#define ES_REG_DAC2_COUNT 0x28 /* R/W: DAC2 sample count register */ 302#define ES_REG_ADC_COUNT 0x2c /* R/W: ADC sample count register */ 303#define ES_REG_CURR_COUNT(i) (((i)>>16)&0xffff) 304#define ES_REG_COUNTO(o) (((o)&0xffff)<<0) 305#define ES_REG_COUNTM (0xffff<<0) 306#define ES_REG_COUNTI(i) (((i)>>0)&0xffff) 307 308#define ES_REG_DAC1_FRAME 0x30 /* R/W: PAGE 0x0c; DAC1 frame address */ 309#define ES_REG_DAC1_SIZE 0x34 /* R/W: PAGE 0x0c; DAC1 frame size */ 310#define ES_REG_DAC2_FRAME 0x38 /* R/W: PAGE 0x0c; DAC2 frame address */ 311#define ES_REG_DAC2_SIZE 0x3c /* R/W: PAGE 0x0c; DAC2 frame size */ 312#define ES_REG_ADC_FRAME 0x30 /* R/W: PAGE 0x0d; ADC frame address */ 313#define ES_REG_ADC_SIZE 0x34 /* R/W: PAGE 0x0d; ADC frame size */ 314#define ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16) 315#define ES_REG_FCURR_COUNTM (0xffff<<16) 316#define ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc) 317#define ES_REG_FSIZEO(o) (((o)&0xffff)<<0) 318#define ES_REG_FSIZEM (0xffff<<0) 319#define ES_REG_FSIZEI(i) (((i)>>0)&0xffff) 320#define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */ 321#define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */ 322 323#define ES_REG_UART_FIFO 0x30 /* R/W: PAGE 0x0e; UART FIFO register */ 324#define ES_REG_UF_VALID (1<<8) 325#define ES_REG_UF_BYTEO(o) (((o)&0xff)<<0) 326#define ES_REG_UF_BYTEM (0xff<<0) 327#define ES_REG_UF_BYTEI(i) (((i)>>0)&0xff) 328 329 330/* 331 * Pages 332 */ 333 334#define ES_PAGE_DAC 0x0c 335#define ES_PAGE_ADC 0x0d 336#define ES_PAGE_UART 0x0e 337#define ES_PAGE_UART1 0x0f 338 339/* 340 * Sample rate converter addresses 341 */ 342 343#define ES_SMPREG_DAC1 0x70 344#define ES_SMPREG_DAC2 0x74 345#define ES_SMPREG_ADC 0x78 346#define ES_SMPREG_VOL_ADC 0x6c 347#define ES_SMPREG_VOL_DAC1 0x7c 348#define ES_SMPREG_VOL_DAC2 0x7e 349#define ES_SMPREG_TRUNC_N 0x00 350#define ES_SMPREG_INT_REGS 0x01 351#define ES_SMPREG_ACCUM_FRAC 0x02 352#define ES_SMPREG_VFREQ_FRAC 0x03 353 354/* 355 * Some contants 356 */ 357 358#define ES_1370_SRCLOCK 1411200 359#define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2) 360 361/* 362 * Open modes 363 */ 364 365#define ES_MODE_PLAY1 0x0001 366#define ES_MODE_PLAY2 0x0002 367#define ES_MODE_CAPTURE 0x0004 368 369#define ES_MODE_OUTPUT 0x0001 /* for MIDI */ 370#define ES_MODE_INPUT 0x0002 /* for MIDI */ 371 372/* 373 374 */ 375 376struct ensoniq { 377 spinlock_t reg_lock; 378 struct mutex src_mutex; 379 380 int irq; 381 382 unsigned long playback1size; 383 unsigned long playback2size; 384 unsigned long capture3size; 385 386 unsigned long port; 387 unsigned int mode; 388 unsigned int uartm; /* UART mode */ 389 390 unsigned int ctrl; /* control register */ 391 unsigned int sctrl; /* serial control register */ 392 unsigned int cssr; /* control status register */ 393 unsigned int uartc; /* uart control register */ 394 unsigned int rev; /* chip revision */ 395 396 union { 397#ifdef CHIP1371 398 struct { 399 struct snd_ac97 *ac97; 400 } es1371; 401#else 402 struct { 403 int pclkdiv_lock; 404 struct snd_ak4531 *ak4531; 405 } es1370; 406#endif 407 } u; 408 409 struct pci_dev *pci; 410 struct snd_card *card; 411 struct snd_pcm *pcm1; /* DAC1/ADC PCM */ 412 struct snd_pcm *pcm2; /* DAC2 PCM */ 413 struct snd_pcm_substream *playback1_substream; 414 struct snd_pcm_substream *playback2_substream; 415 struct snd_pcm_substream *capture_substream; 416 unsigned int p1_dma_size; 417 unsigned int p2_dma_size; 418 unsigned int c_dma_size; 419 unsigned int p1_period_size; 420 unsigned int p2_period_size; 421 unsigned int c_period_size; 422 struct snd_rawmidi *rmidi; 423 struct snd_rawmidi_substream *midi_input; 424 struct snd_rawmidi_substream *midi_output; 425 426 unsigned int spdif; 427 unsigned int spdif_default; 428 unsigned int spdif_stream; 429 430#ifdef CHIP1370 431 struct snd_dma_buffer dma_bug; 432#endif 433 434#ifdef SUPPORT_JOYSTICK 435 struct gameport *gameport; 436#endif 437}; 438 439static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id); 440 441static struct pci_device_id snd_audiopci_ids[] = { 442#ifdef CHIP1370 443 { 0x1274, 0x5000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* ES1370 */ 444#endif 445#ifdef CHIP1371 446 { 0x1274, 0x1371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* ES1371 */ 447 { 0x1274, 0x5880, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* ES1373 - CT5880 */ 448 { 0x1102, 0x8938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* Ectiva EV1938 */ 449#endif 450 { 0, } 451}; 452 453MODULE_DEVICE_TABLE(pci, snd_audiopci_ids); 454 455/* 456 * constants 457 */ 458 459#define POLL_COUNT 0xa000 460 461#ifdef CHIP1370 462static unsigned int snd_es1370_fixed_rates[] = 463 {5512, 11025, 22050, 44100}; 464static struct snd_pcm_hw_constraint_list snd_es1370_hw_constraints_rates = { 465 .count = 4, 466 .list = snd_es1370_fixed_rates, 467 .mask = 0, 468}; 469static struct snd_ratnum es1370_clock = { 470 .num = ES_1370_SRCLOCK, 471 .den_min = 29, 472 .den_max = 353, 473 .den_step = 1, 474}; 475static struct snd_pcm_hw_constraint_ratnums snd_es1370_hw_constraints_clock = { 476 .nrats = 1, 477 .rats = &es1370_clock, 478}; 479#else 480static struct snd_ratden es1371_dac_clock = { 481 .num_min = 3000 * (1 << 15), 482 .num_max = 48000 * (1 << 15), 483 .num_step = 3000, 484 .den = 1 << 15, 485}; 486static struct snd_pcm_hw_constraint_ratdens snd_es1371_hw_constraints_dac_clock = { 487 .nrats = 1, 488 .rats = &es1371_dac_clock, 489}; 490static struct snd_ratnum es1371_adc_clock = { 491 .num = 48000 << 15, 492 .den_min = 32768, 493 .den_max = 393216, 494 .den_step = 1, 495}; 496static struct snd_pcm_hw_constraint_ratnums snd_es1371_hw_constraints_adc_clock = { 497 .nrats = 1, 498 .rats = &es1371_adc_clock, 499}; 500#endif 501static const unsigned int snd_ensoniq_sample_shift[] = 502 {0, 1, 1, 2}; 503 504/* 505 * common I/O routines 506 */ 507 508#ifdef CHIP1371 509 510static unsigned int snd_es1371_wait_src_ready(struct ensoniq * ensoniq) 511{ 512 unsigned int t, r = 0; 513 514 for (t = 0; t < POLL_COUNT; t++) { 515 r = inl(ES_REG(ensoniq, 1371_SMPRATE)); 516 if ((r & ES_1371_SRC_RAM_BUSY) == 0) 517 return r; 518 cond_resched(); 519 } 520 snd_printk(KERN_ERR "wait source ready timeout 0x%lx [0x%x]\n", 521 ES_REG(ensoniq, 1371_SMPRATE), r); 522 return 0; 523} 524 525static unsigned int snd_es1371_src_read(struct ensoniq * ensoniq, unsigned short reg) 526{ 527 unsigned int temp, i, orig, r; 528 529 /* wait for ready */ 530 temp = orig = snd_es1371_wait_src_ready(ensoniq); 531 532 /* expose the SRC state bits */ 533 r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | 534 ES_1371_DIS_P2 | ES_1371_DIS_R1); 535 r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000; 536 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 537 538 /* now, wait for busy and the correct time to read */ 539 temp = snd_es1371_wait_src_ready(ensoniq); 540 541 if ((temp & 0x00870000) != 0x00010000) { 542 /* wait for the right state */ 543 for (i = 0; i < POLL_COUNT; i++) { 544 temp = inl(ES_REG(ensoniq, 1371_SMPRATE)); 545 if ((temp & 0x00870000) == 0x00010000) 546 break; 547 } 548 } 549 550 /* hide the state bits */ 551 r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | 552 ES_1371_DIS_P2 | ES_1371_DIS_R1); 553 r |= ES_1371_SRC_RAM_ADDRO(reg); 554 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 555 556 return temp; 557} 558 559static void snd_es1371_src_write(struct ensoniq * ensoniq, 560 unsigned short reg, unsigned short data) 561{ 562 unsigned int r; 563 564 r = snd_es1371_wait_src_ready(ensoniq) & 565 (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | 566 ES_1371_DIS_P2 | ES_1371_DIS_R1); 567 r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data); 568 outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE)); 569} 570 571#endif /* CHIP1371 */ 572 573#ifdef CHIP1370 574 575static void snd_es1370_codec_write(struct snd_ak4531 *ak4531, 576 unsigned short reg, unsigned short val) 577{ 578 struct ensoniq *ensoniq = ak4531->private_data; 579 unsigned long end_time = jiffies + HZ / 10; 580 581 do { 582 if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) { 583 outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC)); 584 return; 585 } 586 schedule_timeout_uninterruptible(1); 587 } while (time_after(end_time, jiffies)); 588 snd_printk(KERN_ERR "codec write timeout, status = 0x%x\n", 589 inl(ES_REG(ensoniq, STATUS))); 590} 591 592#endif /* CHIP1370 */ 593 594#ifdef CHIP1371 595 596static void snd_es1371_codec_write(struct snd_ac97 *ac97, 597 unsigned short reg, unsigned short val) 598{ 599 struct ensoniq *ensoniq = ac97->private_data; 600 unsigned int t, x; 601 602 mutex_lock(&ensoniq->src_mutex); 603 for (t = 0; t < POLL_COUNT; t++) { 604 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) { 605 /* save the current state for latter */ 606 x = snd_es1371_wait_src_ready(ensoniq); 607 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | 608 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000, 609 ES_REG(ensoniq, 1371_SMPRATE)); 610 /* wait for not busy (state 0) first to avoid 611 transition states */ 612 for (t = 0; t < POLL_COUNT; t++) { 613 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 614 0x00000000) 615 break; 616 } 617 /* wait for a SAFE time to write addr/data and then do it, dammit */ 618 for (t = 0; t < POLL_COUNT; t++) { 619 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 620 0x00010000) 621 break; 622 } 623 outl(ES_1371_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1371_CODEC)); 624 /* restore SRC reg */ 625 snd_es1371_wait_src_ready(ensoniq); 626 outl(x, ES_REG(ensoniq, 1371_SMPRATE)); 627 mutex_unlock(&ensoniq->src_mutex); 628 return; 629 } 630 } 631 mutex_unlock(&ensoniq->src_mutex); 632 snd_printk(KERN_ERR "codec write timeout at 0x%lx [0x%x]\n", 633 ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC))); 634} 635 636static unsigned short snd_es1371_codec_read(struct snd_ac97 *ac97, 637 unsigned short reg) 638{ 639 struct ensoniq *ensoniq = ac97->private_data; 640 unsigned int t, x, fail = 0; 641 642 __again: 643 mutex_lock(&ensoniq->src_mutex); 644 for (t = 0; t < POLL_COUNT; t++) { 645 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) { 646 /* save the current state for latter */ 647 x = snd_es1371_wait_src_ready(ensoniq); 648 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | 649 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000, 650 ES_REG(ensoniq, 1371_SMPRATE)); 651 /* wait for not busy (state 0) first to avoid 652 transition states */ 653 for (t = 0; t < POLL_COUNT; t++) { 654 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 655 0x00000000) 656 break; 657 } 658 /* wait for a SAFE time to write addr/data and then do it, dammit */ 659 for (t = 0; t < POLL_COUNT; t++) { 660 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 661 0x00010000) 662 break; 663 } 664 outl(ES_1371_CODEC_READS(reg), ES_REG(ensoniq, 1371_CODEC)); 665 /* restore SRC reg */ 666 snd_es1371_wait_src_ready(ensoniq); 667 outl(x, ES_REG(ensoniq, 1371_SMPRATE)); 668 /* wait for WIP again */ 669 for (t = 0; t < POLL_COUNT; t++) { 670 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) 671 break; 672 } 673 /* now wait for the stinkin' data (RDY) */ 674 for (t = 0; t < POLL_COUNT; t++) { 675 if ((x = inl(ES_REG(ensoniq, 1371_CODEC))) & ES_1371_CODEC_RDY) { 676 mutex_unlock(&ensoniq->src_mutex); 677 return ES_1371_CODEC_READ(x); 678 } 679 } 680 mutex_unlock(&ensoniq->src_mutex); 681 if (++fail > 10) { 682 snd_printk(KERN_ERR "codec read timeout (final) " 683 "at 0x%lx, reg = 0x%x [0x%x]\n", 684 ES_REG(ensoniq, 1371_CODEC), reg, 685 inl(ES_REG(ensoniq, 1371_CODEC))); 686 return 0; 687 } 688 goto __again; 689 } 690 } 691 mutex_unlock(&ensoniq->src_mutex); 692 snd_printk(KERN_ERR "es1371: codec read timeout at 0x%lx [0x%x]\n", 693 ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC))); 694 return 0; 695} 696 697static void snd_es1371_codec_wait(struct snd_ac97 *ac97) 698{ 699 msleep(750); 700 snd_es1371_codec_read(ac97, AC97_RESET); 701 snd_es1371_codec_read(ac97, AC97_VENDOR_ID1); 702 snd_es1371_codec_read(ac97, AC97_VENDOR_ID2); 703 msleep(50); 704} 705 706static void snd_es1371_adc_rate(struct ensoniq * ensoniq, unsigned int rate) 707{ 708 unsigned int n, truncm, freq, result; 709 710 mutex_lock(&ensoniq->src_mutex); 711 n = rate / 3000; 712 if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9))) 713 n--; 714 truncm = (21 * n - 1) | 1; 715 freq = ((48000UL << 15) / rate) * n; 716 result = (48000UL << 15) / (freq / n); 717 if (rate >= 24000) { 718 if (truncm > 239) 719 truncm = 239; 720 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N, 721 (((239 - truncm) >> 1) << 9) | (n << 4)); 722 } else { 723 if (truncm > 119) 724 truncm = 119; 725 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N, 726 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4)); 727 } 728 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS, 729 (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC + 730 ES_SMPREG_INT_REGS) & 0x00ff) | 731 ((freq >> 5) & 0xfc00)); 732 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff); 733 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8); 734 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8); 735 mutex_unlock(&ensoniq->src_mutex); 736} 737 738static void snd_es1371_dac1_rate(struct ensoniq * ensoniq, unsigned int rate) 739{ 740 unsigned int freq, r; 741 742 mutex_lock(&ensoniq->src_mutex); 743 freq = ((rate << 15) + 1500) / 3000; 744 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | 745 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 746 ES_1371_DIS_P1; 747 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 748 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 749 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 + 750 ES_SMPREG_INT_REGS) & 0x00ff) | 751 ((freq >> 5) & 0xfc00)); 752 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff); 753 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | 754 ES_1371_DIS_P2 | ES_1371_DIS_R1)); 755 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 756 mutex_unlock(&ensoniq->src_mutex); 757} 758 759static void snd_es1371_dac2_rate(struct ensoniq * ensoniq, unsigned int rate) 760{ 761 unsigned int freq, r; 762 763 mutex_lock(&ensoniq->src_mutex); 764 freq = ((rate << 15) + 1500) / 3000; 765 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | 766 ES_1371_DIS_P1 | ES_1371_DIS_R1)) | 767 ES_1371_DIS_P2; 768 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 769 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 770 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 + 771 ES_SMPREG_INT_REGS) & 0x00ff) | 772 ((freq >> 5) & 0xfc00)); 773 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC, 774 freq & 0x7fff); 775 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | 776 ES_1371_DIS_P1 | ES_1371_DIS_R1)); 777 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 778 mutex_unlock(&ensoniq->src_mutex); 779} 780 781#endif /* CHIP1371 */ 782 783static int snd_ensoniq_trigger(struct snd_pcm_substream *substream, int cmd) 784{ 785 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 786 switch (cmd) { 787 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 788 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 789 { 790 unsigned int what = 0; 791 struct snd_pcm_substream *s; 792 snd_pcm_group_for_each_entry(s, substream) { 793 if (s == ensoniq->playback1_substream) { 794 what |= ES_P1_PAUSE; 795 snd_pcm_trigger_done(s, substream); 796 } else if (s == ensoniq->playback2_substream) { 797 what |= ES_P2_PAUSE; 798 snd_pcm_trigger_done(s, substream); 799 } else if (s == ensoniq->capture_substream) 800 return -EINVAL; 801 } 802 spin_lock(&ensoniq->reg_lock); 803 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) 804 ensoniq->sctrl |= what; 805 else 806 ensoniq->sctrl &= ~what; 807 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 808 spin_unlock(&ensoniq->reg_lock); 809 break; 810 } 811 case SNDRV_PCM_TRIGGER_START: 812 case SNDRV_PCM_TRIGGER_STOP: 813 { 814 unsigned int what = 0; 815 struct snd_pcm_substream *s; 816 snd_pcm_group_for_each_entry(s, substream) { 817 if (s == ensoniq->playback1_substream) { 818 what |= ES_DAC1_EN; 819 snd_pcm_trigger_done(s, substream); 820 } else if (s == ensoniq->playback2_substream) { 821 what |= ES_DAC2_EN; 822 snd_pcm_trigger_done(s, substream); 823 } else if (s == ensoniq->capture_substream) { 824 what |= ES_ADC_EN; 825 snd_pcm_trigger_done(s, substream); 826 } 827 } 828 spin_lock(&ensoniq->reg_lock); 829 if (cmd == SNDRV_PCM_TRIGGER_START) 830 ensoniq->ctrl |= what; 831 else 832 ensoniq->ctrl &= ~what; 833 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 834 spin_unlock(&ensoniq->reg_lock); 835 break; 836 } 837 default: 838 return -EINVAL; 839 } 840 return 0; 841} 842 843/* 844 * PCM part 845 */ 846 847static int snd_ensoniq_hw_params(struct snd_pcm_substream *substream, 848 struct snd_pcm_hw_params *hw_params) 849{ 850 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 851} 852 853static int snd_ensoniq_hw_free(struct snd_pcm_substream *substream) 854{ 855 return snd_pcm_lib_free_pages(substream); 856} 857 858static int snd_ensoniq_playback1_prepare(struct snd_pcm_substream *substream) 859{ 860 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 861 struct snd_pcm_runtime *runtime = substream->runtime; 862 unsigned int mode = 0; 863 864 ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream); 865 ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream); 866 if (snd_pcm_format_width(runtime->format) == 16) 867 mode |= 0x02; 868 if (runtime->channels > 1) 869 mode |= 0x01; 870 spin_lock_irq(&ensoniq->reg_lock); 871 ensoniq->ctrl &= ~ES_DAC1_EN; 872#ifdef CHIP1371 873 /* 48k doesn't need SRC (it breaks AC3-passthru) */ 874 if (runtime->rate == 48000) 875 ensoniq->ctrl |= ES_1373_BYPASS_P1; 876 else 877 ensoniq->ctrl &= ~ES_1373_BYPASS_P1; 878#endif 879 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 880 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE)); 881 outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME)); 882 outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE)); 883 ensoniq->sctrl &= ~(ES_P1_LOOP_SEL | ES_P1_PAUSE | ES_P1_SCT_RLD | ES_P1_MODEM); 884 ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode); 885 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 886 outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1, 887 ES_REG(ensoniq, DAC1_COUNT)); 888#ifdef CHIP1370 889 ensoniq->ctrl &= ~ES_1370_WTSRSELM; 890 switch (runtime->rate) { 891 case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break; 892 case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break; 893 case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break; 894 case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break; 895 default: snd_BUG(); 896 } 897#endif 898 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 899 spin_unlock_irq(&ensoniq->reg_lock); 900#ifndef CHIP1370 901 snd_es1371_dac1_rate(ensoniq, runtime->rate); 902#endif 903 return 0; 904} 905 906static int snd_ensoniq_playback2_prepare(struct snd_pcm_substream *substream) 907{ 908 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 909 struct snd_pcm_runtime *runtime = substream->runtime; 910 unsigned int mode = 0; 911 912 ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream); 913 ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream); 914 if (snd_pcm_format_width(runtime->format) == 16) 915 mode |= 0x02; 916 if (runtime->channels > 1) 917 mode |= 0x01; 918 spin_lock_irq(&ensoniq->reg_lock); 919 ensoniq->ctrl &= ~ES_DAC2_EN; 920 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 921 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE)); 922 outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME)); 923 outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE)); 924 ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN | 925 ES_P2_END_INCM | ES_P2_ST_INCM | ES_P2_MODEM); 926 ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) | 927 ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0); 928 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 929 outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1, 930 ES_REG(ensoniq, DAC2_COUNT)); 931#ifdef CHIP1370 932 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) { 933 ensoniq->ctrl &= ~ES_1370_PCLKDIVM; 934 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate)); 935 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2; 936 } 937#endif 938 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 939 spin_unlock_irq(&ensoniq->reg_lock); 940#ifndef CHIP1370 941 snd_es1371_dac2_rate(ensoniq, runtime->rate); 942#endif 943 return 0; 944} 945 946static int snd_ensoniq_capture_prepare(struct snd_pcm_substream *substream) 947{ 948 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 949 struct snd_pcm_runtime *runtime = substream->runtime; 950 unsigned int mode = 0; 951 952 ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream); 953 ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream); 954 if (snd_pcm_format_width(runtime->format) == 16) 955 mode |= 0x02; 956 if (runtime->channels > 1) 957 mode |= 0x01; 958 spin_lock_irq(&ensoniq->reg_lock); 959 ensoniq->ctrl &= ~ES_ADC_EN; 960 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 961 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE)); 962 outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME)); 963 outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE)); 964 ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM); 965 ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode); 966 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 967 outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1, 968 ES_REG(ensoniq, ADC_COUNT)); 969#ifdef CHIP1370 970 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) { 971 ensoniq->ctrl &= ~ES_1370_PCLKDIVM; 972 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate)); 973 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE; 974 } 975#endif 976 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 977 spin_unlock_irq(&ensoniq->reg_lock); 978#ifndef CHIP1370 979 snd_es1371_adc_rate(ensoniq, runtime->rate); 980#endif 981 return 0; 982} 983 984static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(struct snd_pcm_substream *substream) 985{ 986 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 987 size_t ptr; 988 989 spin_lock(&ensoniq->reg_lock); 990 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) { 991 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE)); 992 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE))); 993 ptr = bytes_to_frames(substream->runtime, ptr); 994 } else { 995 ptr = 0; 996 } 997 spin_unlock(&ensoniq->reg_lock); 998 return ptr; 999} 1000 1001static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(struct snd_pcm_substream *substream) 1002{ 1003 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1004 size_t ptr; 1005 1006 spin_lock(&ensoniq->reg_lock); 1007 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) { 1008 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE)); 1009 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE))); 1010 ptr = bytes_to_frames(substream->runtime, ptr); 1011 } else { 1012 ptr = 0; 1013 } 1014 spin_unlock(&ensoniq->reg_lock); 1015 return ptr; 1016} 1017 1018static snd_pcm_uframes_t snd_ensoniq_capture_pointer(struct snd_pcm_substream *substream) 1019{ 1020 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1021 size_t ptr; 1022 1023 spin_lock(&ensoniq->reg_lock); 1024 if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) { 1025 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE)); 1026 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE))); 1027 ptr = bytes_to_frames(substream->runtime, ptr); 1028 } else { 1029 ptr = 0; 1030 } 1031 spin_unlock(&ensoniq->reg_lock); 1032 return ptr; 1033} 1034 1035static struct snd_pcm_hardware snd_ensoniq_playback1 = 1036{ 1037 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1038 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1039 SNDRV_PCM_INFO_MMAP_VALID | 1040 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START), 1041 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1042 .rates = 1043#ifndef CHIP1370 1044 SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1045#else 1046 (SNDRV_PCM_RATE_KNOT | /* 5512Hz rate */ 1047 SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 | 1048 SNDRV_PCM_RATE_44100), 1049#endif 1050 .rate_min = 4000, 1051 .rate_max = 48000, 1052 .channels_min = 1, 1053 .channels_max = 2, 1054 .buffer_bytes_max = (128*1024), 1055 .period_bytes_min = 64, 1056 .period_bytes_max = (128*1024), 1057 .periods_min = 1, 1058 .periods_max = 1024, 1059 .fifo_size = 0, 1060}; 1061 1062static struct snd_pcm_hardware snd_ensoniq_playback2 = 1063{ 1064 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1065 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1066 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE | 1067 SNDRV_PCM_INFO_SYNC_START), 1068 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1069 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1070 .rate_min = 4000, 1071 .rate_max = 48000, 1072 .channels_min = 1, 1073 .channels_max = 2, 1074 .buffer_bytes_max = (128*1024), 1075 .period_bytes_min = 64, 1076 .period_bytes_max = (128*1024), 1077 .periods_min = 1, 1078 .periods_max = 1024, 1079 .fifo_size = 0, 1080}; 1081 1082static struct snd_pcm_hardware snd_ensoniq_capture = 1083{ 1084 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1085 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1086 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START), 1087 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1088 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1089 .rate_min = 4000, 1090 .rate_max = 48000, 1091 .channels_min = 1, 1092 .channels_max = 2, 1093 .buffer_bytes_max = (128*1024), 1094 .period_bytes_min = 64, 1095 .period_bytes_max = (128*1024), 1096 .periods_min = 1, 1097 .periods_max = 1024, 1098 .fifo_size = 0, 1099}; 1100 1101static int snd_ensoniq_playback1_open(struct snd_pcm_substream *substream) 1102{ 1103 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1104 struct snd_pcm_runtime *runtime = substream->runtime; 1105 1106 ensoniq->mode |= ES_MODE_PLAY1; 1107 ensoniq->playback1_substream = substream; 1108 runtime->hw = snd_ensoniq_playback1; 1109 snd_pcm_set_sync(substream); 1110 spin_lock_irq(&ensoniq->reg_lock); 1111 if (ensoniq->spdif && ensoniq->playback2_substream == NULL) 1112 ensoniq->spdif_stream = ensoniq->spdif_default; 1113 spin_unlock_irq(&ensoniq->reg_lock); 1114#ifdef CHIP1370 1115 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1116 &snd_es1370_hw_constraints_rates); 1117#else 1118 snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1119 &snd_es1371_hw_constraints_dac_clock); 1120#endif 1121 return 0; 1122} 1123 1124static int snd_ensoniq_playback2_open(struct snd_pcm_substream *substream) 1125{ 1126 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1127 struct snd_pcm_runtime *runtime = substream->runtime; 1128 1129 ensoniq->mode |= ES_MODE_PLAY2; 1130 ensoniq->playback2_substream = substream; 1131 runtime->hw = snd_ensoniq_playback2; 1132 snd_pcm_set_sync(substream); 1133 spin_lock_irq(&ensoniq->reg_lock); 1134 if (ensoniq->spdif && ensoniq->playback1_substream == NULL) 1135 ensoniq->spdif_stream = ensoniq->spdif_default; 1136 spin_unlock_irq(&ensoniq->reg_lock); 1137#ifdef CHIP1370 1138 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1139 &snd_es1370_hw_constraints_clock); 1140#else 1141 snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1142 &snd_es1371_hw_constraints_dac_clock); 1143#endif 1144 return 0; 1145} 1146 1147static int snd_ensoniq_capture_open(struct snd_pcm_substream *substream) 1148{ 1149 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1150 struct snd_pcm_runtime *runtime = substream->runtime; 1151 1152 ensoniq->mode |= ES_MODE_CAPTURE; 1153 ensoniq->capture_substream = substream; 1154 runtime->hw = snd_ensoniq_capture; 1155 snd_pcm_set_sync(substream); 1156#ifdef CHIP1370 1157 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1158 &snd_es1370_hw_constraints_clock); 1159#else 1160 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1161 &snd_es1371_hw_constraints_adc_clock); 1162#endif 1163 return 0; 1164} 1165 1166static int snd_ensoniq_playback1_close(struct snd_pcm_substream *substream) 1167{ 1168 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1169 1170 ensoniq->playback1_substream = NULL; 1171 ensoniq->mode &= ~ES_MODE_PLAY1; 1172 return 0; 1173} 1174 1175static int snd_ensoniq_playback2_close(struct snd_pcm_substream *substream) 1176{ 1177 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1178 1179 ensoniq->playback2_substream = NULL; 1180 spin_lock_irq(&ensoniq->reg_lock); 1181#ifdef CHIP1370 1182 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2; 1183#endif 1184 ensoniq->mode &= ~ES_MODE_PLAY2; 1185 spin_unlock_irq(&ensoniq->reg_lock); 1186 return 0; 1187} 1188 1189static int snd_ensoniq_capture_close(struct snd_pcm_substream *substream) 1190{ 1191 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1192 1193 ensoniq->capture_substream = NULL; 1194 spin_lock_irq(&ensoniq->reg_lock); 1195#ifdef CHIP1370 1196 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE; 1197#endif 1198 ensoniq->mode &= ~ES_MODE_CAPTURE; 1199 spin_unlock_irq(&ensoniq->reg_lock); 1200 return 0; 1201} 1202 1203static struct snd_pcm_ops snd_ensoniq_playback1_ops = { 1204 .open = snd_ensoniq_playback1_open, 1205 .close = snd_ensoniq_playback1_close, 1206 .ioctl = snd_pcm_lib_ioctl, 1207 .hw_params = snd_ensoniq_hw_params, 1208 .hw_free = snd_ensoniq_hw_free, 1209 .prepare = snd_ensoniq_playback1_prepare, 1210 .trigger = snd_ensoniq_trigger, 1211 .pointer = snd_ensoniq_playback1_pointer, 1212}; 1213 1214static struct snd_pcm_ops snd_ensoniq_playback2_ops = { 1215 .open = snd_ensoniq_playback2_open, 1216 .close = snd_ensoniq_playback2_close, 1217 .ioctl = snd_pcm_lib_ioctl, 1218 .hw_params = snd_ensoniq_hw_params, 1219 .hw_free = snd_ensoniq_hw_free, 1220 .prepare = snd_ensoniq_playback2_prepare, 1221 .trigger = snd_ensoniq_trigger, 1222 .pointer = snd_ensoniq_playback2_pointer, 1223}; 1224 1225static struct snd_pcm_ops snd_ensoniq_capture_ops = { 1226 .open = snd_ensoniq_capture_open, 1227 .close = snd_ensoniq_capture_close, 1228 .ioctl = snd_pcm_lib_ioctl, 1229 .hw_params = snd_ensoniq_hw_params, 1230 .hw_free = snd_ensoniq_hw_free, 1231 .prepare = snd_ensoniq_capture_prepare, 1232 .trigger = snd_ensoniq_trigger, 1233 .pointer = snd_ensoniq_capture_pointer, 1234}; 1235 1236static int __devinit snd_ensoniq_pcm(struct ensoniq * ensoniq, int device, 1237 struct snd_pcm ** rpcm) 1238{ 1239 struct snd_pcm *pcm; 1240 int err; 1241 1242 if (rpcm) 1243 *rpcm = NULL; 1244#ifdef CHIP1370 1245 err = snd_pcm_new(ensoniq->card, "ES1370/1", device, 1, 1, &pcm); 1246#else 1247 err = snd_pcm_new(ensoniq->card, "ES1371/1", device, 1, 1, &pcm); 1248#endif 1249 if (err < 0) 1250 return err; 1251 1252#ifdef CHIP1370 1253 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops); 1254#else 1255 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops); 1256#endif 1257 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops); 1258 1259 pcm->private_data = ensoniq; 1260 pcm->info_flags = 0; 1261#ifdef CHIP1370 1262 strcpy(pcm->name, "ES1370 DAC2/ADC"); 1263#else 1264 strcpy(pcm->name, "ES1371 DAC2/ADC"); 1265#endif 1266 ensoniq->pcm1 = pcm; 1267 1268 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1269 snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024); 1270 1271 if (rpcm) 1272 *rpcm = pcm; 1273 return 0; 1274} 1275 1276static int __devinit snd_ensoniq_pcm2(struct ensoniq * ensoniq, int device, 1277 struct snd_pcm ** rpcm) 1278{ 1279 struct snd_pcm *pcm; 1280 int err; 1281 1282 if (rpcm) 1283 *rpcm = NULL; 1284#ifdef CHIP1370 1285 err = snd_pcm_new(ensoniq->card, "ES1370/2", device, 1, 0, &pcm); 1286#else 1287 err = snd_pcm_new(ensoniq->card, "ES1371/2", device, 1, 0, &pcm); 1288#endif 1289 if (err < 0) 1290 return err; 1291 1292#ifdef CHIP1370 1293 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops); 1294#else 1295 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops); 1296#endif 1297 pcm->private_data = ensoniq; 1298 pcm->info_flags = 0; 1299#ifdef CHIP1370 1300 strcpy(pcm->name, "ES1370 DAC1"); 1301#else 1302 strcpy(pcm->name, "ES1371 DAC1"); 1303#endif 1304 ensoniq->pcm2 = pcm; 1305 1306 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1307 snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024); 1308 1309 if (rpcm) 1310 *rpcm = pcm; 1311 return 0; 1312} 1313 1314/* 1315 * Mixer section 1316 */ 1317 1318/* 1319 * ENS1371 mixer (including SPDIF interface) 1320 */ 1321#ifdef CHIP1371 1322static int snd_ens1373_spdif_info(struct snd_kcontrol *kcontrol, 1323 struct snd_ctl_elem_info *uinfo) 1324{ 1325 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1326 uinfo->count = 1; 1327 return 0; 1328} 1329 1330static int snd_ens1373_spdif_default_get(struct snd_kcontrol *kcontrol, 1331 struct snd_ctl_elem_value *ucontrol) 1332{ 1333 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1334 spin_lock_irq(&ensoniq->reg_lock); 1335 ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff; 1336 ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff; 1337 ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff; 1338 ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff; 1339 spin_unlock_irq(&ensoniq->reg_lock); 1340 return 0; 1341} 1342 1343static int snd_ens1373_spdif_default_put(struct snd_kcontrol *kcontrol, 1344 struct snd_ctl_elem_value *ucontrol) 1345{ 1346 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1347 unsigned int val; 1348 int change; 1349 1350 val = ((u32)ucontrol->value.iec958.status[0] << 0) | 1351 ((u32)ucontrol->value.iec958.status[1] << 8) | 1352 ((u32)ucontrol->value.iec958.status[2] << 16) | 1353 ((u32)ucontrol->value.iec958.status[3] << 24); 1354 spin_lock_irq(&ensoniq->reg_lock); 1355 change = ensoniq->spdif_default != val; 1356 ensoniq->spdif_default = val; 1357 if (change && ensoniq->playback1_substream == NULL && 1358 ensoniq->playback2_substream == NULL) 1359 outl(val, ES_REG(ensoniq, CHANNEL_STATUS)); 1360 spin_unlock_irq(&ensoniq->reg_lock); 1361 return change; 1362} 1363 1364static int snd_ens1373_spdif_mask_get(struct snd_kcontrol *kcontrol, 1365 struct snd_ctl_elem_value *ucontrol) 1366{ 1367 ucontrol->value.iec958.status[0] = 0xff; 1368 ucontrol->value.iec958.status[1] = 0xff; 1369 ucontrol->value.iec958.status[2] = 0xff; 1370 ucontrol->value.iec958.status[3] = 0xff; 1371 return 0; 1372} 1373 1374static int snd_ens1373_spdif_stream_get(struct snd_kcontrol *kcontrol, 1375 struct snd_ctl_elem_value *ucontrol) 1376{ 1377 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1378 spin_lock_irq(&ensoniq->reg_lock); 1379 ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff; 1380 ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff; 1381 ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff; 1382 ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff; 1383 spin_unlock_irq(&ensoniq->reg_lock); 1384 return 0; 1385} 1386 1387static int snd_ens1373_spdif_stream_put(struct snd_kcontrol *kcontrol, 1388 struct snd_ctl_elem_value *ucontrol) 1389{ 1390 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1391 unsigned int val; 1392 int change; 1393 1394 val = ((u32)ucontrol->value.iec958.status[0] << 0) | 1395 ((u32)ucontrol->value.iec958.status[1] << 8) | 1396 ((u32)ucontrol->value.iec958.status[2] << 16) | 1397 ((u32)ucontrol->value.iec958.status[3] << 24); 1398 spin_lock_irq(&ensoniq->reg_lock); 1399 change = ensoniq->spdif_stream != val; 1400 ensoniq->spdif_stream = val; 1401 if (change && (ensoniq->playback1_substream != NULL || 1402 ensoniq->playback2_substream != NULL)) 1403 outl(val, ES_REG(ensoniq, CHANNEL_STATUS)); 1404 spin_unlock_irq(&ensoniq->reg_lock); 1405 return change; 1406} 1407 1408#define ES1371_SPDIF(xname) \ 1409{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \ 1410 .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put } 1411 1412static int snd_es1371_spdif_info(struct snd_kcontrol *kcontrol, 1413 struct snd_ctl_elem_info *uinfo) 1414{ 1415 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 1416 uinfo->count = 1; 1417 uinfo->value.integer.min = 0; 1418 uinfo->value.integer.max = 1; 1419 return 0; 1420} 1421 1422static int snd_es1371_spdif_get(struct snd_kcontrol *kcontrol, 1423 struct snd_ctl_elem_value *ucontrol) 1424{ 1425 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1426 1427 spin_lock_irq(&ensoniq->reg_lock); 1428 ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0; 1429 spin_unlock_irq(&ensoniq->reg_lock); 1430 return 0; 1431} 1432 1433static int snd_es1371_spdif_put(struct snd_kcontrol *kcontrol, 1434 struct snd_ctl_elem_value *ucontrol) 1435{ 1436 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1437 unsigned int nval1, nval2; 1438 int change; 1439 1440 nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0; 1441 nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0; 1442 spin_lock_irq(&ensoniq->reg_lock); 1443 change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1; 1444 ensoniq->ctrl &= ~ES_1373_SPDIF_THRU; 1445 ensoniq->ctrl |= nval1; 1446 ensoniq->cssr &= ~ES_1373_SPDIF_EN; 1447 ensoniq->cssr |= nval2; 1448 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1449 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS)); 1450 spin_unlock_irq(&ensoniq->reg_lock); 1451 return change; 1452} 1453 1454 1455/* spdif controls */ 1456static struct snd_kcontrol_new snd_es1371_mixer_spdif[] __devinitdata = { 1457 ES1371_SPDIF(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH)), 1458 { 1459 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1460 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), 1461 .info = snd_ens1373_spdif_info, 1462 .get = snd_ens1373_spdif_default_get, 1463 .put = snd_ens1373_spdif_default_put, 1464 }, 1465 { 1466 .access = SNDRV_CTL_ELEM_ACCESS_READ, 1467 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1468 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK), 1469 .info = snd_ens1373_spdif_info, 1470 .get = snd_ens1373_spdif_mask_get 1471 }, 1472 { 1473 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1474 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), 1475 .info = snd_ens1373_spdif_info, 1476 .get = snd_ens1373_spdif_stream_get, 1477 .put = snd_ens1373_spdif_stream_put 1478 }, 1479}; 1480 1481 1482static int snd_es1373_rear_info(struct snd_kcontrol *kcontrol, 1483 struct snd_ctl_elem_info *uinfo) 1484{ 1485 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 1486 uinfo->count = 1; 1487 uinfo->value.integer.min = 0; 1488 uinfo->value.integer.max = 1; 1489 return 0; 1490} 1491 1492static int snd_es1373_rear_get(struct snd_kcontrol *kcontrol, 1493 struct snd_ctl_elem_value *ucontrol) 1494{ 1495 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1496 int val = 0; 1497 1498 spin_lock_irq(&ensoniq->reg_lock); 1499 if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26| 1500 ES_1373_REAR_BIT24)) == ES_1373_REAR_BIT26) 1501 val = 1; 1502 ucontrol->value.integer.value[0] = val; 1503 spin_unlock_irq(&ensoniq->reg_lock); 1504 return 0; 1505} 1506 1507static int snd_es1373_rear_put(struct snd_kcontrol *kcontrol, 1508 struct snd_ctl_elem_value *ucontrol) 1509{ 1510 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1511 unsigned int nval1; 1512 int change; 1513 1514 nval1 = ucontrol->value.integer.value[0] ? 1515 ES_1373_REAR_BIT26 : (ES_1373_REAR_BIT27|ES_1373_REAR_BIT24); 1516 spin_lock_irq(&ensoniq->reg_lock); 1517 change = (ensoniq->cssr & (ES_1373_REAR_BIT27| 1518 ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) != nval1; 1519 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24); 1520 ensoniq->cssr |= nval1; 1521 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS)); 1522 spin_unlock_irq(&ensoniq->reg_lock); 1523 return change; 1524} 1525 1526static struct snd_kcontrol_new snd_ens1373_rear __devinitdata = 1527{ 1528 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1529 .name = "AC97 2ch->4ch Copy Switch", 1530 .info = snd_es1373_rear_info, 1531 .get = snd_es1373_rear_get, 1532 .put = snd_es1373_rear_put, 1533}; 1534 1535static int snd_es1373_line_info(struct snd_kcontrol *kcontrol, 1536 struct snd_ctl_elem_info *uinfo) 1537{ 1538 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 1539 uinfo->count = 1; 1540 uinfo->value.integer.min = 0; 1541 uinfo->value.integer.max = 1; 1542 return 0; 1543} 1544 1545static int snd_es1373_line_get(struct snd_kcontrol *kcontrol, 1546 struct snd_ctl_elem_value *ucontrol) 1547{ 1548 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1549 int val = 0; 1550 1551 spin_lock_irq(&ensoniq->reg_lock); 1552 if ((ensoniq->ctrl & ES_1371_GPIO_OUTM) >= 4) 1553 val = 1; 1554 ucontrol->value.integer.value[0] = val; 1555 spin_unlock_irq(&ensoniq->reg_lock); 1556 return 0; 1557} 1558 1559static int snd_es1373_line_put(struct snd_kcontrol *kcontrol, 1560 struct snd_ctl_elem_value *ucontrol) 1561{ 1562 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1563 int changed; 1564 unsigned int ctrl; 1565 1566 spin_lock_irq(&ensoniq->reg_lock); 1567 ctrl = ensoniq->ctrl; 1568 if (ucontrol->value.integer.value[0]) 1569 ensoniq->ctrl |= ES_1371_GPIO_OUT(4); /* switch line-in -> rear out */ 1570 else 1571 ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4); 1572 changed = (ctrl != ensoniq->ctrl); 1573 if (changed) 1574 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1575 spin_unlock_irq(&ensoniq->reg_lock); 1576 return changed; 1577} 1578 1579static struct snd_kcontrol_new snd_ens1373_line __devinitdata = 1580{ 1581 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1582 .name = "Line In->Rear Out Switch", 1583 .info = snd_es1373_line_info, 1584 .get = snd_es1373_line_get, 1585 .put = snd_es1373_line_put, 1586}; 1587 1588static void snd_ensoniq_mixer_free_ac97(struct snd_ac97 *ac97) 1589{ 1590 struct ensoniq *ensoniq = ac97->private_data; 1591 ensoniq->u.es1371.ac97 = NULL; 1592} 1593 1594struct es1371_quirk { 1595 unsigned short vid; /* vendor ID */ 1596 unsigned short did; /* device ID */ 1597 unsigned char rev; /* revision */ 1598}; 1599 1600static int __devinit es1371_quirk_lookup(struct ensoniq *ensoniq, 1601 struct es1371_quirk *list) 1602{ 1603 while (list->vid != (unsigned short)PCI_ANY_ID) { 1604 if (ensoniq->pci->vendor == list->vid && 1605 ensoniq->pci->device == list->did && 1606 ensoniq->rev == list->rev) 1607 return 1; 1608 list++; 1609 } 1610 return 0; 1611} 1612 1613static struct es1371_quirk es1371_spdif_present[] __devinitdata = { 1614 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C }, 1615 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D }, 1616 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E }, 1617 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A }, 1618 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 }, 1619 { .vid = PCI_ANY_ID, .did = PCI_ANY_ID } 1620}; 1621 1622static struct snd_pci_quirk ens1373_line_quirk[] __devinitdata = { 1623 SND_PCI_QUIRK_ID(0x1274, 0x2000), /* GA-7DXR */ 1624 SND_PCI_QUIRK_ID(0x1458, 0xa000), /* GA-8IEXP */ 1625 { } /* end */ 1626}; 1627 1628static int __devinit snd_ensoniq_1371_mixer(struct ensoniq *ensoniq, 1629 int has_spdif, int has_line) 1630{ 1631 struct snd_card *card = ensoniq->card; 1632 struct snd_ac97_bus *pbus; 1633 struct snd_ac97_template ac97; 1634 int err; 1635 static struct snd_ac97_bus_ops ops = { 1636 .write = snd_es1371_codec_write, 1637 .read = snd_es1371_codec_read, 1638 .wait = snd_es1371_codec_wait, 1639 }; 1640 1641 if ((err = snd_ac97_bus(card, 0, &ops, NULL, &pbus)) < 0) 1642 return err; 1643 1644 memset(&ac97, 0, sizeof(ac97)); 1645 ac97.private_data = ensoniq; 1646 ac97.private_free = snd_ensoniq_mixer_free_ac97; 1647 ac97.scaps = AC97_SCAP_AUDIO; 1648 if ((err = snd_ac97_mixer(pbus, &ac97, &ensoniq->u.es1371.ac97)) < 0) 1649 return err; 1650 if (has_spdif > 0 || 1651 (!has_spdif && es1371_quirk_lookup(ensoniq, es1371_spdif_present))) { 1652 struct snd_kcontrol *kctl; 1653 int i, index = 0; 1654 1655 ensoniq->spdif_default = ensoniq->spdif_stream = 1656 SNDRV_PCM_DEFAULT_CON_SPDIF; 1657 outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS)); 1658 1659 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF) 1660 index++; 1661 1662 for (i = 0; i < ARRAY_SIZE(snd_es1371_mixer_spdif); i++) { 1663 kctl = snd_ctl_new1(&snd_es1371_mixer_spdif[i], ensoniq); 1664 if (!kctl) 1665 return -ENOMEM; 1666 kctl->id.index = index; 1667 err = snd_ctl_add(card, kctl); 1668 if (err < 0) 1669 return err; 1670 } 1671 } 1672 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) { 1673 /* mirror rear to front speakers */ 1674 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT24); 1675 ensoniq->cssr |= ES_1373_REAR_BIT26; 1676 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq)); 1677 if (err < 0) 1678 return err; 1679 } 1680 if (has_line > 0 || 1681 snd_pci_quirk_lookup(ensoniq->pci, ens1373_line_quirk)) { 1682 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_line, 1683 ensoniq)); 1684 if (err < 0) 1685 return err; 1686 } 1687 1688 return 0; 1689} 1690 1691#endif /* CHIP1371 */ 1692 1693/* generic control callbacks for ens1370 */ 1694#ifdef CHIP1370 1695#define ENSONIQ_CONTROL(xname, mask) \ 1696{ .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \ 1697 .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \ 1698 .private_value = mask } 1699 1700static int snd_ensoniq_control_info(struct snd_kcontrol *kcontrol, 1701 struct snd_ctl_elem_info *uinfo) 1702{ 1703 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 1704 uinfo->count = 1; 1705 uinfo->value.integer.min = 0; 1706 uinfo->value.integer.max = 1; 1707 return 0; 1708} 1709 1710static int snd_ensoniq_control_get(struct snd_kcontrol *kcontrol, 1711 struct snd_ctl_elem_value *ucontrol) 1712{ 1713 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1714 int mask = kcontrol->private_value; 1715 1716 spin_lock_irq(&ensoniq->reg_lock); 1717 ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0; 1718 spin_unlock_irq(&ensoniq->reg_lock); 1719 return 0; 1720} 1721 1722static int snd_ensoniq_control_put(struct snd_kcontrol *kcontrol, 1723 struct snd_ctl_elem_value *ucontrol) 1724{ 1725 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1726 int mask = kcontrol->private_value; 1727 unsigned int nval; 1728 int change; 1729 1730 nval = ucontrol->value.integer.value[0] ? mask : 0; 1731 spin_lock_irq(&ensoniq->reg_lock); 1732 change = (ensoniq->ctrl & mask) != nval; 1733 ensoniq->ctrl &= ~mask; 1734 ensoniq->ctrl |= nval; 1735 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1736 spin_unlock_irq(&ensoniq->reg_lock); 1737 return change; 1738} 1739 1740/* 1741 * ENS1370 mixer 1742 */ 1743 1744static struct snd_kcontrol_new snd_es1370_controls[2] __devinitdata = { 1745ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0), 1746ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1) 1747}; 1748 1749#define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls) 1750 1751static void snd_ensoniq_mixer_free_ak4531(struct snd_ak4531 *ak4531) 1752{ 1753 struct ensoniq *ensoniq = ak4531->private_data; 1754 ensoniq->u.es1370.ak4531 = NULL; 1755} 1756 1757static int __devinit snd_ensoniq_1370_mixer(struct ensoniq * ensoniq) 1758{ 1759 struct snd_card *card = ensoniq->card; 1760 struct snd_ak4531 ak4531; 1761 unsigned int idx; 1762 int err; 1763 1764 /* try reset AK4531 */ 1765 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC)); 1766 inw(ES_REG(ensoniq, 1370_CODEC)); 1767 udelay(100); 1768 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC)); 1769 inw(ES_REG(ensoniq, 1370_CODEC)); 1770 udelay(100); 1771 1772 memset(&ak4531, 0, sizeof(ak4531)); 1773 ak4531.write = snd_es1370_codec_write; 1774 ak4531.private_data = ensoniq; 1775 ak4531.private_free = snd_ensoniq_mixer_free_ak4531; 1776 if ((err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531)) < 0) 1777 return err; 1778 for (idx = 0; idx < ES1370_CONTROLS; idx++) { 1779 err = snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq)); 1780 if (err < 0) 1781 return err; 1782 } 1783 return 0; 1784} 1785 1786#endif /* CHIP1370 */ 1787 1788#ifdef SUPPORT_JOYSTICK 1789 1790#ifdef CHIP1371 1791static int __devinit snd_ensoniq_get_joystick_port(int dev) 1792{ 1793 switch (joystick_port[dev]) { 1794 case 0: /* disabled */ 1795 case 1: /* auto-detect */ 1796 case 0x200: 1797 case 0x208: 1798 case 0x210: 1799 case 0x218: 1800 return joystick_port[dev]; 1801 1802 default: 1803 printk(KERN_ERR "ens1371: invalid joystick port %#x", joystick_port[dev]); 1804 return 0; 1805 } 1806} 1807#else 1808static inline int snd_ensoniq_get_joystick_port(int dev) 1809{ 1810 return joystick[dev] ? 0x200 : 0; 1811} 1812#endif 1813 1814static int __devinit snd_ensoniq_create_gameport(struct ensoniq *ensoniq, int dev) 1815{ 1816 struct gameport *gp; 1817 int io_port; 1818 1819 io_port = snd_ensoniq_get_joystick_port(dev); 1820 1821 switch (io_port) { 1822 case 0: 1823 return -ENOSYS; 1824 1825 case 1: /* auto_detect */ 1826 for (io_port = 0x200; io_port <= 0x218; io_port += 8) 1827 if (request_region(io_port, 8, "ens137x: gameport")) 1828 break; 1829 if (io_port > 0x218) { 1830 printk(KERN_WARNING "ens137x: no gameport ports available\n"); 1831 return -EBUSY; 1832 } 1833 break; 1834 1835 default: 1836 if (!request_region(io_port, 8, "ens137x: gameport")) { 1837 printk(KERN_WARNING "ens137x: gameport io port 0x%#x in use\n", 1838 io_port); 1839 return -EBUSY; 1840 } 1841 break; 1842 } 1843 1844 ensoniq->gameport = gp = gameport_allocate_port(); 1845 if (!gp) { 1846 printk(KERN_ERR "ens137x: cannot allocate memory for gameport\n"); 1847 release_region(io_port, 8); 1848 return -ENOMEM; 1849 } 1850 1851 gameport_set_name(gp, "ES137x"); 1852 gameport_set_phys(gp, "pci%s/gameport0", pci_name(ensoniq->pci)); 1853 gameport_set_dev_parent(gp, &ensoniq->pci->dev); 1854 gp->io = io_port; 1855 1856 ensoniq->ctrl |= ES_JYSTK_EN; 1857#ifdef CHIP1371 1858 ensoniq->ctrl &= ~ES_1371_JOY_ASELM; 1859 ensoniq->ctrl |= ES_1371_JOY_ASEL((io_port - 0x200) / 8); 1860#endif 1861 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1862 1863 gameport_register_port(ensoniq->gameport); 1864 1865 return 0; 1866} 1867 1868static void snd_ensoniq_free_gameport(struct ensoniq *ensoniq) 1869{ 1870 if (ensoniq->gameport) { 1871 int port = ensoniq->gameport->io; 1872 1873 gameport_unregister_port(ensoniq->gameport); 1874 ensoniq->gameport = NULL; 1875 ensoniq->ctrl &= ~ES_JYSTK_EN; 1876 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1877 release_region(port, 8); 1878 } 1879} 1880#else 1881static inline int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, long port) { return -ENOSYS; } 1882static inline void snd_ensoniq_free_gameport(struct ensoniq *ensoniq) { } 1883#endif /* SUPPORT_JOYSTICK */ 1884 1885/* 1886 1887 */ 1888 1889static void snd_ensoniq_proc_read(struct snd_info_entry *entry, 1890 struct snd_info_buffer *buffer) 1891{ 1892 struct ensoniq *ensoniq = entry->private_data; 1893 1894#ifdef CHIP1370 1895 snd_iprintf(buffer, "Ensoniq AudioPCI ES1370\n\n"); 1896#else 1897 snd_iprintf(buffer, "Ensoniq AudioPCI ES1371\n\n"); 1898#endif 1899 snd_iprintf(buffer, "Joystick enable : %s\n", 1900 ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off"); 1901#ifdef CHIP1370 1902 snd_iprintf(buffer, "MIC +5V bias : %s\n", 1903 ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off"); 1904 snd_iprintf(buffer, "Line In to AOUT : %s\n", 1905 ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off"); 1906#else 1907 snd_iprintf(buffer, "Joystick port : 0x%x\n", 1908 (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200); 1909#endif 1910} 1911 1912static void __devinit snd_ensoniq_proc_init(struct ensoniq * ensoniq) 1913{ 1914 struct snd_info_entry *entry; 1915 1916 if (! snd_card_proc_new(ensoniq->card, "audiopci", &entry)) 1917 snd_info_set_text_ops(entry, ensoniq, snd_ensoniq_proc_read); 1918} 1919 1920/* 1921 1922 */ 1923 1924static int snd_ensoniq_free(struct ensoniq *ensoniq) 1925{ 1926 snd_ensoniq_free_gameport(ensoniq); 1927 if (ensoniq->irq < 0) 1928 goto __hw_end; 1929#ifdef CHIP1370 1930 outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL)); /* switch everything off */ 1931 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */ 1932#else 1933 outl(0, ES_REG(ensoniq, CONTROL)); /* switch everything off */ 1934 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */ 1935#endif 1936 synchronize_irq(ensoniq->irq); 1937 pci_set_power_state(ensoniq->pci, 3); 1938 __hw_end: 1939#ifdef CHIP1370 1940 if (ensoniq->dma_bug.area) 1941 snd_dma_free_pages(&ensoniq->dma_bug); 1942#endif 1943 if (ensoniq->irq >= 0) 1944 free_irq(ensoniq->irq, ensoniq); 1945 pci_release_regions(ensoniq->pci); 1946 pci_disable_device(ensoniq->pci); 1947 kfree(ensoniq); 1948 return 0; 1949} 1950 1951static int snd_ensoniq_dev_free(struct snd_device *device) 1952{ 1953 struct ensoniq *ensoniq = device->device_data; 1954 return snd_ensoniq_free(ensoniq); 1955} 1956 1957#ifdef CHIP1371 1958static struct snd_pci_quirk es1371_amplifier_hack[] __devinitdata = { 1959 SND_PCI_QUIRK_ID(0x107b, 0x2150), /* Gateway Solo 2150 */ 1960 SND_PCI_QUIRK_ID(0x13bd, 0x100c), /* EV1938 on Mebius PC-MJ100V */ 1961 SND_PCI_QUIRK_ID(0x1102, 0x5938), /* Targa Xtender300 */ 1962 SND_PCI_QUIRK_ID(0x1102, 0x8938), /* IPC Topnote G notebook */ 1963 { } /* end */ 1964}; 1965 1966static struct es1371_quirk es1371_ac97_reset_hack[] = { 1967 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C }, 1968 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D }, 1969 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E }, 1970 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A }, 1971 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 }, 1972 { .vid = PCI_ANY_ID, .did = PCI_ANY_ID } 1973}; 1974#endif 1975 1976static void snd_ensoniq_chip_init(struct ensoniq *ensoniq) 1977{ 1978#ifdef CHIP1371 1979 int idx; 1980#endif 1981 /* this code was part of snd_ensoniq_create before intruduction 1982 * of suspend/resume 1983 */ 1984#ifdef CHIP1370 1985 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1986 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 1987 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE)); 1988 outl(ensoniq->dma_bug.addr, ES_REG(ensoniq, PHANTOM_FRAME)); 1989 outl(0, ES_REG(ensoniq, PHANTOM_COUNT)); 1990#else 1991 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1992 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 1993 outl(0, ES_REG(ensoniq, 1371_LEGACY)); 1994 if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack)) { 1995 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS)); 1996 /* need to delay around 20ms(bleech) to give 1997 some CODECs enough time to wakeup */ 1998 msleep(20); 1999 } 2000 /* AC'97 warm reset to start the bitclk */ 2001 outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL)); 2002 inl(ES_REG(ensoniq, CONTROL)); 2003 udelay(20); 2004 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 2005 /* Init the sample rate converter */ 2006 snd_es1371_wait_src_ready(ensoniq); 2007 outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE)); 2008 for (idx = 0; idx < 0x80; idx++) 2009 snd_es1371_src_write(ensoniq, idx, 0); 2010 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4); 2011 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10); 2012 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4); 2013 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10); 2014 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12); 2015 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12); 2016 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12); 2017 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12); 2018 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12); 2019 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12); 2020 snd_es1371_adc_rate(ensoniq, 22050); 2021 snd_es1371_dac1_rate(ensoniq, 22050); 2022 snd_es1371_dac2_rate(ensoniq, 22050); 2023 /* WARNING: 2024 * enabling the sample rate converter without properly programming 2025 * its parameters causes the chip to lock up (the SRC busy bit will 2026 * be stuck high, and I've found no way to rectify this other than 2027 * power cycle) - Thomas Sailer 2028 */ 2029 snd_es1371_wait_src_ready(ensoniq); 2030 outl(0, ES_REG(ensoniq, 1371_SMPRATE)); 2031 /* try reset codec directly */ 2032 outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC)); 2033#endif 2034 outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL)); 2035 outb(0x00, ES_REG(ensoniq, UART_RES)); 2036 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS)); 2037 synchronize_irq(ensoniq->irq); 2038} 2039 2040#ifdef CONFIG_PM 2041static int snd_ensoniq_suspend(struct pci_dev *pci, pm_message_t state) 2042{ 2043 struct snd_card *card = pci_get_drvdata(pci); 2044 struct ensoniq *ensoniq = card->private_data; 2045 2046 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 2047 2048 snd_pcm_suspend_all(ensoniq->pcm1); 2049 snd_pcm_suspend_all(ensoniq->pcm2); 2050 2051#ifdef CHIP1371 2052 snd_ac97_suspend(ensoniq->u.es1371.ac97); 2053#else 2054 /* try to reset AK4531 */ 2055 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC)); 2056 inw(ES_REG(ensoniq, 1370_CODEC)); 2057 udelay(100); 2058 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC)); 2059 inw(ES_REG(ensoniq, 1370_CODEC)); 2060 udelay(100); 2061 snd_ak4531_suspend(ensoniq->u.es1370.ak4531); 2062#endif 2063 2064 pci_disable_device(pci); 2065 pci_save_state(pci); 2066 pci_set_power_state(pci, pci_choose_state(pci, state)); 2067 return 0; 2068} 2069 2070static int snd_ensoniq_resume(struct pci_dev *pci) 2071{ 2072 struct snd_card *card = pci_get_drvdata(pci); 2073 struct ensoniq *ensoniq = card->private_data; 2074 2075 pci_set_power_state(pci, PCI_D0); 2076 pci_restore_state(pci); 2077 if (pci_enable_device(pci) < 0) { 2078 printk(KERN_ERR DRIVER_NAME ": pci_enable_device failed, " 2079 "disabling device\n"); 2080 snd_card_disconnect(card); 2081 return -EIO; 2082 } 2083 pci_set_master(pci); 2084 2085 snd_ensoniq_chip_init(ensoniq); 2086 2087#ifdef CHIP1371 2088 snd_ac97_resume(ensoniq->u.es1371.ac97); 2089#else 2090 snd_ak4531_resume(ensoniq->u.es1370.ak4531); 2091#endif 2092 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 2093 return 0; 2094} 2095#endif /* CONFIG_PM */ 2096 2097 2098static int __devinit snd_ensoniq_create(struct snd_card *card, 2099 struct pci_dev *pci, 2100 struct ensoniq ** rensoniq) 2101{ 2102 struct ensoniq *ensoniq; 2103 unsigned char cmdb; 2104 int err; 2105 static struct snd_device_ops ops = { 2106 .dev_free = snd_ensoniq_dev_free, 2107 }; 2108 2109 *rensoniq = NULL; 2110 if ((err = pci_enable_device(pci)) < 0) 2111 return err; 2112 ensoniq = kzalloc(sizeof(*ensoniq), GFP_KERNEL); 2113 if (ensoniq == NULL) { 2114 pci_disable_device(pci); 2115 return -ENOMEM; 2116 } 2117 spin_lock_init(&ensoniq->reg_lock); 2118 mutex_init(&ensoniq->src_mutex); 2119 ensoniq->card = card; 2120 ensoniq->pci = pci; 2121 ensoniq->irq = -1; 2122 if ((err = pci_request_regions(pci, "Ensoniq AudioPCI")) < 0) { 2123 kfree(ensoniq); 2124 pci_disable_device(pci); 2125 return err; 2126 } 2127 ensoniq->port = pci_resource_start(pci, 0); 2128 if (request_irq(pci->irq, snd_audiopci_interrupt, IRQF_SHARED, 2129 "Ensoniq AudioPCI", ensoniq)) { 2130 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); 2131 snd_ensoniq_free(ensoniq); 2132 return -EBUSY; 2133 } 2134 ensoniq->irq = pci->irq; 2135#ifdef CHIP1370 2136 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci), 2137 16, &ensoniq->dma_bug) < 0) { 2138 snd_printk(KERN_ERR "unable to allocate space for phantom area - dma_bug\n"); 2139 snd_ensoniq_free(ensoniq); 2140 return -EBUSY; 2141 } 2142#endif 2143 pci_set_master(pci); 2144 pci_read_config_byte(pci, PCI_REVISION_ID, &cmdb); 2145 ensoniq->rev = cmdb; 2146#ifdef CHIP1370 2147 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000)); 2148 ensoniq->sctrl = 0; 2149#else 2150 ensoniq->ctrl = 0; 2151 ensoniq->sctrl = 0; 2152 ensoniq->cssr = 0; 2153 if (snd_pci_quirk_lookup(pci, es1371_amplifier_hack)) 2154 ensoniq->ctrl |= ES_1371_GPIO_OUT(1); /* turn amplifier on */ 2155 2156 if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack)) 2157 ensoniq->cssr |= ES_1371_ST_AC97_RST; 2158#endif 2159 2160 snd_ensoniq_chip_init(ensoniq); 2161 2162 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ensoniq, &ops)) < 0) { 2163 snd_ensoniq_free(ensoniq); 2164 return err; 2165 } 2166 2167 snd_ensoniq_proc_init(ensoniq); 2168 2169 snd_card_set_dev(card, &pci->dev); 2170 2171 *rensoniq = ensoniq; 2172 return 0; 2173} 2174 2175/* 2176 * MIDI section 2177 */ 2178 2179static void snd_ensoniq_midi_interrupt(struct ensoniq * ensoniq) 2180{ 2181 struct snd_rawmidi *rmidi = ensoniq->rmidi; 2182 unsigned char status, mask, byte; 2183 2184 if (rmidi == NULL) 2185 return; 2186 /* do Rx at first */ 2187 spin_lock(&ensoniq->reg_lock); 2188 mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0; 2189 while (mask) { 2190 status = inb(ES_REG(ensoniq, UART_STATUS)); 2191 if ((status & mask) == 0) 2192 break; 2193 byte = inb(ES_REG(ensoniq, UART_DATA)); 2194 snd_rawmidi_receive(ensoniq->midi_input, &byte, 1); 2195 } 2196 spin_unlock(&ensoniq->reg_lock); 2197 2198 /* do Tx at second */ 2199 spin_lock(&ensoniq->reg_lock); 2200 mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0; 2201 while (mask) { 2202 status = inb(ES_REG(ensoniq, UART_STATUS)); 2203 if ((status & mask) == 0) 2204 break; 2205 if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) { 2206 ensoniq->uartc &= ~ES_TXINTENM; 2207 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); 2208 mask &= ~ES_TXRDY; 2209 } else { 2210 outb(byte, ES_REG(ensoniq, UART_DATA)); 2211 } 2212 } 2213 spin_unlock(&ensoniq->reg_lock); 2214} 2215 2216static int snd_ensoniq_midi_input_open(struct snd_rawmidi_substream *substream) 2217{ 2218 struct ensoniq *ensoniq = substream->rmidi->private_data; 2219 2220 spin_lock_irq(&ensoniq->reg_lock); 2221 ensoniq->uartm |= ES_MODE_INPUT; 2222 ensoniq->midi_input = substream; 2223 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) { 2224 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL)); 2225 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL)); 2226 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL)); 2227 } 2228 spin_unlock_irq(&ensoniq->reg_lock); 2229 return 0; 2230} 2231 2232static int snd_ensoniq_midi_input_close(struct snd_rawmidi_substream *substream) 2233{ 2234 struct ensoniq *ensoniq = substream->rmidi->private_data; 2235 2236 spin_lock_irq(&ensoniq->reg_lock); 2237 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) { 2238 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL)); 2239 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL)); 2240 } else { 2241 outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL)); 2242 } 2243 ensoniq->midi_input = NULL; 2244 ensoniq->uartm &= ~ES_MODE_INPUT; 2245 spin_unlock_irq(&ensoniq->reg_lock); 2246 return 0; 2247} 2248 2249static int snd_ensoniq_midi_output_open(struct snd_rawmidi_substream *substream) 2250{ 2251 struct ensoniq *ensoniq = substream->rmidi->private_data; 2252 2253 spin_lock_irq(&ensoniq->reg_lock); 2254 ensoniq->uartm |= ES_MODE_OUTPUT; 2255 ensoniq->midi_output = substream; 2256 if (!(ensoniq->uartm & ES_MODE_INPUT)) { 2257 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL)); 2258 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL)); 2259 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL)); 2260 } 2261 spin_unlock_irq(&ensoniq->reg_lock); 2262 return 0; 2263} 2264 2265static int snd_ensoniq_midi_output_close(struct snd_rawmidi_substream *substream) 2266{ 2267 struct ensoniq *ensoniq = substream->rmidi->private_data; 2268 2269 spin_lock_irq(&ensoniq->reg_lock); 2270 if (!(ensoniq->uartm & ES_MODE_INPUT)) { 2271 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL)); 2272 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL)); 2273 } else { 2274 outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL)); 2275 } 2276 ensoniq->midi_output = NULL; 2277 ensoniq->uartm &= ~ES_MODE_OUTPUT; 2278 spin_unlock_irq(&ensoniq->reg_lock); 2279 return 0; 2280} 2281 2282static void snd_ensoniq_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) 2283{ 2284 unsigned long flags; 2285 struct ensoniq *ensoniq = substream->rmidi->private_data; 2286 int idx; 2287 2288 spin_lock_irqsave(&ensoniq->reg_lock, flags); 2289 if (up) { 2290 if ((ensoniq->uartc & ES_RXINTEN) == 0) { 2291 /* empty input FIFO */ 2292 for (idx = 0; idx < 32; idx++) 2293 inb(ES_REG(ensoniq, UART_DATA)); 2294 ensoniq->uartc |= ES_RXINTEN; 2295 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); 2296 } 2297 } else { 2298 if (ensoniq->uartc & ES_RXINTEN) { 2299 ensoniq->uartc &= ~ES_RXINTEN; 2300 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); 2301 } 2302 } 2303 spin_unlock_irqrestore(&ensoniq->reg_lock, flags); 2304} 2305 2306static void snd_ensoniq_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) 2307{ 2308 unsigned long flags; 2309 struct ensoniq *ensoniq = substream->rmidi->private_data; 2310 unsigned char byte; 2311 2312 spin_lock_irqsave(&ensoniq->reg_lock, flags); 2313 if (up) { 2314 if (ES_TXINTENI(ensoniq->uartc) == 0) { 2315 ensoniq->uartc |= ES_TXINTENO(1); 2316 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */ 2317 while (ES_TXINTENI(ensoniq->uartc) == 1 && 2318 (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) { 2319 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) { 2320 ensoniq->uartc &= ~ES_TXINTENM; 2321 } else { 2322 outb(byte, ES_REG(ensoniq, UART_DATA)); 2323 } 2324 } 2325 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); 2326 } 2327 } else { 2328 if (ES_TXINTENI(ensoniq->uartc) == 1) { 2329 ensoniq->uartc &= ~ES_TXINTENM; 2330 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); 2331 } 2332 } 2333 spin_unlock_irqrestore(&ensoniq->reg_lock, flags); 2334} 2335 2336static struct snd_rawmidi_ops snd_ensoniq_midi_output = 2337{ 2338 .open = snd_ensoniq_midi_output_open, 2339 .close = snd_ensoniq_midi_output_close, 2340 .trigger = snd_ensoniq_midi_output_trigger, 2341}; 2342 2343static struct snd_rawmidi_ops snd_ensoniq_midi_input = 2344{ 2345 .open = snd_ensoniq_midi_input_open, 2346 .close = snd_ensoniq_midi_input_close, 2347 .trigger = snd_ensoniq_midi_input_trigger, 2348}; 2349 2350static int __devinit snd_ensoniq_midi(struct ensoniq * ensoniq, int device, 2351 struct snd_rawmidi **rrawmidi) 2352{ 2353 struct snd_rawmidi *rmidi; 2354 int err; 2355 2356 if (rrawmidi) 2357 *rrawmidi = NULL; 2358 if ((err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi)) < 0) 2359 return err; 2360#ifdef CHIP1370 2361 strcpy(rmidi->name, "ES1370"); 2362#else 2363 strcpy(rmidi->name, "ES1371"); 2364#endif 2365 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output); 2366 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input); 2367 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | 2368 SNDRV_RAWMIDI_INFO_DUPLEX; 2369 rmidi->private_data = ensoniq; 2370 ensoniq->rmidi = rmidi; 2371 if (rrawmidi) 2372 *rrawmidi = rmidi; 2373 return 0; 2374} 2375 2376/* 2377 * Interrupt handler 2378 */ 2379 2380static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id) 2381{ 2382 struct ensoniq *ensoniq = dev_id; 2383 unsigned int status, sctrl; 2384 2385 if (ensoniq == NULL) 2386 return IRQ_NONE; 2387 2388 status = inl(ES_REG(ensoniq, STATUS)); 2389 if (!(status & ES_INTR)) 2390 return IRQ_NONE; 2391 2392 spin_lock(&ensoniq->reg_lock); 2393 sctrl = ensoniq->sctrl; 2394 if (status & ES_DAC1) 2395 sctrl &= ~ES_P1_INT_EN; 2396 if (status & ES_DAC2) 2397 sctrl &= ~ES_P2_INT_EN; 2398 if (status & ES_ADC) 2399 sctrl &= ~ES_R1_INT_EN; 2400 outl(sctrl, ES_REG(ensoniq, SERIAL)); 2401 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 2402 spin_unlock(&ensoniq->reg_lock); 2403 2404 if (status & ES_UART) 2405 snd_ensoniq_midi_interrupt(ensoniq); 2406 if ((status & ES_DAC2) && ensoniq->playback2_substream) 2407 snd_pcm_period_elapsed(ensoniq->playback2_substream); 2408 if ((status & ES_ADC) && ensoniq->capture_substream) 2409 snd_pcm_period_elapsed(ensoniq->capture_substream); 2410 if ((status & ES_DAC1) && ensoniq->playback1_substream) 2411 snd_pcm_period_elapsed(ensoniq->playback1_substream); 2412 return IRQ_HANDLED; 2413} 2414 2415static int __devinit snd_audiopci_probe(struct pci_dev *pci, 2416 const struct pci_device_id *pci_id) 2417{ 2418 static int dev; 2419 struct snd_card *card; 2420 struct ensoniq *ensoniq; 2421 int err, pcm_devs[2]; 2422 2423 if (dev >= SNDRV_CARDS) 2424 return -ENODEV; 2425 if (!enable[dev]) { 2426 dev++; 2427 return -ENOENT; 2428 } 2429 2430 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0); 2431 if (card == NULL) 2432 return -ENOMEM; 2433 2434 if ((err = snd_ensoniq_create(card, pci, &ensoniq)) < 0) { 2435 snd_card_free(card); 2436 return err; 2437 } 2438 card->private_data = ensoniq; 2439 2440 pcm_devs[0] = 0; pcm_devs[1] = 1; 2441#ifdef CHIP1370 2442 if ((err = snd_ensoniq_1370_mixer(ensoniq)) < 0) { 2443 snd_card_free(card); 2444 return err; 2445 } 2446#endif 2447#ifdef CHIP1371 2448 if ((err = snd_ensoniq_1371_mixer(ensoniq, spdif[dev], lineio[dev])) < 0) { 2449 snd_card_free(card); 2450 return err; 2451 } 2452#endif 2453 if ((err = snd_ensoniq_pcm(ensoniq, 0, NULL)) < 0) { 2454 snd_card_free(card); 2455 return err; 2456 } 2457 if ((err = snd_ensoniq_pcm2(ensoniq, 1, NULL)) < 0) { 2458 snd_card_free(card); 2459 return err; 2460 } 2461 if ((err = snd_ensoniq_midi(ensoniq, 0, NULL)) < 0) { 2462 snd_card_free(card); 2463 return err; 2464 } 2465 2466 snd_ensoniq_create_gameport(ensoniq, dev); 2467 2468 strcpy(card->driver, DRIVER_NAME); 2469 2470 strcpy(card->shortname, "Ensoniq AudioPCI"); 2471 sprintf(card->longname, "%s %s at 0x%lx, irq %i", 2472 card->shortname, 2473 card->driver, 2474 ensoniq->port, 2475 ensoniq->irq); 2476 2477 if ((err = snd_card_register(card)) < 0) { 2478 snd_card_free(card); 2479 return err; 2480 } 2481 2482 pci_set_drvdata(pci, card); 2483 dev++; 2484 return 0; 2485} 2486 2487static void __devexit snd_audiopci_remove(struct pci_dev *pci) 2488{ 2489 snd_card_free(pci_get_drvdata(pci)); 2490 pci_set_drvdata(pci, NULL); 2491} 2492 2493static struct pci_driver driver = { 2494 .name = DRIVER_NAME, 2495 .id_table = snd_audiopci_ids, 2496 .probe = snd_audiopci_probe, 2497 .remove = __devexit_p(snd_audiopci_remove), 2498#ifdef CONFIG_PM 2499 .suspend = snd_ensoniq_suspend, 2500 .resume = snd_ensoniq_resume, 2501#endif 2502}; 2503 2504static int __init alsa_card_ens137x_init(void) 2505{ 2506 return pci_register_driver(&driver); 2507} 2508 2509static void __exit alsa_card_ens137x_exit(void) 2510{ 2511 pci_unregister_driver(&driver); 2512} 2513 2514module_init(alsa_card_ens137x_init) 2515module_exit(alsa_card_ens137x_exit) 2516