1/* 2 * Driver for C-Media CMI8338 and 8738 PCI soundcards. 3 * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20/* Does not work. Warning may block system in capture mode */ 21/* #define USE_VAR48KRATE */ 22 23#include <sound/driver.h> 24#include <asm/io.h> 25#include <linux/delay.h> 26#include <linux/interrupt.h> 27#include <linux/init.h> 28#include <linux/pci.h> 29#include <linux/slab.h> 30#include <linux/gameport.h> 31#include <linux/moduleparam.h> 32#include <linux/mutex.h> 33#include <sound/core.h> 34#include <sound/info.h> 35#include <sound/control.h> 36#include <sound/pcm.h> 37#include <sound/rawmidi.h> 38#include <sound/mpu401.h> 39#include <sound/opl3.h> 40#include <sound/sb.h> 41#include <sound/asoundef.h> 42#include <sound/initval.h> 43 44MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>"); 45MODULE_DESCRIPTION("C-Media CMI8x38 PCI"); 46MODULE_LICENSE("GPL"); 47MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738}," 48 "{C-Media,CMI8738B}," 49 "{C-Media,CMI8338A}," 50 "{C-Media,CMI8338B}}"); 51 52#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE)) 53#define SUPPORT_JOYSTICK 1 54#endif 55 56static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 57static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 58static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */ 59static long mpu_port[SNDRV_CARDS]; 60static long fm_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1}; 61static int soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1}; 62#ifdef SUPPORT_JOYSTICK 63static int joystick_port[SNDRV_CARDS]; 64#endif 65 66module_param_array(index, int, NULL, 0444); 67MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard."); 68module_param_array(id, charp, NULL, 0444); 69MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard."); 70module_param_array(enable, bool, NULL, 0444); 71MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard."); 72module_param_array(mpu_port, long, NULL, 0444); 73MODULE_PARM_DESC(mpu_port, "MPU-401 port."); 74module_param_array(fm_port, long, NULL, 0444); 75MODULE_PARM_DESC(fm_port, "FM port."); 76module_param_array(soft_ac3, bool, NULL, 0444); 77MODULE_PARM_DESC(soft_ac3, "Sofware-conversion of raw SPDIF packets (model 033 only)."); 78#ifdef SUPPORT_JOYSTICK 79module_param_array(joystick_port, int, NULL, 0444); 80MODULE_PARM_DESC(joystick_port, "Joystick port address."); 81#endif 82 83/* 84 * CM8x38 registers definition 85 */ 86 87#define CM_REG_FUNCTRL0 0x00 88#define CM_RST_CH1 0x00080000 89#define CM_RST_CH0 0x00040000 90#define CM_CHEN1 0x00020000 /* ch1: enable */ 91#define CM_CHEN0 0x00010000 /* ch0: enable */ 92#define CM_PAUSE1 0x00000008 /* ch1: pause */ 93#define CM_PAUSE0 0x00000004 /* ch0: pause */ 94#define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */ 95#define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */ 96 97#define CM_REG_FUNCTRL1 0x04 98#define CM_ASFC_MASK 0x0000E000 /* ADC sampling frequency */ 99#define CM_ASFC_SHIFT 13 100#define CM_DSFC_MASK 0x00001C00 /* DAC sampling frequency */ 101#define CM_DSFC_SHIFT 10 102#define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */ 103#define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */ 104#define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/OUT -> IN loopback */ 105#define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */ 106#define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */ 107#define CM_BREQ 0x00000010 /* bus master enabled */ 108#define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */ 109#define CM_UART_EN 0x00000004 /* UART */ 110#define CM_JYSTK_EN 0x00000002 /* joy stick */ 111 112#define CM_REG_CHFORMAT 0x08 113 114#define CM_CHB3D5C 0x80000000 /* 5,6 channels */ 115#define CM_CHB3D 0x20000000 /* 4 channels */ 116 117#define CM_CHIP_MASK1 0x1f000000 118#define CM_CHIP_037 0x01000000 119 120#define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */ 121#define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */ 122#define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */ 123/* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */ 124 125#define CM_ADCBITLEN_MASK 0x0000C000 126#define CM_ADCBITLEN_16 0x00000000 127#define CM_ADCBITLEN_15 0x00004000 128#define CM_ADCBITLEN_14 0x00008000 129#define CM_ADCBITLEN_13 0x0000C000 130 131#define CM_ADCDACLEN_MASK 0x00003000 132#define CM_ADCDACLEN_060 0x00000000 133#define CM_ADCDACLEN_066 0x00001000 134#define CM_ADCDACLEN_130 0x00002000 135#define CM_ADCDACLEN_280 0x00003000 136 137#define CM_CH1_SRATE_176K 0x00000800 138#define CM_CH1_SRATE_88K 0x00000400 139#define CM_CH0_SRATE_176K 0x00000200 140#define CM_CH0_SRATE_88K 0x00000100 141 142#define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */ 143 144#define CM_CH1FMT_MASK 0x0000000C 145#define CM_CH1FMT_SHIFT 2 146#define CM_CH0FMT_MASK 0x00000003 147#define CM_CH0FMT_SHIFT 0 148 149#define CM_REG_INT_HLDCLR 0x0C 150#define CM_CHIP_MASK2 0xff000000 151#define CM_CHIP_039 0x04000000 152#define CM_CHIP_039_6CH 0x01000000 153#define CM_CHIP_055 0x08000000 154#define CM_CHIP_8768 0x20000000 155#define CM_TDMA_INT_EN 0x00040000 156#define CM_CH1_INT_EN 0x00020000 157#define CM_CH0_INT_EN 0x00010000 158#define CM_INT_HOLD 0x00000002 159#define CM_INT_CLEAR 0x00000001 160 161#define CM_REG_INT_STATUS 0x10 162#define CM_INTR 0x80000000 163#define CM_VCO 0x08000000 /* Voice Control? CMI8738 */ 164#define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */ 165#define CM_UARTINT 0x00010000 166#define CM_LTDMAINT 0x00008000 167#define CM_HTDMAINT 0x00004000 168#define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */ 169#define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */ 170#define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */ 171#define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */ 172#define CM_CH1BUSY 0x00000008 173#define CM_CH0BUSY 0x00000004 174#define CM_CHINT1 0x00000002 175#define CM_CHINT0 0x00000001 176 177#define CM_REG_LEGACY_CTRL 0x14 178#define CM_NXCHG 0x80000000 /* h/w multi channels? */ 179#define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */ 180#define CM_VMPU_330 0x00000000 181#define CM_VMPU_320 0x20000000 182#define CM_VMPU_310 0x40000000 183#define CM_VMPU_300 0x60000000 184#define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */ 185#define CM_VSBSEL_220 0x00000000 186#define CM_VSBSEL_240 0x04000000 187#define CM_VSBSEL_260 0x08000000 188#define CM_VSBSEL_280 0x0C000000 189#define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */ 190#define CM_FMSEL_388 0x00000000 191#define CM_FMSEL_3C8 0x01000000 192#define CM_FMSEL_3E0 0x02000000 193#define CM_FMSEL_3E8 0x03000000 194#define CM_ENSPDOUT 0x00800000 /* enable XPDIF/OUT to I/O interface */ 195#define CM_SPDCOPYRHT 0x00400000 /* set copyright spdif in/out */ 196#define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */ 197#define CM_SETRETRY 0x00010000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */ 198#define CM_CHB3D6C 0x00008000 /* 5.1 channels support */ 199#define CM_LINE_AS_BASS 0x00006000 /* use line-in as bass */ 200 201#define CM_REG_MISC_CTRL 0x18 202#define CM_PWD 0x80000000 203#define CM_RESET 0x40000000 204#define CM_SFIL_MASK 0x30000000 205#define CM_TXVX 0x08000000 206#define CM_N4SPK3D 0x04000000 /* 4ch output */ 207#define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */ 208#define CM_SPDIF48K 0x01000000 /* write */ 209#define CM_SPATUS48K 0x01000000 /* read */ 210#define CM_ENDBDAC 0x00800000 /* enable dual dac */ 211#define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */ 212#define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */ 213#define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-IN -> int. OUT */ 214#define CM_FM_EN 0x00080000 /* enalbe FM */ 215#define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */ 216#define CM_VIDWPDSB 0x00010000 217#define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */ 218#define CM_MASK_EN 0x00004000 219#define CM_VIDWPPRT 0x00002000 220#define CM_SFILENB 0x00001000 221#define CM_MMODE_MASK 0x00000E00 222#define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */ 223#define CM_ENCENTER 0x00000080 224#define CM_FLINKON 0x00000040 225#define CM_FLINKOFF 0x00000020 226#define CM_MIDSMP 0x00000010 227#define CM_UPDDMA_MASK 0x0000000C 228#define CM_TWAIT_MASK 0x00000003 229 230 /* byte */ 231#define CM_REG_MIXER0 0x20 232 233#define CM_REG_SB16_DATA 0x22 234#define CM_REG_SB16_ADDR 0x23 235 236#define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */ 237#define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */ 238#define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */ 239#define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */ 240 241#define CM_REG_MIXER1 0x24 242#define CM_FMMUTE 0x80 /* mute FM */ 243#define CM_FMMUTE_SHIFT 7 244#define CM_WSMUTE 0x40 /* mute PCM */ 245#define CM_WSMUTE_SHIFT 6 246#define CM_SPK4 0x20 /* lin-in -> rear line out */ 247#define CM_SPK4_SHIFT 5 248#define CM_REAR2FRONT 0x10 /* exchange rear/front */ 249#define CM_REAR2FRONT_SHIFT 4 250#define CM_WAVEINL 0x08 /* digital wave rec. left chan */ 251#define CM_WAVEINL_SHIFT 3 252#define CM_WAVEINR 0x04 /* digical wave rec. right */ 253#define CM_WAVEINR_SHIFT 2 254#define CM_X3DEN 0x02 /* 3D surround enable */ 255#define CM_X3DEN_SHIFT 1 256#define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */ 257#define CM_CDPLAY_SHIFT 0 258 259#define CM_REG_MIXER2 0x25 260#define CM_RAUXREN 0x80 /* AUX right capture */ 261#define CM_RAUXREN_SHIFT 7 262#define CM_RAUXLEN 0x40 /* AUX left capture */ 263#define CM_RAUXLEN_SHIFT 6 264#define CM_VAUXRM 0x20 /* AUX right mute */ 265#define CM_VAUXRM_SHIFT 5 266#define CM_VAUXLM 0x10 /* AUX left mute */ 267#define CM_VAUXLM_SHIFT 4 268#define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */ 269#define CM_VADMIC_SHIFT 1 270#define CM_MICGAINZ 0x01 /* mic boost */ 271#define CM_MICGAINZ_SHIFT 0 272 273#define CM_REG_MIXER3 0x24 274#define CM_REG_AUX_VOL 0x26 275#define CM_VAUXL_MASK 0xf0 276#define CM_VAUXR_MASK 0x0f 277 278#define CM_REG_MISC 0x27 279#define CM_XGPO1 0x20 280// #define CM_XGPBIO 0x04 281#define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */ 282#define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */ 283#define CM_SPDVALID 0x02 /* spdif input valid check */ 284#define CM_DMAUTO 0x01 285 286#define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */ 287/* 288 * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738 289 * or identical with AC97 codec? 290 */ 291#define CM_REG_EXTERN_CODEC CM_REG_AC97 292 293/* 294 * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6) 295 */ 296#define CM_REG_MPU_PCI 0x40 297 298/* 299 * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6) 300 */ 301#define CM_REG_FM_PCI 0x50 302 303/* 304 * access from SB-mixer port 305 */ 306#define CM_REG_EXTENT_IND 0xf0 307#define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */ 308#define CM_VPHONE_SHIFT 5 309#define CM_VPHOM 0x10 /* Phone mute control */ 310#define CM_VSPKM 0x08 /* Speaker mute control, default high */ 311#define CM_RLOOPREN 0x04 /* Rec. R-channel enable */ 312#define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */ 313#define CM_VADMIC3 0x01 /* Mic record boost */ 314 315/* 316 * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738): 317 * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL 318 * unit (readonly?). 319 */ 320#define CM_REG_PLL 0xf8 321 322/* 323 * extended registers 324 */ 325#define CM_REG_CH0_FRAME1 0x80 /* base address */ 326#define CM_REG_CH0_FRAME2 0x84 327#define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */ 328#define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */ 329#define CM_REG_EXT_MISC 0x90 330#define CM_REG_MISC_CTRL_8768 0x92 /* reg. name the same as 0x18 */ 331#define CM_CHB3D8C 0x20 /* 7.1 channels support */ 332#define CM_SPD32FMT 0x10 /* SPDIF/IN 32k */ 333#define CM_ADC2SPDIF 0x08 /* ADC output to SPDIF/OUT */ 334#define CM_SHAREADC 0x04 /* DAC in ADC as Center/LFE */ 335#define CM_REALTCMP 0x02 /* monitor the CMPL/CMPR of ADC */ 336#define CM_INVLRCK 0x01 /* invert ZVPORT's LRCK */ 337 338/* 339 * size of i/o region 340 */ 341#define CM_EXTENT_CODEC 0x100 342#define CM_EXTENT_MIDI 0x2 343#define CM_EXTENT_SYNTH 0x4 344 345 346/* 347 * channels for playback / capture 348 */ 349#define CM_CH_PLAY 0 350#define CM_CH_CAPT 1 351 352/* 353 * flags to check device open/close 354 */ 355#define CM_OPEN_NONE 0 356#define CM_OPEN_CH_MASK 0x01 357#define CM_OPEN_DAC 0x10 358#define CM_OPEN_ADC 0x20 359#define CM_OPEN_SPDIF 0x40 360#define CM_OPEN_MCHAN 0x80 361#define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC) 362#define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC) 363#define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN) 364#define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC) 365#define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF) 366#define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF) 367 368 369#if CM_CH_PLAY == 1 370#define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K 371#define CM_PLAYBACK_SPDF CM_SPDF_1 372#define CM_CAPTURE_SPDF CM_SPDF_0 373#else 374#define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K 375#define CM_PLAYBACK_SPDF CM_SPDF_0 376#define CM_CAPTURE_SPDF CM_SPDF_1 377#endif 378 379 380/* 381 * driver data 382 */ 383 384struct cmipci_pcm { 385 struct snd_pcm_substream *substream; 386 int running; /* dac/adc running? */ 387 unsigned int dma_size; /* in frames */ 388 unsigned int period_size; /* in frames */ 389 unsigned int offset; /* physical address of the buffer */ 390 unsigned int fmt; /* format bits */ 391 int ch; /* channel (0/1) */ 392 unsigned int is_dac; /* is dac? */ 393 int bytes_per_frame; 394 int shift; 395}; 396 397/* mixer elements toggled/resumed during ac3 playback */ 398struct cmipci_mixer_auto_switches { 399 const char *name; /* switch to toggle */ 400 int toggle_on; /* value to change when ac3 mode */ 401}; 402static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = { 403 {"PCM Playback Switch", 0}, 404 {"IEC958 Output Switch", 1}, 405 {"IEC958 Mix Analog", 0}, 406 // {"IEC958 Out To DAC", 1}, // no longer used 407 {"IEC958 Loop", 0}, 408}; 409#define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer) 410 411struct cmipci { 412 struct snd_card *card; 413 414 struct pci_dev *pci; 415 unsigned int device; /* device ID */ 416 int irq; 417 418 unsigned long iobase; 419 unsigned int ctrl; /* FUNCTRL0 current value */ 420 421 struct snd_pcm *pcm; /* DAC/ADC PCM */ 422 struct snd_pcm *pcm2; /* 2nd DAC */ 423 struct snd_pcm *pcm_spdif; /* SPDIF */ 424 425 int chip_version; 426 int max_channels; 427 unsigned int has_dual_dac: 1; 428 unsigned int can_ac3_sw: 1; 429 unsigned int can_ac3_hw: 1; 430 unsigned int can_multi_ch: 1; 431 unsigned int do_soft_ac3: 1; 432 433 unsigned int spdif_playback_avail: 1; /* spdif ready? */ 434 unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */ 435 int spdif_counter; /* for software AC3 */ 436 437 unsigned int dig_status; 438 unsigned int dig_pcm_status; 439 440 struct snd_pcm_hardware *hw_info[3]; /* for playbacks */ 441 442 int opened[2]; /* open mode */ 443 struct mutex open_mutex; 444 445 unsigned int mixer_insensitive: 1; 446 struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS]; 447 int mixer_res_status[CM_SAVED_MIXERS]; 448 449 struct cmipci_pcm channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */ 450 451 /* external MIDI */ 452 struct snd_rawmidi *rmidi; 453 454#ifdef SUPPORT_JOYSTICK 455 struct gameport *gameport; 456#endif 457 458 spinlock_t reg_lock; 459 460#ifdef CONFIG_PM 461 unsigned int saved_regs[0x20]; 462 unsigned char saved_mixers[0x20]; 463#endif 464}; 465 466 467/* read/write operations for dword register */ 468static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data) 469{ 470 outl(data, cm->iobase + cmd); 471} 472 473static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd) 474{ 475 return inl(cm->iobase + cmd); 476} 477 478/* read/write operations for word register */ 479static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data) 480{ 481 outw(data, cm->iobase + cmd); 482} 483 484static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd) 485{ 486 return inw(cm->iobase + cmd); 487} 488 489/* read/write operations for byte register */ 490static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data) 491{ 492 outb(data, cm->iobase + cmd); 493} 494 495static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd) 496{ 497 return inb(cm->iobase + cmd); 498} 499 500/* bit operations for dword register */ 501static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag) 502{ 503 unsigned int val, oval; 504 val = oval = inl(cm->iobase + cmd); 505 val |= flag; 506 if (val == oval) 507 return 0; 508 outl(val, cm->iobase + cmd); 509 return 1; 510} 511 512static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag) 513{ 514 unsigned int val, oval; 515 val = oval = inl(cm->iobase + cmd); 516 val &= ~flag; 517 if (val == oval) 518 return 0; 519 outl(val, cm->iobase + cmd); 520 return 1; 521} 522 523/* bit operations for byte register */ 524static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag) 525{ 526 unsigned char val, oval; 527 val = oval = inb(cm->iobase + cmd); 528 val |= flag; 529 if (val == oval) 530 return 0; 531 outb(val, cm->iobase + cmd); 532 return 1; 533} 534 535static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag) 536{ 537 unsigned char val, oval; 538 val = oval = inb(cm->iobase + cmd); 539 val &= ~flag; 540 if (val == oval) 541 return 0; 542 outb(val, cm->iobase + cmd); 543 return 1; 544} 545 546 547/* 548 * PCM interface 549 */ 550 551/* 552 * calculate frequency 553 */ 554 555static unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 }; 556 557static unsigned int snd_cmipci_rate_freq(unsigned int rate) 558{ 559 unsigned int i; 560 for (i = 0; i < ARRAY_SIZE(rates); i++) { 561 if (rates[i] == rate) 562 return i; 563 } 564 snd_BUG(); 565 return 0; 566} 567 568#ifdef USE_VAR48KRATE 569/* 570 * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???) 571 * does it this way .. maybe not. Never get any information from C-Media about 572 * that <werner@suse.de>. 573 */ 574static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n) 575{ 576 unsigned int delta, tolerance; 577 int xm, xn, xr; 578 579 for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5)) 580 rate <<= 1; 581 *n = -1; 582 if (*r > 0xff) 583 goto out; 584 tolerance = rate*CM_TOLERANCE_RATE; 585 586 for (xn = (1+2); xn < (0x1f+2); xn++) { 587 for (xm = (1+2); xm < (0xff+2); xm++) { 588 xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn; 589 590 if (xr < rate) 591 delta = rate - xr; 592 else 593 delta = xr - rate; 594 595 /* 596 * If we found one, remember this, 597 * and try to find a closer one 598 */ 599 if (delta < tolerance) { 600 tolerance = delta; 601 *m = xm - 2; 602 *n = xn - 2; 603 } 604 } 605 } 606out: 607 return (*n > -1); 608} 609 610/* 611 * Program pll register bits, I assume that the 8 registers 0xf8 upto 0xff 612 * are mapped onto the 8 ADC/DAC sampling frequency which can be choosen 613 * at the register CM_REG_FUNCTRL1 (0x04). 614 * Problem: other ways are also possible (any information about that?) 615 */ 616static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot) 617{ 618 unsigned int reg = CM_REG_PLL + slot; 619 /* 620 * Guess that this programs at reg. 0x04 the pos 15:13/12:10 621 * for DSFC/ASFC (000 upto 111). 622 */ 623 624 625 snd_cmipci_write_b(cm, reg, rate>>8); 626 snd_cmipci_write_b(cm, reg, rate&0xff); 627 628} 629#endif /* USE_VAR48KRATE */ 630 631static int snd_cmipci_hw_params(struct snd_pcm_substream *substream, 632 struct snd_pcm_hw_params *hw_params) 633{ 634 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 635} 636 637static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream, 638 struct snd_pcm_hw_params *hw_params) 639{ 640 struct cmipci *cm = snd_pcm_substream_chip(substream); 641 if (params_channels(hw_params) > 2) { 642 mutex_lock(&cm->open_mutex); 643 if (cm->opened[CM_CH_PLAY]) { 644 mutex_unlock(&cm->open_mutex); 645 return -EBUSY; 646 } 647 /* reserve the channel A */ 648 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI; 649 mutex_unlock(&cm->open_mutex); 650 } 651 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 652} 653 654static void snd_cmipci_ch_reset(struct cmipci *cm, int ch) 655{ 656 int reset = CM_RST_CH0 << (cm->channel[ch].ch); 657 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset); 658 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset); 659 udelay(10); 660} 661 662static int snd_cmipci_hw_free(struct snd_pcm_substream *substream) 663{ 664 return snd_pcm_lib_free_pages(substream); 665} 666 667 668/* 669 */ 670 671static unsigned int hw_channels[] = {1, 2, 4, 5, 6, 8}; 672static struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = { 673 .count = 3, 674 .list = hw_channels, 675 .mask = 0, 676}; 677static struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = { 678 .count = 5, 679 .list = hw_channels, 680 .mask = 0, 681}; 682static struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = { 683 .count = 6, 684 .list = hw_channels, 685 .mask = 0, 686}; 687 688static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels) 689{ 690 if (channels > 2) { 691 if (! cm->can_multi_ch) 692 return -EINVAL; 693 if (rec->fmt != 0x03) /* stereo 16bit only */ 694 return -EINVAL; 695 696 spin_lock_irq(&cm->reg_lock); 697 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG); 698 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); 699 if (channels > 4) { 700 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D); 701 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C); 702 } else { 703 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C); 704 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D); 705 } 706 if (channels >= 6) { 707 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C); 708 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER); 709 } else { 710 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C); 711 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER); 712 } 713 if (cm->chip_version == 68) { 714 if (channels == 8) { 715 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL_8768, CM_CHB3D8C); 716 } else { 717 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL_8768, CM_CHB3D8C); 718 } 719 } 720 spin_unlock_irq(&cm->reg_lock); 721 722 } else { 723 if (cm->can_multi_ch) { 724 spin_lock_irq(&cm->reg_lock); 725 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG); 726 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D); 727 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C); 728 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C); 729 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER); 730 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); 731 spin_unlock_irq(&cm->reg_lock); 732 } 733 } 734 return 0; 735} 736 737 738/* 739 * prepare playback/capture channel 740 * channel to be used must have been set in rec->ch. 741 */ 742static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec, 743 struct snd_pcm_substream *substream) 744{ 745 unsigned int reg, freq, val; 746 struct snd_pcm_runtime *runtime = substream->runtime; 747 748 rec->fmt = 0; 749 rec->shift = 0; 750 if (snd_pcm_format_width(runtime->format) >= 16) { 751 rec->fmt |= 0x02; 752 if (snd_pcm_format_width(runtime->format) > 16) 753 rec->shift++; /* 24/32bit */ 754 } 755 if (runtime->channels > 1) 756 rec->fmt |= 0x01; 757 if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) { 758 snd_printd("cannot set dac channels\n"); 759 return -EINVAL; 760 } 761 762 rec->offset = runtime->dma_addr; 763 /* buffer and period sizes in frame */ 764 rec->dma_size = runtime->buffer_size << rec->shift; 765 rec->period_size = runtime->period_size << rec->shift; 766 if (runtime->channels > 2) { 767 /* multi-channels */ 768 rec->dma_size = (rec->dma_size * runtime->channels) / 2; 769 rec->period_size = (rec->period_size * runtime->channels) / 2; 770 } 771 772 spin_lock_irq(&cm->reg_lock); 773 774 /* set buffer address */ 775 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1; 776 snd_cmipci_write(cm, reg, rec->offset); 777 /* program sample counts */ 778 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2; 779 snd_cmipci_write_w(cm, reg, rec->dma_size - 1); 780 snd_cmipci_write_w(cm, reg + 2, rec->period_size - 1); 781 782 /* set adc/dac flag */ 783 val = rec->ch ? CM_CHADC1 : CM_CHADC0; 784 if (rec->is_dac) 785 cm->ctrl &= ~val; 786 else 787 cm->ctrl |= val; 788 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); 789 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl); 790 791 /* set sample rate */ 792 freq = snd_cmipci_rate_freq(runtime->rate); 793 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1); 794 if (rec->ch) { 795 val &= ~CM_ASFC_MASK; 796 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK; 797 } else { 798 val &= ~CM_DSFC_MASK; 799 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK; 800 } 801 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val); 802 //snd_printd("cmipci: functrl1 = %08x\n", val); 803 804 /* set format */ 805 val = snd_cmipci_read(cm, CM_REG_CHFORMAT); 806 if (rec->ch) { 807 val &= ~CM_CH1FMT_MASK; 808 val |= rec->fmt << CM_CH1FMT_SHIFT; 809 } else { 810 val &= ~CM_CH0FMT_MASK; 811 val |= rec->fmt << CM_CH0FMT_SHIFT; 812 } 813 snd_cmipci_write(cm, CM_REG_CHFORMAT, val); 814 //snd_printd("cmipci: chformat = %08x\n", val); 815 816 rec->running = 0; 817 spin_unlock_irq(&cm->reg_lock); 818 819 return 0; 820} 821 822/* 823 * PCM trigger/stop 824 */ 825static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec, 826 struct snd_pcm_substream *substream, int cmd) 827{ 828 unsigned int inthld, chen, reset, pause; 829 int result = 0; 830 831 inthld = CM_CH0_INT_EN << rec->ch; 832 chen = CM_CHEN0 << rec->ch; 833 reset = CM_RST_CH0 << rec->ch; 834 pause = CM_PAUSE0 << rec->ch; 835 836 spin_lock(&cm->reg_lock); 837 switch (cmd) { 838 case SNDRV_PCM_TRIGGER_START: 839 rec->running = 1; 840 /* set interrupt */ 841 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld); 842 cm->ctrl |= chen; 843 /* enable channel */ 844 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); 845 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl); 846 break; 847 case SNDRV_PCM_TRIGGER_STOP: 848 rec->running = 0; 849 /* disable interrupt */ 850 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld); 851 /* reset */ 852 cm->ctrl &= ~chen; 853 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset); 854 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset); 855 break; 856 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 857 case SNDRV_PCM_TRIGGER_SUSPEND: 858 cm->ctrl |= pause; 859 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); 860 break; 861 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 862 case SNDRV_PCM_TRIGGER_RESUME: 863 cm->ctrl &= ~pause; 864 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); 865 break; 866 default: 867 result = -EINVAL; 868 break; 869 } 870 spin_unlock(&cm->reg_lock); 871 return result; 872} 873 874/* 875 * return the current pointer 876 */ 877static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec, 878 struct snd_pcm_substream *substream) 879{ 880 size_t ptr; 881 unsigned int reg; 882 if (!rec->running) 883 return 0; 884 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2; 885 ptr = rec->dma_size - (snd_cmipci_read_w(cm, reg) + 1); 886 ptr >>= rec->shift; 887 if (substream->runtime->channels > 2) 888 ptr = (ptr * 2) / substream->runtime->channels; 889 return ptr; 890} 891 892/* 893 * playback 894 */ 895 896static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream, 897 int cmd) 898{ 899 struct cmipci *cm = snd_pcm_substream_chip(substream); 900 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], substream, cmd); 901} 902 903static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream) 904{ 905 struct cmipci *cm = snd_pcm_substream_chip(substream); 906 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream); 907} 908 909 910 911/* 912 * capture 913 */ 914 915static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream, 916 int cmd) 917{ 918 struct cmipci *cm = snd_pcm_substream_chip(substream); 919 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], substream, cmd); 920} 921 922static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream) 923{ 924 struct cmipci *cm = snd_pcm_substream_chip(substream); 925 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream); 926} 927 928 929/* 930 * hw preparation for spdif 931 */ 932 933static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol, 934 struct snd_ctl_elem_info *uinfo) 935{ 936 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 937 uinfo->count = 1; 938 return 0; 939} 940 941static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol, 942 struct snd_ctl_elem_value *ucontrol) 943{ 944 struct cmipci *chip = snd_kcontrol_chip(kcontrol); 945 int i; 946 947 spin_lock_irq(&chip->reg_lock); 948 for (i = 0; i < 4; i++) 949 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff; 950 spin_unlock_irq(&chip->reg_lock); 951 return 0; 952} 953 954static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol, 955 struct snd_ctl_elem_value *ucontrol) 956{ 957 struct cmipci *chip = snd_kcontrol_chip(kcontrol); 958 int i, change; 959 unsigned int val; 960 961 val = 0; 962 spin_lock_irq(&chip->reg_lock); 963 for (i = 0; i < 4; i++) 964 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8); 965 change = val != chip->dig_status; 966 chip->dig_status = val; 967 spin_unlock_irq(&chip->reg_lock); 968 return change; 969} 970 971static struct snd_kcontrol_new snd_cmipci_spdif_default __devinitdata = 972{ 973 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 974 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), 975 .info = snd_cmipci_spdif_default_info, 976 .get = snd_cmipci_spdif_default_get, 977 .put = snd_cmipci_spdif_default_put 978}; 979 980static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol, 981 struct snd_ctl_elem_info *uinfo) 982{ 983 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 984 uinfo->count = 1; 985 return 0; 986} 987 988static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol, 989 struct snd_ctl_elem_value *ucontrol) 990{ 991 ucontrol->value.iec958.status[0] = 0xff; 992 ucontrol->value.iec958.status[1] = 0xff; 993 ucontrol->value.iec958.status[2] = 0xff; 994 ucontrol->value.iec958.status[3] = 0xff; 995 return 0; 996} 997 998static struct snd_kcontrol_new snd_cmipci_spdif_mask __devinitdata = 999{ 1000 .access = SNDRV_CTL_ELEM_ACCESS_READ, 1001 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1002 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK), 1003 .info = snd_cmipci_spdif_mask_info, 1004 .get = snd_cmipci_spdif_mask_get, 1005}; 1006 1007static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol, 1008 struct snd_ctl_elem_info *uinfo) 1009{ 1010 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1011 uinfo->count = 1; 1012 return 0; 1013} 1014 1015static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol, 1016 struct snd_ctl_elem_value *ucontrol) 1017{ 1018 struct cmipci *chip = snd_kcontrol_chip(kcontrol); 1019 int i; 1020 1021 spin_lock_irq(&chip->reg_lock); 1022 for (i = 0; i < 4; i++) 1023 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff; 1024 spin_unlock_irq(&chip->reg_lock); 1025 return 0; 1026} 1027 1028static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol, 1029 struct snd_ctl_elem_value *ucontrol) 1030{ 1031 struct cmipci *chip = snd_kcontrol_chip(kcontrol); 1032 int i, change; 1033 unsigned int val; 1034 1035 val = 0; 1036 spin_lock_irq(&chip->reg_lock); 1037 for (i = 0; i < 4; i++) 1038 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8); 1039 change = val != chip->dig_pcm_status; 1040 chip->dig_pcm_status = val; 1041 spin_unlock_irq(&chip->reg_lock); 1042 return change; 1043} 1044 1045static struct snd_kcontrol_new snd_cmipci_spdif_stream __devinitdata = 1046{ 1047 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, 1048 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1049 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), 1050 .info = snd_cmipci_spdif_stream_info, 1051 .get = snd_cmipci_spdif_stream_get, 1052 .put = snd_cmipci_spdif_stream_put 1053}; 1054 1055/* 1056 */ 1057 1058/* save mixer setting and mute for AC3 playback */ 1059static int save_mixer_state(struct cmipci *cm) 1060{ 1061 if (! cm->mixer_insensitive) { 1062 struct snd_ctl_elem_value *val; 1063 unsigned int i; 1064 1065 val = kmalloc(sizeof(*val), GFP_ATOMIC); 1066 if (!val) 1067 return -ENOMEM; 1068 for (i = 0; i < CM_SAVED_MIXERS; i++) { 1069 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i]; 1070 if (ctl) { 1071 int event; 1072 memset(val, 0, sizeof(*val)); 1073 ctl->get(ctl, val); 1074 cm->mixer_res_status[i] = val->value.integer.value[0]; 1075 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on; 1076 event = SNDRV_CTL_EVENT_MASK_INFO; 1077 if (cm->mixer_res_status[i] != val->value.integer.value[0]) { 1078 ctl->put(ctl, val); /* toggle */ 1079 event |= SNDRV_CTL_EVENT_MASK_VALUE; 1080 } 1081 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; 1082 snd_ctl_notify(cm->card, event, &ctl->id); 1083 } 1084 } 1085 kfree(val); 1086 cm->mixer_insensitive = 1; 1087 } 1088 return 0; 1089} 1090 1091 1092/* restore the previously saved mixer status */ 1093static void restore_mixer_state(struct cmipci *cm) 1094{ 1095 if (cm->mixer_insensitive) { 1096 struct snd_ctl_elem_value *val; 1097 unsigned int i; 1098 1099 val = kmalloc(sizeof(*val), GFP_KERNEL); 1100 if (!val) 1101 return; 1102 cm->mixer_insensitive = 0; /* at first clear this; 1103 otherwise the changes will be ignored */ 1104 for (i = 0; i < CM_SAVED_MIXERS; i++) { 1105 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i]; 1106 if (ctl) { 1107 int event; 1108 1109 memset(val, 0, sizeof(*val)); 1110 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; 1111 ctl->get(ctl, val); 1112 event = SNDRV_CTL_EVENT_MASK_INFO; 1113 if (val->value.integer.value[0] != cm->mixer_res_status[i]) { 1114 val->value.integer.value[0] = cm->mixer_res_status[i]; 1115 ctl->put(ctl, val); 1116 event |= SNDRV_CTL_EVENT_MASK_VALUE; 1117 } 1118 snd_ctl_notify(cm->card, event, &ctl->id); 1119 } 1120 } 1121 kfree(val); 1122 } 1123} 1124 1125/* spinlock held! */ 1126static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate) 1127{ 1128 if (do_ac3) { 1129 /* AC3EN for 037 */ 1130 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1); 1131 /* AC3EN for 039 */ 1132 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2); 1133 1134 if (cm->can_ac3_hw) { 1135 /* SPD24SEL for 037, 0x02 */ 1136 /* SPD24SEL for 039, 0x20, but cannot be set */ 1137 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL); 1138 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); 1139 } else { /* can_ac3_sw */ 1140 /* SPD32SEL for 037 & 039, 0x20 */ 1141 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); 1142 /* set 176K sample rate to fix 033 HW bug */ 1143 if (cm->chip_version == 33) { 1144 if (rate >= 48000) { 1145 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K); 1146 } else { 1147 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K); 1148 } 1149 } 1150 } 1151 1152 } else { 1153 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1); 1154 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2); 1155 1156 if (cm->can_ac3_hw) { 1157 /* chip model >= 37 */ 1158 if (snd_pcm_format_width(subs->runtime->format) > 16) { 1159 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); 1160 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL); 1161 } else { 1162 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); 1163 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL); 1164 } 1165 } else { 1166 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); 1167 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL); 1168 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K); 1169 } 1170 } 1171} 1172 1173static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3) 1174{ 1175 int rate, err; 1176 1177 rate = subs->runtime->rate; 1178 1179 if (up && do_ac3) 1180 if ((err = save_mixer_state(cm)) < 0) 1181 return err; 1182 1183 spin_lock_irq(&cm->reg_lock); 1184 cm->spdif_playback_avail = up; 1185 if (up) { 1186 /* they are controlled via "IEC958 Output Switch" */ 1187 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */ 1188 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */ 1189 if (cm->spdif_playback_enabled) 1190 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); 1191 setup_ac3(cm, subs, do_ac3, rate); 1192 1193 if (rate == 48000) 1194 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97); 1195 else 1196 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97); 1197 1198 } else { 1199 /* they are controlled via "IEC958 Output Switch" */ 1200 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */ 1201 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */ 1202 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); 1203 setup_ac3(cm, subs, 0, 0); 1204 } 1205 spin_unlock_irq(&cm->reg_lock); 1206 return 0; 1207} 1208 1209 1210/* 1211 * preparation 1212 */ 1213 1214/* playback - enable spdif only on the certain condition */ 1215static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream) 1216{ 1217 struct cmipci *cm = snd_pcm_substream_chip(substream); 1218 int rate = substream->runtime->rate; 1219 int err, do_spdif, do_ac3 = 0; 1220 1221 do_spdif = ((rate == 44100 || rate == 48000) && 1222 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE && 1223 substream->runtime->channels == 2); 1224 if (do_spdif && cm->can_ac3_hw) 1225 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO; 1226 if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0) 1227 return err; 1228 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream); 1229} 1230 1231/* playback (via device #2) - enable spdif always */ 1232static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream) 1233{ 1234 struct cmipci *cm = snd_pcm_substream_chip(substream); 1235 int err, do_ac3; 1236 1237 if (cm->can_ac3_hw) 1238 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO; 1239 else 1240 do_ac3 = 1; /* doesn't matter */ 1241 if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0) 1242 return err; 1243 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream); 1244} 1245 1246static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream) 1247{ 1248 struct cmipci *cm = snd_pcm_substream_chip(substream); 1249 setup_spdif_playback(cm, substream, 0, 0); 1250 restore_mixer_state(cm); 1251 return snd_cmipci_hw_free(substream); 1252} 1253 1254/* capture */ 1255static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream) 1256{ 1257 struct cmipci *cm = snd_pcm_substream_chip(substream); 1258 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream); 1259} 1260 1261/* capture with spdif (via device #2) */ 1262static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream) 1263{ 1264 struct cmipci *cm = snd_pcm_substream_chip(substream); 1265 1266 spin_lock_irq(&cm->reg_lock); 1267 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF); 1268 spin_unlock_irq(&cm->reg_lock); 1269 1270 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream); 1271} 1272 1273static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs) 1274{ 1275 struct cmipci *cm = snd_pcm_substream_chip(subs); 1276 1277 spin_lock_irq(&cm->reg_lock); 1278 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF); 1279 spin_unlock_irq(&cm->reg_lock); 1280 1281 return snd_cmipci_hw_free(subs); 1282} 1283 1284 1285/* 1286 * interrupt handler 1287 */ 1288static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id) 1289{ 1290 struct cmipci *cm = dev_id; 1291 unsigned int status, mask = 0; 1292 1293 /* fastpath out, to ease interrupt sharing */ 1294 status = snd_cmipci_read(cm, CM_REG_INT_STATUS); 1295 if (!(status & CM_INTR)) 1296 return IRQ_NONE; 1297 1298 /* acknowledge interrupt */ 1299 spin_lock(&cm->reg_lock); 1300 if (status & CM_CHINT0) 1301 mask |= CM_CH0_INT_EN; 1302 if (status & CM_CHINT1) 1303 mask |= CM_CH1_INT_EN; 1304 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask); 1305 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask); 1306 spin_unlock(&cm->reg_lock); 1307 1308 if (cm->rmidi && (status & CM_UARTINT)) 1309 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data); 1310 1311 if (cm->pcm) { 1312 if ((status & CM_CHINT0) && cm->channel[0].running) 1313 snd_pcm_period_elapsed(cm->channel[0].substream); 1314 if ((status & CM_CHINT1) && cm->channel[1].running) 1315 snd_pcm_period_elapsed(cm->channel[1].substream); 1316 } 1317 return IRQ_HANDLED; 1318} 1319 1320/* 1321 * h/w infos 1322 */ 1323 1324/* playback on channel A */ 1325static struct snd_pcm_hardware snd_cmipci_playback = 1326{ 1327 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1328 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | 1329 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), 1330 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1331 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000, 1332 .rate_min = 5512, 1333 .rate_max = 48000, 1334 .channels_min = 1, 1335 .channels_max = 2, 1336 .buffer_bytes_max = (128*1024), 1337 .period_bytes_min = 64, 1338 .period_bytes_max = (128*1024), 1339 .periods_min = 2, 1340 .periods_max = 1024, 1341 .fifo_size = 0, 1342}; 1343 1344/* capture on channel B */ 1345static struct snd_pcm_hardware snd_cmipci_capture = 1346{ 1347 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1348 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | 1349 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), 1350 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1351 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000, 1352 .rate_min = 5512, 1353 .rate_max = 48000, 1354 .channels_min = 1, 1355 .channels_max = 2, 1356 .buffer_bytes_max = (128*1024), 1357 .period_bytes_min = 64, 1358 .period_bytes_max = (128*1024), 1359 .periods_min = 2, 1360 .periods_max = 1024, 1361 .fifo_size = 0, 1362}; 1363 1364/* playback on channel B - stereo 16bit only? */ 1365static struct snd_pcm_hardware snd_cmipci_playback2 = 1366{ 1367 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1368 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | 1369 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), 1370 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1371 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000, 1372 .rate_min = 5512, 1373 .rate_max = 48000, 1374 .channels_min = 2, 1375 .channels_max = 2, 1376 .buffer_bytes_max = (128*1024), 1377 .period_bytes_min = 64, 1378 .period_bytes_max = (128*1024), 1379 .periods_min = 2, 1380 .periods_max = 1024, 1381 .fifo_size = 0, 1382}; 1383 1384/* spdif playback on channel A */ 1385static struct snd_pcm_hardware snd_cmipci_playback_spdif = 1386{ 1387 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1388 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | 1389 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), 1390 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1391 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000, 1392 .rate_min = 44100, 1393 .rate_max = 48000, 1394 .channels_min = 2, 1395 .channels_max = 2, 1396 .buffer_bytes_max = (128*1024), 1397 .period_bytes_min = 64, 1398 .period_bytes_max = (128*1024), 1399 .periods_min = 2, 1400 .periods_max = 1024, 1401 .fifo_size = 0, 1402}; 1403 1404/* spdif playback on channel A (32bit, IEC958 subframes) */ 1405static struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe = 1406{ 1407 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1408 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | 1409 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), 1410 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1411 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000, 1412 .rate_min = 44100, 1413 .rate_max = 48000, 1414 .channels_min = 2, 1415 .channels_max = 2, 1416 .buffer_bytes_max = (128*1024), 1417 .period_bytes_min = 64, 1418 .period_bytes_max = (128*1024), 1419 .periods_min = 2, 1420 .periods_max = 1024, 1421 .fifo_size = 0, 1422}; 1423 1424/* spdif capture on channel B */ 1425static struct snd_pcm_hardware snd_cmipci_capture_spdif = 1426{ 1427 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1428 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | 1429 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), 1430 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1431 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000, 1432 .rate_min = 44100, 1433 .rate_max = 48000, 1434 .channels_min = 2, 1435 .channels_max = 2, 1436 .buffer_bytes_max = (128*1024), 1437 .period_bytes_min = 64, 1438 .period_bytes_max = (128*1024), 1439 .periods_min = 2, 1440 .periods_max = 1024, 1441 .fifo_size = 0, 1442}; 1443 1444/* 1445 * check device open/close 1446 */ 1447static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs) 1448{ 1449 int ch = mode & CM_OPEN_CH_MASK; 1450 1451 mutex_lock(&cm->open_mutex); 1452 if (cm->opened[ch]) { 1453 mutex_unlock(&cm->open_mutex); 1454 return -EBUSY; 1455 } 1456 cm->opened[ch] = mode; 1457 cm->channel[ch].substream = subs; 1458 if (! (mode & CM_OPEN_DAC)) { 1459 /* disable dual DAC mode */ 1460 cm->channel[ch].is_dac = 0; 1461 spin_lock_irq(&cm->reg_lock); 1462 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC); 1463 spin_unlock_irq(&cm->reg_lock); 1464 } 1465 mutex_unlock(&cm->open_mutex); 1466 return 0; 1467} 1468 1469static void close_device_check(struct cmipci *cm, int mode) 1470{ 1471 int ch = mode & CM_OPEN_CH_MASK; 1472 1473 mutex_lock(&cm->open_mutex); 1474 if (cm->opened[ch] == mode) { 1475 if (cm->channel[ch].substream) { 1476 snd_cmipci_ch_reset(cm, ch); 1477 cm->channel[ch].running = 0; 1478 cm->channel[ch].substream = NULL; 1479 } 1480 cm->opened[ch] = 0; 1481 if (! cm->channel[ch].is_dac) { 1482 /* enable dual DAC mode again */ 1483 cm->channel[ch].is_dac = 1; 1484 spin_lock_irq(&cm->reg_lock); 1485 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC); 1486 spin_unlock_irq(&cm->reg_lock); 1487 } 1488 } 1489 mutex_unlock(&cm->open_mutex); 1490} 1491 1492/* 1493 */ 1494 1495static int snd_cmipci_playback_open(struct snd_pcm_substream *substream) 1496{ 1497 struct cmipci *cm = snd_pcm_substream_chip(substream); 1498 struct snd_pcm_runtime *runtime = substream->runtime; 1499 int err; 1500 1501 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0) 1502 return err; 1503 runtime->hw = snd_cmipci_playback; 1504 runtime->hw.channels_max = cm->max_channels; 1505 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000); 1506 cm->dig_pcm_status = cm->dig_status; 1507 return 0; 1508} 1509 1510static int snd_cmipci_capture_open(struct snd_pcm_substream *substream) 1511{ 1512 struct cmipci *cm = snd_pcm_substream_chip(substream); 1513 struct snd_pcm_runtime *runtime = substream->runtime; 1514 int err; 1515 1516 if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0) 1517 return err; 1518 runtime->hw = snd_cmipci_capture; 1519 if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording 1520 runtime->hw.rate_min = 41000; 1521 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000; 1522 } 1523 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000); 1524 return 0; 1525} 1526 1527static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream) 1528{ 1529 struct cmipci *cm = snd_pcm_substream_chip(substream); 1530 struct snd_pcm_runtime *runtime = substream->runtime; 1531 int err; 1532 1533 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */ 1534 return err; 1535 runtime->hw = snd_cmipci_playback2; 1536 mutex_lock(&cm->open_mutex); 1537 if (! cm->opened[CM_CH_PLAY]) { 1538 if (cm->can_multi_ch) { 1539 runtime->hw.channels_max = cm->max_channels; 1540 if (cm->max_channels == 4) 1541 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4); 1542 else if (cm->max_channels == 6) 1543 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6); 1544 else if (cm->max_channels == 8) 1545 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8); 1546 } 1547 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000); 1548 } 1549 mutex_unlock(&cm->open_mutex); 1550 return 0; 1551} 1552 1553static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream) 1554{ 1555 struct cmipci *cm = snd_pcm_substream_chip(substream); 1556 struct snd_pcm_runtime *runtime = substream->runtime; 1557 int err; 1558 1559 if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */ 1560 return err; 1561 if (cm->can_ac3_hw) { 1562 runtime->hw = snd_cmipci_playback_spdif; 1563 if (cm->chip_version >= 37) 1564 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE; 1565 } else { 1566 runtime->hw = snd_cmipci_playback_iec958_subframe; 1567 } 1568 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000); 1569 cm->dig_pcm_status = cm->dig_status; 1570 return 0; 1571} 1572 1573static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream) 1574{ 1575 struct cmipci *cm = snd_pcm_substream_chip(substream); 1576 struct snd_pcm_runtime *runtime = substream->runtime; 1577 int err; 1578 1579 if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */ 1580 return err; 1581 runtime->hw = snd_cmipci_capture_spdif; 1582 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000); 1583 return 0; 1584} 1585 1586 1587/* 1588 */ 1589 1590static int snd_cmipci_playback_close(struct snd_pcm_substream *substream) 1591{ 1592 struct cmipci *cm = snd_pcm_substream_chip(substream); 1593 close_device_check(cm, CM_OPEN_PLAYBACK); 1594 return 0; 1595} 1596 1597static int snd_cmipci_capture_close(struct snd_pcm_substream *substream) 1598{ 1599 struct cmipci *cm = snd_pcm_substream_chip(substream); 1600 close_device_check(cm, CM_OPEN_CAPTURE); 1601 return 0; 1602} 1603 1604static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream) 1605{ 1606 struct cmipci *cm = snd_pcm_substream_chip(substream); 1607 close_device_check(cm, CM_OPEN_PLAYBACK2); 1608 close_device_check(cm, CM_OPEN_PLAYBACK_MULTI); 1609 return 0; 1610} 1611 1612static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream) 1613{ 1614 struct cmipci *cm = snd_pcm_substream_chip(substream); 1615 close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK); 1616 return 0; 1617} 1618 1619static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream) 1620{ 1621 struct cmipci *cm = snd_pcm_substream_chip(substream); 1622 close_device_check(cm, CM_OPEN_SPDIF_CAPTURE); 1623 return 0; 1624} 1625 1626 1627/* 1628 */ 1629 1630static struct snd_pcm_ops snd_cmipci_playback_ops = { 1631 .open = snd_cmipci_playback_open, 1632 .close = snd_cmipci_playback_close, 1633 .ioctl = snd_pcm_lib_ioctl, 1634 .hw_params = snd_cmipci_hw_params, 1635 .hw_free = snd_cmipci_playback_hw_free, 1636 .prepare = snd_cmipci_playback_prepare, 1637 .trigger = snd_cmipci_playback_trigger, 1638 .pointer = snd_cmipci_playback_pointer, 1639}; 1640 1641static struct snd_pcm_ops snd_cmipci_capture_ops = { 1642 .open = snd_cmipci_capture_open, 1643 .close = snd_cmipci_capture_close, 1644 .ioctl = snd_pcm_lib_ioctl, 1645 .hw_params = snd_cmipci_hw_params, 1646 .hw_free = snd_cmipci_hw_free, 1647 .prepare = snd_cmipci_capture_prepare, 1648 .trigger = snd_cmipci_capture_trigger, 1649 .pointer = snd_cmipci_capture_pointer, 1650}; 1651 1652static struct snd_pcm_ops snd_cmipci_playback2_ops = { 1653 .open = snd_cmipci_playback2_open, 1654 .close = snd_cmipci_playback2_close, 1655 .ioctl = snd_pcm_lib_ioctl, 1656 .hw_params = snd_cmipci_playback2_hw_params, 1657 .hw_free = snd_cmipci_hw_free, 1658 .prepare = snd_cmipci_capture_prepare, /* channel B */ 1659 .trigger = snd_cmipci_capture_trigger, /* channel B */ 1660 .pointer = snd_cmipci_capture_pointer, /* channel B */ 1661}; 1662 1663static struct snd_pcm_ops snd_cmipci_playback_spdif_ops = { 1664 .open = snd_cmipci_playback_spdif_open, 1665 .close = snd_cmipci_playback_spdif_close, 1666 .ioctl = snd_pcm_lib_ioctl, 1667 .hw_params = snd_cmipci_hw_params, 1668 .hw_free = snd_cmipci_playback_hw_free, 1669 .prepare = snd_cmipci_playback_spdif_prepare, /* set up rate */ 1670 .trigger = snd_cmipci_playback_trigger, 1671 .pointer = snd_cmipci_playback_pointer, 1672}; 1673 1674static struct snd_pcm_ops snd_cmipci_capture_spdif_ops = { 1675 .open = snd_cmipci_capture_spdif_open, 1676 .close = snd_cmipci_capture_spdif_close, 1677 .ioctl = snd_pcm_lib_ioctl, 1678 .hw_params = snd_cmipci_hw_params, 1679 .hw_free = snd_cmipci_capture_spdif_hw_free, 1680 .prepare = snd_cmipci_capture_spdif_prepare, 1681 .trigger = snd_cmipci_capture_trigger, 1682 .pointer = snd_cmipci_capture_pointer, 1683}; 1684 1685 1686/* 1687 */ 1688 1689static int __devinit snd_cmipci_pcm_new(struct cmipci *cm, int device) 1690{ 1691 struct snd_pcm *pcm; 1692 int err; 1693 1694 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm); 1695 if (err < 0) 1696 return err; 1697 1698 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops); 1699 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops); 1700 1701 pcm->private_data = cm; 1702 pcm->info_flags = 0; 1703 strcpy(pcm->name, "C-Media PCI DAC/ADC"); 1704 cm->pcm = pcm; 1705 1706 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1707 snd_dma_pci_data(cm->pci), 64*1024, 128*1024); 1708 1709 return 0; 1710} 1711 1712static int __devinit snd_cmipci_pcm2_new(struct cmipci *cm, int device) 1713{ 1714 struct snd_pcm *pcm; 1715 int err; 1716 1717 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm); 1718 if (err < 0) 1719 return err; 1720 1721 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops); 1722 1723 pcm->private_data = cm; 1724 pcm->info_flags = 0; 1725 strcpy(pcm->name, "C-Media PCI 2nd DAC"); 1726 cm->pcm2 = pcm; 1727 1728 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1729 snd_dma_pci_data(cm->pci), 64*1024, 128*1024); 1730 1731 return 0; 1732} 1733 1734static int __devinit snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device) 1735{ 1736 struct snd_pcm *pcm; 1737 int err; 1738 1739 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm); 1740 if (err < 0) 1741 return err; 1742 1743 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops); 1744 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops); 1745 1746 pcm->private_data = cm; 1747 pcm->info_flags = 0; 1748 strcpy(pcm->name, "C-Media PCI IEC958"); 1749 cm->pcm_spdif = pcm; 1750 1751 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1752 snd_dma_pci_data(cm->pci), 64*1024, 128*1024); 1753 1754 return 0; 1755} 1756 1757/* 1758 * mixer interface: 1759 * - CM8338/8738 has a compatible mixer interface with SB16, but 1760 * lack of some elements like tone control, i/o gain and AGC. 1761 * - Access to native registers: 1762 * - A 3D switch 1763 * - Output mute switches 1764 */ 1765 1766static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data) 1767{ 1768 outb(idx, s->iobase + CM_REG_SB16_ADDR); 1769 outb(data, s->iobase + CM_REG_SB16_DATA); 1770} 1771 1772static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx) 1773{ 1774 unsigned char v; 1775 1776 outb(idx, s->iobase + CM_REG_SB16_ADDR); 1777 v = inb(s->iobase + CM_REG_SB16_DATA); 1778 return v; 1779} 1780 1781/* 1782 * general mixer element 1783 */ 1784struct cmipci_sb_reg { 1785 unsigned int left_reg, right_reg; 1786 unsigned int left_shift, right_shift; 1787 unsigned int mask; 1788 unsigned int invert: 1; 1789 unsigned int stereo: 1; 1790}; 1791 1792#define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \ 1793 ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23)) 1794 1795#define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \ 1796{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 1797 .info = snd_cmipci_info_volume, \ 1798 .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \ 1799 .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \ 1800} 1801 1802#define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1) 1803#define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0) 1804#define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1) 1805#define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0) 1806 1807static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val) 1808{ 1809 r->left_reg = val & 0xff; 1810 r->right_reg = (val >> 8) & 0xff; 1811 r->left_shift = (val >> 16) & 0x07; 1812 r->right_shift = (val >> 19) & 0x07; 1813 r->invert = (val >> 22) & 1; 1814 r->stereo = (val >> 23) & 1; 1815 r->mask = (val >> 24) & 0xff; 1816} 1817 1818static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol, 1819 struct snd_ctl_elem_info *uinfo) 1820{ 1821 struct cmipci_sb_reg reg; 1822 1823 cmipci_sb_reg_decode(®, kcontrol->private_value); 1824 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; 1825 uinfo->count = reg.stereo + 1; 1826 uinfo->value.integer.min = 0; 1827 uinfo->value.integer.max = reg.mask; 1828 return 0; 1829} 1830 1831static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol, 1832 struct snd_ctl_elem_value *ucontrol) 1833{ 1834 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 1835 struct cmipci_sb_reg reg; 1836 int val; 1837 1838 cmipci_sb_reg_decode(®, kcontrol->private_value); 1839 spin_lock_irq(&cm->reg_lock); 1840 val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask; 1841 if (reg.invert) 1842 val = reg.mask - val; 1843 ucontrol->value.integer.value[0] = val; 1844 if (reg.stereo) { 1845 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask; 1846 if (reg.invert) 1847 val = reg.mask - val; 1848 ucontrol->value.integer.value[1] = val; 1849 } 1850 spin_unlock_irq(&cm->reg_lock); 1851 return 0; 1852} 1853 1854static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol, 1855 struct snd_ctl_elem_value *ucontrol) 1856{ 1857 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 1858 struct cmipci_sb_reg reg; 1859 int change; 1860 int left, right, oleft, oright; 1861 1862 cmipci_sb_reg_decode(®, kcontrol->private_value); 1863 left = ucontrol->value.integer.value[0] & reg.mask; 1864 if (reg.invert) 1865 left = reg.mask - left; 1866 left <<= reg.left_shift; 1867 if (reg.stereo) { 1868 right = ucontrol->value.integer.value[1] & reg.mask; 1869 if (reg.invert) 1870 right = reg.mask - right; 1871 right <<= reg.right_shift; 1872 } else 1873 right = 0; 1874 spin_lock_irq(&cm->reg_lock); 1875 oleft = snd_cmipci_mixer_read(cm, reg.left_reg); 1876 left |= oleft & ~(reg.mask << reg.left_shift); 1877 change = left != oleft; 1878 if (reg.stereo) { 1879 if (reg.left_reg != reg.right_reg) { 1880 snd_cmipci_mixer_write(cm, reg.left_reg, left); 1881 oright = snd_cmipci_mixer_read(cm, reg.right_reg); 1882 } else 1883 oright = left; 1884 right |= oright & ~(reg.mask << reg.right_shift); 1885 change |= right != oright; 1886 snd_cmipci_mixer_write(cm, reg.right_reg, right); 1887 } else 1888 snd_cmipci_mixer_write(cm, reg.left_reg, left); 1889 spin_unlock_irq(&cm->reg_lock); 1890 return change; 1891} 1892 1893/* 1894 * input route (left,right) -> (left,right) 1895 */ 1896#define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \ 1897{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 1898 .info = snd_cmipci_info_input_sw, \ 1899 .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \ 1900 .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \ 1901} 1902 1903static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol, 1904 struct snd_ctl_elem_info *uinfo) 1905{ 1906 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 1907 uinfo->count = 4; 1908 uinfo->value.integer.min = 0; 1909 uinfo->value.integer.max = 1; 1910 return 0; 1911} 1912 1913static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol, 1914 struct snd_ctl_elem_value *ucontrol) 1915{ 1916 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 1917 struct cmipci_sb_reg reg; 1918 int val1, val2; 1919 1920 cmipci_sb_reg_decode(®, kcontrol->private_value); 1921 spin_lock_irq(&cm->reg_lock); 1922 val1 = snd_cmipci_mixer_read(cm, reg.left_reg); 1923 val2 = snd_cmipci_mixer_read(cm, reg.right_reg); 1924 spin_unlock_irq(&cm->reg_lock); 1925 ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1; 1926 ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1; 1927 ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1; 1928 ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1; 1929 return 0; 1930} 1931 1932static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol, 1933 struct snd_ctl_elem_value *ucontrol) 1934{ 1935 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 1936 struct cmipci_sb_reg reg; 1937 int change; 1938 int val1, val2, oval1, oval2; 1939 1940 cmipci_sb_reg_decode(®, kcontrol->private_value); 1941 spin_lock_irq(&cm->reg_lock); 1942 oval1 = snd_cmipci_mixer_read(cm, reg.left_reg); 1943 oval2 = snd_cmipci_mixer_read(cm, reg.right_reg); 1944 val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift)); 1945 val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift)); 1946 val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift; 1947 val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift; 1948 val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift; 1949 val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift; 1950 change = val1 != oval1 || val2 != oval2; 1951 snd_cmipci_mixer_write(cm, reg.left_reg, val1); 1952 snd_cmipci_mixer_write(cm, reg.right_reg, val2); 1953 spin_unlock_irq(&cm->reg_lock); 1954 return change; 1955} 1956 1957/* 1958 * native mixer switches/volumes 1959 */ 1960 1961#define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \ 1962{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 1963 .info = snd_cmipci_info_native_mixer, \ 1964 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \ 1965 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \ 1966} 1967 1968#define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \ 1969{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 1970 .info = snd_cmipci_info_native_mixer, \ 1971 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \ 1972 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \ 1973} 1974 1975#define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \ 1976{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 1977 .info = snd_cmipci_info_native_mixer, \ 1978 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \ 1979 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \ 1980} 1981 1982#define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \ 1983{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 1984 .info = snd_cmipci_info_native_mixer, \ 1985 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \ 1986 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \ 1987} 1988 1989static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol, 1990 struct snd_ctl_elem_info *uinfo) 1991{ 1992 struct cmipci_sb_reg reg; 1993 1994 cmipci_sb_reg_decode(®, kcontrol->private_value); 1995 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; 1996 uinfo->count = reg.stereo + 1; 1997 uinfo->value.integer.min = 0; 1998 uinfo->value.integer.max = reg.mask; 1999 return 0; 2000 2001} 2002 2003static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol, 2004 struct snd_ctl_elem_value *ucontrol) 2005{ 2006 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2007 struct cmipci_sb_reg reg; 2008 unsigned char oreg, val; 2009 2010 cmipci_sb_reg_decode(®, kcontrol->private_value); 2011 spin_lock_irq(&cm->reg_lock); 2012 oreg = inb(cm->iobase + reg.left_reg); 2013 val = (oreg >> reg.left_shift) & reg.mask; 2014 if (reg.invert) 2015 val = reg.mask - val; 2016 ucontrol->value.integer.value[0] = val; 2017 if (reg.stereo) { 2018 val = (oreg >> reg.right_shift) & reg.mask; 2019 if (reg.invert) 2020 val = reg.mask - val; 2021 ucontrol->value.integer.value[1] = val; 2022 } 2023 spin_unlock_irq(&cm->reg_lock); 2024 return 0; 2025} 2026 2027static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol, 2028 struct snd_ctl_elem_value *ucontrol) 2029{ 2030 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2031 struct cmipci_sb_reg reg; 2032 unsigned char oreg, nreg, val; 2033 2034 cmipci_sb_reg_decode(®, kcontrol->private_value); 2035 spin_lock_irq(&cm->reg_lock); 2036 oreg = inb(cm->iobase + reg.left_reg); 2037 val = ucontrol->value.integer.value[0] & reg.mask; 2038 if (reg.invert) 2039 val = reg.mask - val; 2040 nreg = oreg & ~(reg.mask << reg.left_shift); 2041 nreg |= (val << reg.left_shift); 2042 if (reg.stereo) { 2043 val = ucontrol->value.integer.value[1] & reg.mask; 2044 if (reg.invert) 2045 val = reg.mask - val; 2046 nreg &= ~(reg.mask << reg.right_shift); 2047 nreg |= (val << reg.right_shift); 2048 } 2049 outb(nreg, cm->iobase + reg.left_reg); 2050 spin_unlock_irq(&cm->reg_lock); 2051 return (nreg != oreg); 2052} 2053 2054/* 2055 * special case - check mixer sensitivity 2056 */ 2057static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol, 2058 struct snd_ctl_elem_value *ucontrol) 2059{ 2060 //struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2061 return snd_cmipci_get_native_mixer(kcontrol, ucontrol); 2062} 2063 2064static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol, 2065 struct snd_ctl_elem_value *ucontrol) 2066{ 2067 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2068 if (cm->mixer_insensitive) { 2069 /* ignored */ 2070 return 0; 2071 } 2072 return snd_cmipci_put_native_mixer(kcontrol, ucontrol); 2073} 2074 2075 2076static struct snd_kcontrol_new snd_cmipci_mixers[] __devinitdata = { 2077 CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31), 2078 CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0), 2079 CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31), 2080 //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1), 2081 { /* switch with sensitivity */ 2082 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2083 .name = "PCM Playback Switch", 2084 .info = snd_cmipci_info_native_mixer, 2085 .get = snd_cmipci_get_native_mixer_sensitive, 2086 .put = snd_cmipci_put_native_mixer_sensitive, 2087 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0), 2088 }, 2089 CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0), 2090 CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31), 2091 CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1), 2092 CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5), 2093 CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31), 2094 CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1), 2095 CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1), 2096 CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31), 2097 CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3), 2098 CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3), 2099 CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31), 2100 CMIPCI_SB_SW_MONO("Mic Playback Switch", 0), 2101 CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0), 2102 CMIPCI_SB_VOL_MONO("PC Speaker Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3), 2103 CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15), 2104 CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0), 2105 CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0), 2106 CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1), 2107 CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7), 2108 CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7), 2109 CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0), 2110 CMIPCI_DOUBLE("PC Speaker Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0), 2111 CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0), 2112}; 2113 2114/* 2115 * other switches 2116 */ 2117 2118struct cmipci_switch_args { 2119 int reg; /* register index */ 2120 unsigned int mask; /* mask bits */ 2121 unsigned int mask_on; /* mask bits to turn on */ 2122 unsigned int is_byte: 1; /* byte access? */ 2123 unsigned int ac3_sensitive: 1; /* access forbidden during 2124 * non-audio operation? 2125 */ 2126}; 2127 2128static int snd_cmipci_uswitch_info(struct snd_kcontrol *kcontrol, 2129 struct snd_ctl_elem_info *uinfo) 2130{ 2131 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 2132 uinfo->count = 1; 2133 uinfo->value.integer.min = 0; 2134 uinfo->value.integer.max = 1; 2135 return 0; 2136} 2137 2138static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol, 2139 struct snd_ctl_elem_value *ucontrol, 2140 struct cmipci_switch_args *args) 2141{ 2142 unsigned int val; 2143 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2144 2145 spin_lock_irq(&cm->reg_lock); 2146 if (args->ac3_sensitive && cm->mixer_insensitive) { 2147 ucontrol->value.integer.value[0] = 0; 2148 spin_unlock_irq(&cm->reg_lock); 2149 return 0; 2150 } 2151 if (args->is_byte) 2152 val = inb(cm->iobase + args->reg); 2153 else 2154 val = snd_cmipci_read(cm, args->reg); 2155 ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0; 2156 spin_unlock_irq(&cm->reg_lock); 2157 return 0; 2158} 2159 2160static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol, 2161 struct snd_ctl_elem_value *ucontrol) 2162{ 2163 struct cmipci_switch_args *args; 2164 args = (struct cmipci_switch_args *)kcontrol->private_value; 2165 snd_assert(args != NULL, return -EINVAL); 2166 return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args); 2167} 2168 2169static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol, 2170 struct snd_ctl_elem_value *ucontrol, 2171 struct cmipci_switch_args *args) 2172{ 2173 unsigned int val; 2174 int change; 2175 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2176 2177 spin_lock_irq(&cm->reg_lock); 2178 if (args->ac3_sensitive && cm->mixer_insensitive) { 2179 /* ignored */ 2180 spin_unlock_irq(&cm->reg_lock); 2181 return 0; 2182 } 2183 if (args->is_byte) 2184 val = inb(cm->iobase + args->reg); 2185 else 2186 val = snd_cmipci_read(cm, args->reg); 2187 change = (val & args->mask) != (ucontrol->value.integer.value[0] ? 2188 args->mask_on : (args->mask & ~args->mask_on)); 2189 if (change) { 2190 val &= ~args->mask; 2191 if (ucontrol->value.integer.value[0]) 2192 val |= args->mask_on; 2193 else 2194 val |= (args->mask & ~args->mask_on); 2195 if (args->is_byte) 2196 outb((unsigned char)val, cm->iobase + args->reg); 2197 else 2198 snd_cmipci_write(cm, args->reg, val); 2199 } 2200 spin_unlock_irq(&cm->reg_lock); 2201 return change; 2202} 2203 2204static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol, 2205 struct snd_ctl_elem_value *ucontrol) 2206{ 2207 struct cmipci_switch_args *args; 2208 args = (struct cmipci_switch_args *)kcontrol->private_value; 2209 snd_assert(args != NULL, return -EINVAL); 2210 return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args); 2211} 2212 2213#define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \ 2214static struct cmipci_switch_args cmipci_switch_arg_##sname = { \ 2215 .reg = xreg, \ 2216 .mask = xmask, \ 2217 .mask_on = xmask_on, \ 2218 .is_byte = xis_byte, \ 2219 .ac3_sensitive = xac3, \ 2220} 2221 2222#define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \ 2223 DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3) 2224 2225DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0); 2226DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0); 2227DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0); 2228DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1); 2229DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0); 2230DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0); 2231DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1); 2232DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */ 2233// DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1); 2234DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1); 2235DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0); 2236/* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */ 2237DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0); 2238DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0); 2239#if CM_CH_PLAY == 1 2240DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */ 2241#else 2242DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0); 2243#endif 2244DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0); 2245// DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_SPK4, 1, 0); 2246// DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS, 0, 0); 2247// DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */ 2248DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0); 2249 2250#define DEFINE_SWITCH(sname, stype, sarg) \ 2251{ .name = sname, \ 2252 .iface = stype, \ 2253 .info = snd_cmipci_uswitch_info, \ 2254 .get = snd_cmipci_uswitch_get, \ 2255 .put = snd_cmipci_uswitch_put, \ 2256 .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\ 2257} 2258 2259#define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg) 2260#define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg) 2261 2262 2263/* 2264 * callbacks for spdif output switch 2265 * needs toggle two registers.. 2266 */ 2267static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol, 2268 struct snd_ctl_elem_value *ucontrol) 2269{ 2270 int changed; 2271 changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable); 2272 changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac); 2273 return changed; 2274} 2275 2276static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol, 2277 struct snd_ctl_elem_value *ucontrol) 2278{ 2279 struct cmipci *chip = snd_kcontrol_chip(kcontrol); 2280 int changed; 2281 changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable); 2282 changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac); 2283 if (changed) { 2284 if (ucontrol->value.integer.value[0]) { 2285 if (chip->spdif_playback_avail) 2286 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); 2287 } else { 2288 if (chip->spdif_playback_avail) 2289 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); 2290 } 2291 } 2292 chip->spdif_playback_enabled = ucontrol->value.integer.value[0]; 2293 return changed; 2294} 2295 2296 2297static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol, 2298 struct snd_ctl_elem_info *uinfo) 2299{ 2300 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2301 static char *texts[3] = { "Line-In", "Rear Output", "Bass Output" }; 2302 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2303 uinfo->count = 1; 2304 uinfo->value.enumerated.items = cm->chip_version >= 39 ? 3 : 2; 2305 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2306 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2307 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2308 return 0; 2309} 2310 2311static inline unsigned int get_line_in_mode(struct cmipci *cm) 2312{ 2313 unsigned int val; 2314 if (cm->chip_version >= 39) { 2315 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL); 2316 if (val & CM_LINE_AS_BASS) 2317 return 2; 2318 } 2319 val = snd_cmipci_read_b(cm, CM_REG_MIXER1); 2320 if (val & CM_SPK4) 2321 return 1; 2322 return 0; 2323} 2324 2325static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol, 2326 struct snd_ctl_elem_value *ucontrol) 2327{ 2328 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2329 2330 spin_lock_irq(&cm->reg_lock); 2331 ucontrol->value.enumerated.item[0] = get_line_in_mode(cm); 2332 spin_unlock_irq(&cm->reg_lock); 2333 return 0; 2334} 2335 2336static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol, 2337 struct snd_ctl_elem_value *ucontrol) 2338{ 2339 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2340 int change; 2341 2342 spin_lock_irq(&cm->reg_lock); 2343 if (ucontrol->value.enumerated.item[0] == 2) 2344 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS); 2345 else 2346 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS); 2347 if (ucontrol->value.enumerated.item[0] == 1) 2348 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_SPK4); 2349 else 2350 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_SPK4); 2351 spin_unlock_irq(&cm->reg_lock); 2352 return change; 2353} 2354 2355static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol, 2356 struct snd_ctl_elem_info *uinfo) 2357{ 2358 static char *texts[2] = { "Mic-In", "Center/LFE Output" }; 2359 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2360 uinfo->count = 1; 2361 uinfo->value.enumerated.items = 2; 2362 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2363 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2364 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2365 return 0; 2366} 2367 2368static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol, 2369 struct snd_ctl_elem_value *ucontrol) 2370{ 2371 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2372 /* same bit as spdi_phase */ 2373 spin_lock_irq(&cm->reg_lock); 2374 ucontrol->value.enumerated.item[0] = 2375 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0; 2376 spin_unlock_irq(&cm->reg_lock); 2377 return 0; 2378} 2379 2380static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol, 2381 struct snd_ctl_elem_value *ucontrol) 2382{ 2383 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2384 int change; 2385 2386 spin_lock_irq(&cm->reg_lock); 2387 if (ucontrol->value.enumerated.item[0]) 2388 change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE); 2389 else 2390 change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE); 2391 spin_unlock_irq(&cm->reg_lock); 2392 return change; 2393} 2394 2395/* both for CM8338/8738 */ 2396static struct snd_kcontrol_new snd_cmipci_mixer_switches[] __devinitdata = { 2397 DEFINE_MIXER_SWITCH("Four Channel Mode", fourch), 2398 { 2399 .name = "Line-In Mode", 2400 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2401 .info = snd_cmipci_line_in_mode_info, 2402 .get = snd_cmipci_line_in_mode_get, 2403 .put = snd_cmipci_line_in_mode_put, 2404 }, 2405}; 2406 2407/* for non-multichannel chips */ 2408static struct snd_kcontrol_new snd_cmipci_nomulti_switch __devinitdata = 2409DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac); 2410 2411/* only for CM8738 */ 2412static struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] __devinitdata = { 2413 // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable), 2414 { .name = "IEC958 Output Switch", 2415 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2416 .info = snd_cmipci_uswitch_info, 2417 .get = snd_cmipci_spdout_enable_get, 2418 .put = snd_cmipci_spdout_enable_put, 2419 }, 2420 DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid), 2421 DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright), 2422 DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v), 2423// DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k), 2424 DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop), 2425 DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor), 2426}; 2427 2428/* only for model 033/037 */ 2429static struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] __devinitdata = { 2430 DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out), 2431 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase), 2432 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1), 2433}; 2434 2435/* only for model 039 or later */ 2436static struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] __devinitdata = { 2437 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2), 2438 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2), 2439 { 2440 .name = "Mic-In Mode", 2441 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2442 .info = snd_cmipci_mic_in_mode_info, 2443 .get = snd_cmipci_mic_in_mode_get, 2444 .put = snd_cmipci_mic_in_mode_put, 2445 } 2446}; 2447 2448/* card control switches */ 2449static struct snd_kcontrol_new snd_cmipci_control_switches[] __devinitdata = { 2450 // DEFINE_CARD_SWITCH("Joystick", joystick), /* now module option */ 2451 DEFINE_CARD_SWITCH("Modem", modem), 2452}; 2453 2454 2455static int __devinit snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device) 2456{ 2457 struct snd_card *card; 2458 struct snd_kcontrol_new *sw; 2459 struct snd_kcontrol *kctl; 2460 unsigned int idx; 2461 int err; 2462 2463 snd_assert(cm != NULL && cm->card != NULL, return -EINVAL); 2464 2465 card = cm->card; 2466 2467 strcpy(card->mixername, "CMedia PCI"); 2468 2469 spin_lock_irq(&cm->reg_lock); 2470 snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */ 2471 spin_unlock_irq(&cm->reg_lock); 2472 2473 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) { 2474 if (cm->chip_version == 68) { // 8768 has no PCM volume 2475 if (!strcmp(snd_cmipci_mixers[idx].name, 2476 "PCM Playback Volume")) 2477 continue; 2478 } 2479 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0) 2480 return err; 2481 } 2482 2483 /* mixer switches */ 2484 sw = snd_cmipci_mixer_switches; 2485 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) { 2486 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); 2487 if (err < 0) 2488 return err; 2489 } 2490 if (! cm->can_multi_ch) { 2491 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm)); 2492 if (err < 0) 2493 return err; 2494 } 2495 if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 || 2496 cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) { 2497 sw = snd_cmipci_8738_mixer_switches; 2498 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) { 2499 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); 2500 if (err < 0) 2501 return err; 2502 } 2503 if (cm->can_ac3_hw) { 2504 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0) 2505 return err; 2506 kctl->id.device = pcm_spdif_device; 2507 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0) 2508 return err; 2509 kctl->id.device = pcm_spdif_device; 2510 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0) 2511 return err; 2512 kctl->id.device = pcm_spdif_device; 2513 } 2514 if (cm->chip_version <= 37) { 2515 sw = snd_cmipci_old_mixer_switches; 2516 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) { 2517 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); 2518 if (err < 0) 2519 return err; 2520 } 2521 } 2522 } 2523 if (cm->chip_version >= 39) { 2524 sw = snd_cmipci_extra_mixer_switches; 2525 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) { 2526 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); 2527 if (err < 0) 2528 return err; 2529 } 2530 } 2531 2532 /* card switches */ 2533 sw = snd_cmipci_control_switches; 2534 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_control_switches); idx++, sw++) { 2535 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); 2536 if (err < 0) 2537 return err; 2538 } 2539 2540 for (idx = 0; idx < CM_SAVED_MIXERS; idx++) { 2541 struct snd_ctl_elem_id id; 2542 struct snd_kcontrol *ctl; 2543 memset(&id, 0, sizeof(id)); 2544 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 2545 strcpy(id.name, cm_saved_mixer[idx].name); 2546 if ((ctl = snd_ctl_find_id(cm->card, &id)) != NULL) 2547 cm->mixer_res_ctl[idx] = ctl; 2548 } 2549 2550 return 0; 2551} 2552 2553 2554/* 2555 * proc interface 2556 */ 2557 2558#ifdef CONFIG_PROC_FS 2559static void snd_cmipci_proc_read(struct snd_info_entry *entry, 2560 struct snd_info_buffer *buffer) 2561{ 2562 struct cmipci *cm = entry->private_data; 2563 int i; 2564 2565 snd_iprintf(buffer, "%s\n\n", cm->card->longname); 2566 for (i = 0; i < 0x40; i++) { 2567 int v = inb(cm->iobase + i); 2568 if (i % 4 == 0) 2569 snd_iprintf(buffer, "%02x: ", i); 2570 snd_iprintf(buffer, "%02x", v); 2571 if (i % 4 == 3) 2572 snd_iprintf(buffer, "\n"); 2573 else 2574 snd_iprintf(buffer, " "); 2575 } 2576} 2577 2578static void __devinit snd_cmipci_proc_init(struct cmipci *cm) 2579{ 2580 struct snd_info_entry *entry; 2581 2582 if (! snd_card_proc_new(cm->card, "cmipci", &entry)) 2583 snd_info_set_text_ops(entry, cm, snd_cmipci_proc_read); 2584} 2585#else /* !CONFIG_PROC_FS */ 2586static inline void snd_cmipci_proc_init(struct cmipci *cm) {} 2587#endif 2588 2589 2590static struct pci_device_id snd_cmipci_ids[] = { 2591 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 2592 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 2593 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 2594 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 2595 {PCI_VENDOR_ID_AL, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 2596 {0,}, 2597}; 2598 2599 2600/* 2601 * check chip version and capabilities 2602 * driver name is modified according to the chip model 2603 */ 2604static void __devinit query_chip(struct cmipci *cm) 2605{ 2606 unsigned int detect; 2607 2608 /* check reg 0Ch, bit 24-31 */ 2609 detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2; 2610 if (! detect) { 2611 /* check reg 08h, bit 24-28 */ 2612 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1; 2613 if (! detect) { 2614 cm->chip_version = 33; 2615 cm->max_channels = 2; 2616 if (cm->do_soft_ac3) 2617 cm->can_ac3_sw = 1; 2618 else 2619 cm->can_ac3_hw = 1; 2620 cm->has_dual_dac = 1; 2621 } else { 2622 cm->chip_version = 37; 2623 cm->max_channels = 2; 2624 cm->can_ac3_hw = 1; 2625 cm->has_dual_dac = 1; 2626 } 2627 } else { 2628 /* check reg 0Ch, bit 26 */ 2629 if (detect & CM_CHIP_8768) { 2630 cm->chip_version = 68; 2631 cm->max_channels = 8; 2632 cm->can_ac3_hw = 1; 2633 cm->has_dual_dac = 1; 2634 cm->can_multi_ch = 1; 2635 } else if (detect & CM_CHIP_055) { 2636 cm->chip_version = 55; 2637 cm->max_channels = 6; 2638 cm->can_ac3_hw = 1; 2639 cm->has_dual_dac = 1; 2640 cm->can_multi_ch = 1; 2641 } else if (detect & CM_CHIP_039) { 2642 cm->chip_version = 39; 2643 if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */ 2644 cm->max_channels = 6; 2645 else 2646 cm->max_channels = 4; 2647 cm->can_ac3_hw = 1; 2648 cm->has_dual_dac = 1; 2649 cm->can_multi_ch = 1; 2650 } else { 2651 printk(KERN_ERR "chip %x version not supported\n", detect); 2652 } 2653 } 2654} 2655 2656#ifdef SUPPORT_JOYSTICK 2657static int __devinit snd_cmipci_create_gameport(struct cmipci *cm, int dev) 2658{ 2659 static int ports[] = { 0x201, 0x200, 0 }; 2660 struct gameport *gp; 2661 struct resource *r = NULL; 2662 int i, io_port = 0; 2663 2664 if (joystick_port[dev] == 0) 2665 return -ENODEV; 2666 2667 if (joystick_port[dev] == 1) { /* auto-detect */ 2668 for (i = 0; ports[i]; i++) { 2669 io_port = ports[i]; 2670 r = request_region(io_port, 1, "CMIPCI gameport"); 2671 if (r) 2672 break; 2673 } 2674 } else { 2675 io_port = joystick_port[dev]; 2676 r = request_region(io_port, 1, "CMIPCI gameport"); 2677 } 2678 2679 if (!r) { 2680 printk(KERN_WARNING "cmipci: cannot reserve joystick ports\n"); 2681 return -EBUSY; 2682 } 2683 2684 cm->gameport = gp = gameport_allocate_port(); 2685 if (!gp) { 2686 printk(KERN_ERR "cmipci: cannot allocate memory for gameport\n"); 2687 release_and_free_resource(r); 2688 return -ENOMEM; 2689 } 2690 gameport_set_name(gp, "C-Media Gameport"); 2691 gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci)); 2692 gameport_set_dev_parent(gp, &cm->pci->dev); 2693 gp->io = io_port; 2694 gameport_set_port_data(gp, r); 2695 2696 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN); 2697 2698 gameport_register_port(cm->gameport); 2699 2700 return 0; 2701} 2702 2703static void snd_cmipci_free_gameport(struct cmipci *cm) 2704{ 2705 if (cm->gameport) { 2706 struct resource *r = gameport_get_port_data(cm->gameport); 2707 2708 gameport_unregister_port(cm->gameport); 2709 cm->gameport = NULL; 2710 2711 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN); 2712 release_and_free_resource(r); 2713 } 2714} 2715#else 2716static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; } 2717static inline void snd_cmipci_free_gameport(struct cmipci *cm) { } 2718#endif 2719 2720static int snd_cmipci_free(struct cmipci *cm) 2721{ 2722 if (cm->irq >= 0) { 2723 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN); 2724 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); 2725 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */ 2726 snd_cmipci_ch_reset(cm, CM_CH_PLAY); 2727 snd_cmipci_ch_reset(cm, CM_CH_CAPT); 2728 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */ 2729 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0); 2730 2731 /* reset mixer */ 2732 snd_cmipci_mixer_write(cm, 0, 0); 2733 2734 synchronize_irq(cm->irq); 2735 2736 free_irq(cm->irq, cm); 2737 } 2738 2739 snd_cmipci_free_gameport(cm); 2740 pci_release_regions(cm->pci); 2741 pci_disable_device(cm->pci); 2742 kfree(cm); 2743 return 0; 2744} 2745 2746static int snd_cmipci_dev_free(struct snd_device *device) 2747{ 2748 struct cmipci *cm = device->device_data; 2749 return snd_cmipci_free(cm); 2750} 2751 2752static int __devinit snd_cmipci_create_fm(struct cmipci *cm, long fm_port) 2753{ 2754 long iosynth; 2755 unsigned int val; 2756 struct snd_opl3 *opl3; 2757 int err; 2758 2759 if (!fm_port) 2760 goto disable_fm; 2761 2762 /* first try FM regs in PCI port range */ 2763 iosynth = cm->iobase + CM_REG_FM_PCI; 2764 err = snd_opl3_create(cm->card, iosynth, iosynth + 2, 2765 OPL3_HW_OPL3, 1, &opl3); 2766 if (err < 0) { 2767 /* then try legacy ports */ 2768 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK; 2769 iosynth = fm_port; 2770 switch (iosynth) { 2771 case 0x3E8: val |= CM_FMSEL_3E8; break; 2772 case 0x3E0: val |= CM_FMSEL_3E0; break; 2773 case 0x3C8: val |= CM_FMSEL_3C8; break; 2774 case 0x388: val |= CM_FMSEL_388; break; 2775 default: 2776 goto disable_fm; 2777 } 2778 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val); 2779 /* enable FM */ 2780 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN); 2781 2782 if (snd_opl3_create(cm->card, iosynth, iosynth + 2, 2783 OPL3_HW_OPL3, 0, &opl3) < 0) { 2784 printk(KERN_ERR "cmipci: no OPL device at %#lx, " 2785 "skipping...\n", iosynth); 2786 goto disable_fm; 2787 } 2788 } 2789 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) { 2790 printk(KERN_ERR "cmipci: cannot create OPL3 hwdep\n"); 2791 return err; 2792 } 2793 return 0; 2794 2795 disable_fm: 2796 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_FMSEL_MASK); 2797 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN); 2798 return 0; 2799} 2800 2801static int __devinit snd_cmipci_create(struct snd_card *card, struct pci_dev *pci, 2802 int dev, struct cmipci **rcmipci) 2803{ 2804 struct cmipci *cm; 2805 int err; 2806 static struct snd_device_ops ops = { 2807 .dev_free = snd_cmipci_dev_free, 2808 }; 2809 unsigned int val = 0; 2810 long iomidi; 2811 int integrated_midi; 2812 int pcm_index, pcm_spdif_index; 2813 static struct pci_device_id intel_82437vx[] = { 2814 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) }, 2815 { }, 2816 }; 2817 2818 *rcmipci = NULL; 2819 2820 if ((err = pci_enable_device(pci)) < 0) 2821 return err; 2822 2823 cm = kzalloc(sizeof(*cm), GFP_KERNEL); 2824 if (cm == NULL) { 2825 pci_disable_device(pci); 2826 return -ENOMEM; 2827 } 2828 2829 spin_lock_init(&cm->reg_lock); 2830 mutex_init(&cm->open_mutex); 2831 cm->device = pci->device; 2832 cm->card = card; 2833 cm->pci = pci; 2834 cm->irq = -1; 2835 cm->channel[0].ch = 0; 2836 cm->channel[1].ch = 1; 2837 cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */ 2838 2839 if ((err = pci_request_regions(pci, card->driver)) < 0) { 2840 kfree(cm); 2841 pci_disable_device(pci); 2842 return err; 2843 } 2844 cm->iobase = pci_resource_start(pci, 0); 2845 2846 if (request_irq(pci->irq, snd_cmipci_interrupt, 2847 IRQF_SHARED, card->driver, cm)) { 2848 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); 2849 snd_cmipci_free(cm); 2850 return -EBUSY; 2851 } 2852 cm->irq = pci->irq; 2853 2854 pci_set_master(cm->pci); 2855 2856 /* 2857 * check chip version, max channels and capabilities 2858 */ 2859 2860 cm->chip_version = 0; 2861 cm->max_channels = 2; 2862 cm->do_soft_ac3 = soft_ac3[dev]; 2863 2864 if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A && 2865 pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B) 2866 query_chip(cm); 2867 /* added -MCx suffix for chip supporting multi-channels */ 2868 if (cm->can_multi_ch) 2869 sprintf(cm->card->driver + strlen(cm->card->driver), 2870 "-MC%d", cm->max_channels); 2871 else if (cm->can_ac3_sw) 2872 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC"); 2873 2874 cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF; 2875 cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF; 2876 2877#if CM_CH_PLAY == 1 2878 cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */ 2879#else 2880 cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */ 2881#endif 2882 2883 /* initialize codec registers */ 2884 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */ 2885 snd_cmipci_ch_reset(cm, CM_CH_PLAY); 2886 snd_cmipci_ch_reset(cm, CM_CH_CAPT); 2887 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */ 2888 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0); 2889 2890 snd_cmipci_write(cm, CM_REG_CHFORMAT, 0); 2891 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D); 2892#if CM_CH_PLAY == 1 2893 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); 2894#else 2895 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); 2896#endif 2897 /* Set Bus Master Request */ 2898 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ); 2899 2900 /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */ 2901 switch (pci->device) { 2902 case PCI_DEVICE_ID_CMEDIA_CM8738: 2903 case PCI_DEVICE_ID_CMEDIA_CM8738B: 2904 if (!pci_dev_present(intel_82437vx)) 2905 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX); 2906 break; 2907 default: 2908 break; 2909 } 2910 2911 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) { 2912 snd_cmipci_free(cm); 2913 return err; 2914 } 2915 2916 integrated_midi = snd_cmipci_read_b(cm, CM_REG_MPU_PCI) != 0xff; 2917 if (integrated_midi && mpu_port[dev] == 1) 2918 iomidi = cm->iobase + CM_REG_MPU_PCI; 2919 else { 2920 iomidi = mpu_port[dev]; 2921 switch (iomidi) { 2922 case 0x320: val = CM_VMPU_320; break; 2923 case 0x310: val = CM_VMPU_310; break; 2924 case 0x300: val = CM_VMPU_300; break; 2925 case 0x330: val = CM_VMPU_330; break; 2926 default: 2927 iomidi = 0; break; 2928 } 2929 if (iomidi > 0) { 2930 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val); 2931 /* enable UART */ 2932 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN); 2933 } 2934 } 2935 2936 if ((err = snd_cmipci_create_fm(cm, fm_port[dev])) < 0) 2937 return err; 2938 2939 /* reset mixer */ 2940 snd_cmipci_mixer_write(cm, 0, 0); 2941 2942 snd_cmipci_proc_init(cm); 2943 2944 /* create pcm devices */ 2945 pcm_index = pcm_spdif_index = 0; 2946 if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0) 2947 return err; 2948 pcm_index++; 2949 if (cm->has_dual_dac) { 2950 if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0) 2951 return err; 2952 pcm_index++; 2953 } 2954 if (cm->can_ac3_hw || cm->can_ac3_sw) { 2955 pcm_spdif_index = pcm_index; 2956 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0) 2957 return err; 2958 } 2959 2960 /* create mixer interface & switches */ 2961 if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0) 2962 return err; 2963 2964 if (iomidi > 0) { 2965 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI, 2966 iomidi, 2967 (integrated_midi ? 2968 MPU401_INFO_INTEGRATED : 0), 2969 cm->irq, 0, &cm->rmidi)) < 0) { 2970 printk(KERN_ERR "cmipci: no UART401 device at 0x%lx\n", iomidi); 2971 } 2972 } 2973 2974#ifdef USE_VAR48KRATE 2975 for (val = 0; val < ARRAY_SIZE(rates); val++) 2976 snd_cmipci_set_pll(cm, rates[val], val); 2977 2978 /* 2979 * (Re-)Enable external switch spdo_48k 2980 */ 2981 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97); 2982#endif /* USE_VAR48KRATE */ 2983 2984 if (snd_cmipci_create_gameport(cm, dev) < 0) 2985 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN); 2986 2987 snd_card_set_dev(card, &pci->dev); 2988 2989 *rcmipci = cm; 2990 return 0; 2991} 2992 2993/* 2994 */ 2995 2996MODULE_DEVICE_TABLE(pci, snd_cmipci_ids); 2997 2998static int __devinit snd_cmipci_probe(struct pci_dev *pci, 2999 const struct pci_device_id *pci_id) 3000{ 3001 static int dev; 3002 struct snd_card *card; 3003 struct cmipci *cm; 3004 int err; 3005 3006 if (dev >= SNDRV_CARDS) 3007 return -ENODEV; 3008 if (! enable[dev]) { 3009 dev++; 3010 return -ENOENT; 3011 } 3012 3013 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0); 3014 if (card == NULL) 3015 return -ENOMEM; 3016 3017 switch (pci->device) { 3018 case PCI_DEVICE_ID_CMEDIA_CM8738: 3019 case PCI_DEVICE_ID_CMEDIA_CM8738B: 3020 strcpy(card->driver, "CMI8738"); 3021 break; 3022 case PCI_DEVICE_ID_CMEDIA_CM8338A: 3023 case PCI_DEVICE_ID_CMEDIA_CM8338B: 3024 strcpy(card->driver, "CMI8338"); 3025 break; 3026 default: 3027 strcpy(card->driver, "CMIPCI"); 3028 break; 3029 } 3030 3031 if ((err = snd_cmipci_create(card, pci, dev, &cm)) < 0) { 3032 snd_card_free(card); 3033 return err; 3034 } 3035 card->private_data = cm; 3036 3037 sprintf(card->shortname, "C-Media PCI %s", card->driver); 3038 sprintf(card->longname, "%s (model %d) at 0x%lx, irq %i", 3039 card->shortname, 3040 cm->chip_version, 3041 cm->iobase, 3042 cm->irq); 3043 3044 //snd_printd("%s is detected\n", card->longname); 3045 3046 if ((err = snd_card_register(card)) < 0) { 3047 snd_card_free(card); 3048 return err; 3049 } 3050 pci_set_drvdata(pci, card); 3051 dev++; 3052 return 0; 3053 3054} 3055 3056static void __devexit snd_cmipci_remove(struct pci_dev *pci) 3057{ 3058 snd_card_free(pci_get_drvdata(pci)); 3059 pci_set_drvdata(pci, NULL); 3060} 3061 3062 3063#ifdef CONFIG_PM 3064/* 3065 * power management 3066 */ 3067static unsigned char saved_regs[] = { 3068 CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL, 3069 CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_MIXER3, CM_REG_PLL, 3070 CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2, 3071 CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC, 3072 CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0, 3073}; 3074 3075static unsigned char saved_mixers[] = { 3076 SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1, 3077 SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1, 3078 SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1, 3079 SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1, 3080 SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1, 3081 SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV, 3082 CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW, 3083 SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 3084}; 3085 3086static int snd_cmipci_suspend(struct pci_dev *pci, pm_message_t state) 3087{ 3088 struct snd_card *card = pci_get_drvdata(pci); 3089 struct cmipci *cm = card->private_data; 3090 int i; 3091 3092 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 3093 3094 snd_pcm_suspend_all(cm->pcm); 3095 snd_pcm_suspend_all(cm->pcm2); 3096 snd_pcm_suspend_all(cm->pcm_spdif); 3097 3098 /* save registers */ 3099 for (i = 0; i < ARRAY_SIZE(saved_regs); i++) 3100 cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]); 3101 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++) 3102 cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]); 3103 3104 /* disable ints */ 3105 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); 3106 3107 pci_disable_device(pci); 3108 pci_save_state(pci); 3109 pci_set_power_state(pci, pci_choose_state(pci, state)); 3110 return 0; 3111} 3112 3113static int snd_cmipci_resume(struct pci_dev *pci) 3114{ 3115 struct snd_card *card = pci_get_drvdata(pci); 3116 struct cmipci *cm = card->private_data; 3117 int i; 3118 3119 pci_set_power_state(pci, PCI_D0); 3120 pci_restore_state(pci); 3121 if (pci_enable_device(pci) < 0) { 3122 printk(KERN_ERR "cmipci: pci_enable_device failed, " 3123 "disabling device\n"); 3124 snd_card_disconnect(card); 3125 return -EIO; 3126 } 3127 pci_set_master(pci); 3128 3129 /* reset / initialize to a sane state */ 3130 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); 3131 snd_cmipci_ch_reset(cm, CM_CH_PLAY); 3132 snd_cmipci_ch_reset(cm, CM_CH_CAPT); 3133 snd_cmipci_mixer_write(cm, 0, 0); 3134 3135 /* restore registers */ 3136 for (i = 0; i < ARRAY_SIZE(saved_regs); i++) 3137 snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]); 3138 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++) 3139 snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]); 3140 3141 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 3142 return 0; 3143} 3144#endif /* CONFIG_PM */ 3145 3146static struct pci_driver driver = { 3147 .name = "C-Media PCI", 3148 .id_table = snd_cmipci_ids, 3149 .probe = snd_cmipci_probe, 3150 .remove = __devexit_p(snd_cmipci_remove), 3151#ifdef CONFIG_PM 3152 .suspend = snd_cmipci_suspend, 3153 .resume = snd_cmipci_resume, 3154#endif 3155}; 3156 3157static int __init alsa_card_cmipci_init(void) 3158{ 3159 return pci_register_driver(&driver); 3160} 3161 3162static void __exit alsa_card_cmipci_exit(void) 3163{ 3164 pci_unregister_driver(&driver); 3165} 3166 3167module_init(alsa_card_cmipci_init) 3168module_exit(alsa_card_cmipci_exit) 3169