1/* $Id: dma.h,v 1.1.1.1 2007/08/03 18:53:36 Exp $ 2 * include/asm-sparc64/dma.h 3 * 4 * Copyright 1996 (C) David S. Miller (davem@caip.rutgers.edu) 5 */ 6 7#ifndef _ASM_SPARC64_DMA_H 8#define _ASM_SPARC64_DMA_H 9 10#include <linux/kernel.h> 11#include <linux/types.h> 12#include <linux/spinlock.h> 13 14#include <asm/sbus.h> 15#include <asm/delay.h> 16#include <asm/oplib.h> 17 18/* These are irrelevant for Sparc DMA, but we leave it in so that 19 * things can compile. 20 */ 21#define MAX_DMA_CHANNELS 8 22#define DMA_MODE_READ 1 23#define DMA_MODE_WRITE 2 24#define MAX_DMA_ADDRESS (~0UL) 25 26/* Useful constants */ 27#define SIZE_16MB (16*1024*1024) 28#define SIZE_64K (64*1024) 29 30/* SBUS DMA controller reg offsets */ 31#define DMA_CSR 0x00UL /* rw DMA control/status register 0x00 */ 32#define DMA_ADDR 0x04UL /* rw DMA transfer address register 0x04 */ 33#define DMA_COUNT 0x08UL /* rw DMA transfer count register 0x08 */ 34#define DMA_TEST 0x0cUL /* rw DMA test/debug register 0x0c */ 35 36/* DVMA chip revisions */ 37enum dvma_rev { 38 dvmarev0, 39 dvmaesc1, 40 dvmarev1, 41 dvmarev2, 42 dvmarev3, 43 dvmarevplus, 44 dvmahme 45}; 46 47#define DMA_HASCOUNT(rev) ((rev)==dvmaesc1) 48 49/* Linux DMA information structure, filled during probe. */ 50struct sbus_dma { 51 struct sbus_dma *next; 52 struct sbus_dev *sdev; 53 void __iomem *regs; 54 55 /* Status, misc info */ 56 int node; /* Prom node for this DMA device */ 57 int running; /* Are we doing DMA now? */ 58 int allocated; /* Are we "owned" by anyone yet? */ 59 60 /* Transfer information. */ 61 u32 addr; /* Start address of current transfer */ 62 int nbytes; /* Size of current transfer */ 63 int realbytes; /* For splitting up large transfers, etc. */ 64 65 /* DMA revision */ 66 enum dvma_rev revision; 67}; 68 69extern struct sbus_dma *dma_chain; 70 71/* Broken hardware... */ 72#define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev1) 73#define DMA_ISESC1(dma) ((dma)->revision == dvmaesc1) 74 75/* Main routines in dma.c */ 76extern void dvma_init(struct sbus_bus *); 77 78/* Fields in the cond_reg register */ 79/* First, the version identification bits */ 80#define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */ 81#define DMA_VERS0 0x00000000 /* Sunray DMA version */ 82#define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */ 83#define DMA_VERS1 0x80000000 /* DMA rev 1 */ 84#define DMA_VERS2 0xa0000000 /* DMA rev 2 */ 85#define DMA_VERHME 0xb0000000 /* DMA hme gate array */ 86#define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */ 87 88#define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */ 89#define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */ 90#define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */ 91#define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */ 92#define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */ 93#define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */ 94#define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */ 95#define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */ 96#define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */ 97#define DMA_ST_WRITE 0x00000100 /* write from device to memory */ 98#define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */ 99#define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */ 100#define DMA_ESC_BURST 0x00000800 /* 1=16byte 0=32byte */ 101#define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */ 102#define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */ 103#define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */ 104#define DMA_TERM_CNTR 0x00004000 /* Terminal counter */ 105#define DMA_SCSI_SBUS64 0x00008000 /* HME: Enable 64-bit SBUS mode. */ 106#define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */ 107#define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */ 108#define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */ 109#define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */ 110#define DMA_E_BURSTS 0x000c0000 /* ENET: SBUS r/w burst mask */ 111#define DMA_E_BURST32 0x00040000 /* ENET: SBUS 32 byte r/w burst */ 112#define DMA_E_BURST16 0x00000000 /* ENET: SBUS 16 byte r/w burst */ 113#define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */ 114#define DMA_BRST64 0x000c0000 /* SCSI: 64byte bursts (HME on UltraSparc only) */ 115#define DMA_BRST32 0x00040000 /* SCSI: 32byte bursts */ 116#define DMA_BRST16 0x00000000 /* SCSI: 16byte bursts */ 117#define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */ 118#define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */ 119#define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */ 120#define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */ 121#define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */ 122#define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */ 123#define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */ 124#define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */ 125#define DMA_PARITY_OFF 0x02000000 /* HME: disable parity checking */ 126#define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */ 127#define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */ 128#define DMA_RESET_FAS366 0x08000000 /* HME: Assert RESET to FAS366 */ 129 130/* Values describing the burst-size property from the PROM */ 131#define DMA_BURST1 0x01 132#define DMA_BURST2 0x02 133#define DMA_BURST4 0x04 134#define DMA_BURST8 0x08 135#define DMA_BURST16 0x10 136#define DMA_BURST32 0x20 137#define DMA_BURST64 0x40 138#define DMA_BURSTBITS 0x7f 139 140/* Determine highest possible final transfer address given a base */ 141#define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL)) 142 143/* Yes, I hack a lot of elisp in my spare time... */ 144#define DMA_ERROR_P(regs) ((sbus_readl((regs) + DMA_CSR) & DMA_HNDL_ERROR)) 145#define DMA_IRQ_P(regs) ((sbus_readl((regs) + DMA_CSR)) & (DMA_HNDL_INTR | DMA_HNDL_ERROR)) 146#define DMA_WRITE_P(regs) ((sbus_readl((regs) + DMA_CSR) & DMA_ST_WRITE)) 147#define DMA_OFF(__regs) \ 148do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \ 149 tmp &= ~DMA_ENABLE; \ 150 sbus_writel(tmp, (__regs) + DMA_CSR); \ 151} while(0) 152#define DMA_INTSOFF(__regs) \ 153do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \ 154 tmp &= ~DMA_INT_ENAB; \ 155 sbus_writel(tmp, (__regs) + DMA_CSR); \ 156} while(0) 157#define DMA_INTSON(__regs) \ 158do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \ 159 tmp |= DMA_INT_ENAB; \ 160 sbus_writel(tmp, (__regs) + DMA_CSR); \ 161} while(0) 162#define DMA_PUNTFIFO(__regs) \ 163do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \ 164 tmp |= DMA_FIFO_INV; \ 165 sbus_writel(tmp, (__regs) + DMA_CSR); \ 166} while(0) 167#define DMA_SETSTART(__regs, __addr) \ 168 sbus_writel((u32)(__addr), (__regs) + DMA_ADDR); 169#define DMA_BEGINDMA_W(__regs) \ 170do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \ 171 tmp |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB); \ 172 sbus_writel(tmp, (__regs) + DMA_CSR); \ 173} while(0) 174#define DMA_BEGINDMA_R(__regs) \ 175do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \ 176 tmp |= (DMA_ENABLE|DMA_INT_ENAB); \ 177 tmp &= ~DMA_ST_WRITE; \ 178 sbus_writel(tmp, (__regs) + DMA_CSR); \ 179} while(0) 180 181/* For certain DMA chips, we need to disable ints upon irq entry 182 * and turn them back on when we are done. So in any ESP interrupt 183 * handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT 184 * when leaving the handler. You have been warned... 185 */ 186#define DMA_IRQ_ENTRY(dma, dregs) do { \ 187 if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \ 188 } while (0) 189 190#define DMA_IRQ_EXIT(dma, dregs) do { \ 191 if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \ 192 } while(0) 193 194#define for_each_dvma(dma) \ 195 for((dma) = dma_chain; (dma); (dma) = (dma)->next) 196 197/* From PCI */ 198 199#ifdef CONFIG_PCI 200extern int isa_dma_bridge_buggy; 201#else 202#define isa_dma_bridge_buggy (0) 203#endif 204 205#endif /* !(_ASM_SPARC64_DMA_H) */ 206