1/* $Id: timer.h,v 1.1.1.1 2007/08/03 18:53:36 Exp $ 2 * timer.h: Definitions for the timer chips on the Sparc. 3 * 4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) 5 */ 6 7 8#ifndef _SPARC_TIMER_H 9#define _SPARC_TIMER_H 10 11#include <asm/system.h> /* For SUN4M_NCPUS */ 12#include <asm/sun4paddr.h> 13#include <asm/btfixup.h> 14 15/* Timer structures. The interrupt timer has two properties which 16 * are the counter (which is handled in do_timer in sched.c) and the limit. 17 * This limit is where the timer's counter 'wraps' around. Oddly enough, 18 * the sun4c timer when it hits the limit wraps back to 1 and not zero 19 * thus when calculating the value at which it will fire a microsecond you 20 * must adjust by one. Thanks SUN for designing such great hardware ;( 21 */ 22 23/* Note that I am only going to use the timer that interrupts at 24 * Sparc IRQ 10. There is another one available that can fire at 25 * IRQ 14. Currently it is left untouched, we keep the PROM's limit 26 * register value and let the prom take these interrupts. This allows 27 * L1-A to work. 28 */ 29 30struct sun4c_timer_info { 31 __volatile__ unsigned int cur_count10; 32 __volatile__ unsigned int timer_limit10; 33 __volatile__ unsigned int cur_count14; 34 __volatile__ unsigned int timer_limit14; 35}; 36 37#define SUN4C_TIMER_PHYSADDR 0xf3000000 38#ifdef CONFIG_SUN4 39#define SUN_TIMER_PHYSADDR SUN4_300_TIMER_PHYSADDR 40#else 41#define SUN_TIMER_PHYSADDR SUN4C_TIMER_PHYSADDR 42#endif 43 44/* A sun4m has two blocks of registers which are probably of the same 45 * structure. LSI Logic's L64851 is told to _decrement_ from the limit 46 * value. Aurora behaves similarly but its limit value is compacted in 47 * other fashion (it's wider). Documented fields are defined here. 48 */ 49 50/* As with the interrupt register, we have two classes of timer registers 51 * which are per-cpu and master. Per-cpu timers only hit that cpu and are 52 * only level 14 ticks, master timer hits all cpus and is level 10. 53 */ 54 55#define SUN4M_PRM_CNT_L 0x80000000 56#define SUN4M_PRM_CNT_LVALUE 0x7FFFFC00 57 58struct sun4m_timer_percpu_info { 59 __volatile__ unsigned int l14_timer_limit; /* Initial value is 0x009c4000 */ 60 __volatile__ unsigned int l14_cur_count; 61 62 /* This register appears to be write only and/or inaccessible 63 * on Uni-Processor sun4m machines. 64 */ 65 __volatile__ unsigned int l14_limit_noclear; /* Data access error is here */ 66 67 __volatile__ unsigned int cntrl; /* =1 after POST on Aurora */ 68 __volatile__ unsigned char space[PAGE_SIZE - 16]; 69}; 70 71struct sun4m_timer_regs { 72 struct sun4m_timer_percpu_info cpu_timers[SUN4M_NCPUS]; 73 volatile unsigned int l10_timer_limit; 74 volatile unsigned int l10_cur_count; 75 76 /* Again, this appears to be write only and/or inaccessible 77 * on uni-processor sun4m machines. 78 */ 79 volatile unsigned int l10_limit_noclear; 80 81 /* This register too, it must be magic. */ 82 volatile unsigned int foobar; 83 84 volatile unsigned int cfg; /* equals zero at boot time... */ 85}; 86 87extern struct sun4m_timer_regs *sun4m_timers; 88 89#define SUN4D_PRM_CNT_L 0x80000000 90#define SUN4D_PRM_CNT_LVALUE 0x7FFFFC00 91 92struct sun4d_timer_regs { 93 volatile unsigned int l10_timer_limit; 94 volatile unsigned int l10_cur_countx; 95 volatile unsigned int l10_limit_noclear; 96 volatile unsigned int ctrl; 97 volatile unsigned int l10_cur_count; 98}; 99 100extern struct sun4d_timer_regs *sun4d_timers; 101 102extern __volatile__ unsigned int *master_l10_counter; 103extern __volatile__ unsigned int *master_l10_limit; 104 105BTFIXUPDEF_CALL(int, bus_do_settimeofday, struct timespec *tv) 106#define bus_do_settimeofday(tv) BTFIXUP_CALL(bus_do_settimeofday)(tv) 107 108#endif /* !(_SPARC_TIMER_H) */ 109