1#ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H 2#define __ASM_SH_CPU_SH4_DMA_SH7780_H 3 4#define REQ_HE 0x000000C0 5#define REQ_H 0x00000080 6#define REQ_LE 0x00000040 7#define TM_BURST 0x0000020 8#define TS_8 0x00000000 9#define TS_16 0x00000008 10#define TS_32 0x00000010 11#define TS_16BLK 0x00000018 12#define TS_32BLK 0x00100000 13 14/* 15 * The SuperH DMAC supports a number of transmit sizes, we list them here, 16 * with their respective values as they appear in the CHCR registers. 17 * 18 * Defaults to a 64-bit transfer size. 19 */ 20enum { 21 XMIT_SZ_8BIT, 22 XMIT_SZ_16BIT, 23 XMIT_SZ_32BIT, 24 XMIT_SZ_128BIT, 25 XMIT_SZ_256BIT, 26}; 27 28/* 29 * The DMA count is defined as the number of bytes to transfer. 30 */ 31static unsigned int ts_shift[] __maybe_unused = { 32 [XMIT_SZ_8BIT] = 0, 33 [XMIT_SZ_16BIT] = 1, 34 [XMIT_SZ_32BIT] = 2, 35 [XMIT_SZ_128BIT] = 4, 36 [XMIT_SZ_256BIT] = 5, 37}; 38 39#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */ 40