1#ifndef __ASM_CPU_SH3_DMA_H 2#define __ASM_CPU_SH3_DMA_H 3 4#define SH_DMAC_BASE 0xa4000020 5 6/* Definitions for the SuperH DMAC */ 7#define TM_BURST 0x00000020 8#define TS_8 0x00000000 9#define TS_16 0x00000008 10#define TS_32 0x00000010 11#define TS_128 0x00000018 12 13#define CHCR_TS_MASK 0x18 14#define CHCR_TS_SHIFT 3 15 16#define DMAOR_INIT DMAOR_DME 17 18/* 19 * The SuperH DMAC supports a number of transmit sizes, we list them here, 20 * with their respective values as they appear in the CHCR registers. 21 */ 22enum { 23 XMIT_SZ_8BIT, 24 XMIT_SZ_16BIT, 25 XMIT_SZ_32BIT, 26 XMIT_SZ_128BIT, 27}; 28 29static unsigned int ts_shift[] __maybe_unused = { 30 [XMIT_SZ_8BIT] = 0, 31 [XMIT_SZ_16BIT] = 1, 32 [XMIT_SZ_32BIT] = 2, 33 [XMIT_SZ_128BIT] = 4, 34}; 35 36#endif /* __ASM_CPU_SH3_DMA_H */ 37