1#ifdef __KERNEL__
2#ifndef _ASM_PCI_BRIDGE_H
3#define _ASM_PCI_BRIDGE_H
4
5#include <linux/ioport.h>
6#include <linux/pci.h>
7
8struct device_node;
9struct pci_controller;
10
11/*
12 * pci_io_base returns the memory address at which you can access
13 * the I/O space for PCI bus number `bus' (or NULL on error).
14 */
15extern void __iomem *pci_bus_io_base(unsigned int bus);
16extern unsigned long pci_bus_io_base_phys(unsigned int bus);
17extern unsigned long pci_bus_mem_base_phys(unsigned int bus);
18
19/* Allocate a new PCI host bridge structure */
20extern struct pci_controller* pcibios_alloc_controller(void);
21
22/* Helper function for setting up resources */
23extern void pci_init_resource(struct resource *res, resource_size_t start,
24			      resource_size_t end, int flags, char *name);
25
26/* Get the PCI host controller for a bus */
27extern struct pci_controller* pci_bus_to_hose(int bus);
28
29/* Get the PCI host controller for an OF device */
30extern struct pci_controller*
31pci_find_hose_for_OF_device(struct device_node* node);
32
33/* Fill up host controller resources from the OF node */
34extern void
35pci_process_bridge_OF_ranges(struct pci_controller *hose,
36			   struct device_node *dev, int primary);
37
38/*
39 * Structure of a PCI controller (host bridge)
40 */
41struct pci_controller {
42	int index;			/* PCI domain number */
43	struct pci_controller *next;
44        struct pci_bus *bus;
45	void *arch_data;
46	struct device *parent;
47
48	int first_busno;
49	int last_busno;
50	int bus_offset;
51
52	void __iomem *io_base_virt;
53	resource_size_t io_base_phys;
54
55	/* Some machines (PReP) have a non 1:1 mapping of
56	 * the PCI memory space in the CPU bus space
57	 */
58	resource_size_t pci_mem_offset;
59
60	struct pci_ops *ops;
61	volatile unsigned int __iomem *cfg_addr;
62	volatile void __iomem *cfg_data;
63	/*
64	 * If set, indirect method will set the cfg_type bit as
65	 * needed to generate type 1 configuration transactions.
66	 */
67	int set_cfg_type;
68
69	/* Currently, we limit ourselves to 1 IO range and 3 mem
70	 * ranges since the common pci_bus structure can't handle more
71	 */
72	struct resource	io_resource;
73	struct resource mem_resources[3];
74	int mem_resource_count;
75
76	/* Host bridge I/O and Memory space
77	 * Used for BAR placement algorithms
78	 */
79	struct resource io_space;
80	struct resource mem_space;
81};
82
83static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
84{
85	return bus->sysdata;
86}
87
88/* These are used for config access before all the PCI probing
89   has been done. */
90int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn,
91			   int where, u8 *val);
92int early_read_config_word(struct pci_controller *hose, int bus, int dev_fn,
93			   int where, u16 *val);
94int early_read_config_dword(struct pci_controller *hose, int bus, int dev_fn,
95			    int where, u32 *val);
96int early_write_config_byte(struct pci_controller *hose, int bus, int dev_fn,
97			    int where, u8 val);
98int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn,
99			    int where, u16 val);
100int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn,
101			     int where, u32 val);
102
103extern void setup_indirect_pci_nomap(struct pci_controller* hose,
104			       void __iomem *cfg_addr, void __iomem *cfg_data);
105extern void setup_indirect_pci(struct pci_controller* hose,
106			       u32 cfg_addr, u32 cfg_data);
107extern void setup_grackle(struct pci_controller *hose);
108
109extern unsigned char common_swizzle(struct pci_dev *, unsigned char *);
110
111/*
112 *   The following code swizzles for exactly one bridge.  The routine
113 *   common_swizzle below handles multiple bridges.  But there are a
114 *   some boards that don't follow the PCI spec's suggestion so we
115 *   break this piece out separately.
116 */
117static inline unsigned char bridge_swizzle(unsigned char pin,
118		unsigned char idsel)
119{
120	return (((pin-1) + idsel) % 4) + 1;
121}
122
123/*
124 * The following macro is used to lookup irqs in a standard table
125 * format for those PPC systems that do not already have PCI
126 * interrupts properly routed.
127 */
128#define PCI_IRQ_TABLE_LOOKUP						    \
129({ long _ctl_ = -1; 							    \
130   if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot)    \
131     _ctl_ = pci_irq_table[idsel - min_idsel][pin-1];			    \
132   _ctl_; })
133
134/*
135 * Scan the buses below a given PCI host bridge and assign suitable
136 * resources to all devices found.
137 */
138extern int pciauto_bus_scan(struct pci_controller *, int);
139
140#ifdef CONFIG_PCI
141extern unsigned long pci_address_to_pio(phys_addr_t address);
142#else
143static inline unsigned long pci_address_to_pio(phys_addr_t address)
144{
145	return (unsigned long)-1;
146}
147#endif
148
149#endif
150#endif /* __KERNEL__ */
151