1/* 2 * include/asm-ppc/mpc85xx.h 3 * 4 * MPC85xx definitions 5 * 6 * Maintainer: Kumar Gala <galak@kernel.crashing.org> 7 * 8 * Copyright 2004 Freescale Semiconductor, Inc 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 */ 15 16#ifdef __KERNEL__ 17#ifndef __ASM_MPC85xx_H__ 18#define __ASM_MPC85xx_H__ 19 20#include <asm/mmu.h> 21 22#ifdef CONFIG_85xx 23 24#ifdef CONFIG_MPC8540_ADS 25#include <platforms/85xx/mpc8540_ads.h> 26#endif 27#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS) 28#include <platforms/85xx/mpc8555_cds.h> 29#endif 30#ifdef CONFIG_MPC85xx_CDS 31#include <platforms/85xx/mpc85xx_cds.h> 32#endif 33#ifdef CONFIG_MPC8560_ADS 34#include <platforms/85xx/mpc8560_ads.h> 35#endif 36#ifdef CONFIG_SBC8560 37#include <platforms/85xx/sbc8560.h> 38#endif 39#ifdef CONFIG_STX_GP3 40#include <platforms/85xx/stx_gp3.h> 41#endif 42#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) || \ 43 defined(CONFIG_TQM8560) 44#include <platforms/85xx/tqm85xx.h> 45#endif 46 47/* 48 * The "residual" board information structure the boot loader passes 49 * into the kernel. 50 */ 51extern unsigned char __res[]; 52 53/* Offset from CCSRBAR */ 54#define MPC85xx_CPM_OFFSET (0x80000) 55#define MPC85xx_CPM_SIZE (0x40000) 56#define MPC85xx_DMA_OFFSET (0x21000) 57#define MPC85xx_DMA_SIZE (0x01000) 58#define MPC85xx_DMA0_OFFSET (0x21100) 59#define MPC85xx_DMA0_SIZE (0x00080) 60#define MPC85xx_DMA1_OFFSET (0x21180) 61#define MPC85xx_DMA1_SIZE (0x00080) 62#define MPC85xx_DMA2_OFFSET (0x21200) 63#define MPC85xx_DMA2_SIZE (0x00080) 64#define MPC85xx_DMA3_OFFSET (0x21280) 65#define MPC85xx_DMA3_SIZE (0x00080) 66#define MPC85xx_ENET1_OFFSET (0x24000) 67#define MPC85xx_ENET1_SIZE (0x01000) 68#define MPC85xx_MIIM_OFFSET (0x24520) 69#define MPC85xx_MIIM_SIZE (0x00018) 70#define MPC85xx_ENET2_OFFSET (0x25000) 71#define MPC85xx_ENET2_SIZE (0x01000) 72#define MPC85xx_ENET3_OFFSET (0x26000) 73#define MPC85xx_ENET3_SIZE (0x01000) 74#define MPC85xx_GUTS_OFFSET (0xe0000) 75#define MPC85xx_GUTS_SIZE (0x01000) 76#define MPC85xx_IIC1_OFFSET (0x03000) 77#define MPC85xx_IIC1_SIZE (0x00100) 78#define MPC85xx_OPENPIC_OFFSET (0x40000) 79#define MPC85xx_OPENPIC_SIZE (0x40000) 80#define MPC85xx_PCI1_OFFSET (0x08000) 81#define MPC85xx_PCI1_SIZE (0x01000) 82#define MPC85xx_PCI2_OFFSET (0x09000) 83#define MPC85xx_PCI2_SIZE (0x01000) 84#define MPC85xx_PERFMON_OFFSET (0xe1000) 85#define MPC85xx_PERFMON_SIZE (0x01000) 86#define MPC85xx_SEC2_OFFSET (0x30000) 87#define MPC85xx_SEC2_SIZE (0x10000) 88#define MPC85xx_UART0_OFFSET (0x04500) 89#define MPC85xx_UART0_SIZE (0x00100) 90#define MPC85xx_UART1_OFFSET (0x04600) 91#define MPC85xx_UART1_SIZE (0x00100) 92 93#define MPC85xx_CCSRBAR_SIZE (1024*1024) 94 95/* Let modules/drivers get at CCSRBAR */ 96extern phys_addr_t get_ccsrbar(void); 97 98#ifdef MODULE 99#define CCSRBAR get_ccsrbar() 100#else 101#define CCSRBAR BOARD_CCSRBAR 102#endif 103 104enum ppc_sys_devices { 105 MPC85xx_TSEC1, 106 MPC85xx_TSEC2, 107 MPC85xx_FEC, 108 MPC85xx_IIC1, 109 MPC85xx_DMA0, 110 MPC85xx_DMA1, 111 MPC85xx_DMA2, 112 MPC85xx_DMA3, 113 MPC85xx_DUART, 114 MPC85xx_PERFMON, 115 MPC85xx_SEC2, 116 MPC85xx_CPM_SPI, 117 MPC85xx_CPM_I2C, 118 MPC85xx_CPM_USB, 119 MPC85xx_CPM_SCC1, 120 MPC85xx_CPM_SCC2, 121 MPC85xx_CPM_SCC3, 122 MPC85xx_CPM_SCC4, 123 MPC85xx_CPM_FCC1, 124 MPC85xx_CPM_FCC2, 125 MPC85xx_CPM_FCC3, 126 MPC85xx_CPM_MCC1, 127 MPC85xx_CPM_MCC2, 128 MPC85xx_CPM_SMC1, 129 MPC85xx_CPM_SMC2, 130 MPC85xx_eTSEC1, 131 MPC85xx_eTSEC2, 132 MPC85xx_eTSEC3, 133 MPC85xx_eTSEC4, 134 MPC85xx_IIC2, 135 MPC85xx_MDIO, 136 NUM_PPC_SYS_DEVS, 137}; 138 139/* Internal interrupts are all Level Sensitive, and Positive Polarity */ 140#define MPC85XX_INTERNAL_IRQ_SENSES \ 141 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0 */ \ 142 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1 */ \ 143 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2 */ \ 144 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3 */ \ 145 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4 */ \ 146 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5 */ \ 147 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6 */ \ 148 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7 */ \ 149 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8 */ \ 150 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9 */ \ 151 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10 */ \ 152 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11 */ \ 153 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12 */ \ 154 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13 */ \ 155 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14 */ \ 156 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15 */ \ 157 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16 */ \ 158 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17 */ \ 159 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18 */ \ 160 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19 */ \ 161 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20 */ \ 162 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21 */ \ 163 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22 */ \ 164 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23 */ \ 165 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24 */ \ 166 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25 */ \ 167 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26 */ \ 168 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27 */ \ 169 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28 */ \ 170 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29 */ \ 171 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30 */ \ 172 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31 */ \ 173 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 32 */ \ 174 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 33 */ \ 175 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 34 */ \ 176 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 35 */ \ 177 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 36 */ \ 178 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 37 */ \ 179 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 38 */ \ 180 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 39 */ \ 181 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 40 */ \ 182 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 41 */ \ 183 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 42 */ \ 184 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 43 */ \ 185 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 44 */ \ 186 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 45 */ \ 187 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 46 */ \ 188 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE) /* Internal 47 */ 189 190#endif /* CONFIG_85xx */ 191#endif /* __ASM_MPC85xx_H__ */ 192#endif /* __KERNEL__ */ 193