1/* 2 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved. 3 * 4 * Authors: Shlomi Gridish <gridish@freescale.com> 5 * Li Yang <leoli@freescale.com> 6 * 7 * Description: 8 * QUICC Engine (QE) external definitions and structure. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 */ 15#ifndef _ASM_POWERPC_QE_H 16#define _ASM_POWERPC_QE_H 17#ifdef __KERNEL__ 18 19#include <asm/immap_qe.h> 20 21#define QE_NUM_OF_SNUM 28 22#define QE_NUM_OF_BRGS 16 23#define QE_NUM_OF_PORTS 1024 24 25/* Memory partitions 26*/ 27#define MEM_PART_SYSTEM 0 28#define MEM_PART_SECONDARY 1 29#define MEM_PART_MURAM 2 30 31/* Export QE common operations */ 32extern void qe_reset(void); 33extern int par_io_init(struct device_node *np); 34extern int par_io_of_config(struct device_node *np); 35 36/* QE internal API */ 37int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input); 38void qe_setbrg(u32 brg, u32 rate); 39int qe_get_snum(void); 40void qe_put_snum(u8 snum); 41unsigned long qe_muram_alloc(int size, int align); 42int qe_muram_free(unsigned long offset); 43unsigned long qe_muram_alloc_fixed(unsigned long offset, int size); 44void qe_muram_dump(void); 45void *qe_muram_addr(unsigned long offset); 46 47/* Buffer descriptors */ 48struct qe_bd { 49 u16 status; 50 u16 length; 51 u32 buf; 52} __attribute__ ((packed)); 53 54#define BD_STATUS_MASK 0xffff0000 55#define BD_LENGTH_MASK 0x0000ffff 56 57/* Alignment */ 58#define QE_INTR_TABLE_ALIGN 16 /* ??? */ 59#define QE_ALIGNMENT_OF_BD 8 60#define QE_ALIGNMENT_OF_PRAM 64 61 62/* RISC allocation */ 63enum qe_risc_allocation { 64 QE_RISC_ALLOCATION_RISC1 = 1, /* RISC 1 */ 65 QE_RISC_ALLOCATION_RISC2 = 2, /* RISC 2 */ 66 QE_RISC_ALLOCATION_RISC1_AND_RISC2 = 3 /* Dynamically choose 67 RISC 1 or RISC 2 */ 68}; 69 70/* QE extended filtering Table Lookup Key Size */ 71enum qe_fltr_tbl_lookup_key_size { 72 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES 73 = 0x3f, /* LookupKey parsed by the Generate LookupKey 74 CMD is truncated to 8 bytes */ 75 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES 76 = 0x5f, /* LookupKey parsed by the Generate LookupKey 77 CMD is truncated to 16 bytes */ 78}; 79 80/* QE FLTR extended filtering Largest External Table Lookup Key Size */ 81enum qe_fltr_largest_external_tbl_lookup_key_size { 82 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE 83 = 0x0,/* not used */ 84 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES 85 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES, /* 8 bytes */ 86 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES 87 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES, /* 16 bytes */ 88}; 89 90/* structure representing QE parameter RAM */ 91struct qe_timer_tables { 92 u16 tm_base; /* QE timer table base adr */ 93 u16 tm_ptr; /* QE timer table pointer */ 94 u16 r_tmr; /* QE timer mode register */ 95 u16 r_tmv; /* QE timer valid register */ 96 u32 tm_cmd; /* QE timer cmd register */ 97 u32 tm_cnt; /* QE timer internal cnt */ 98} __attribute__ ((packed)); 99 100#define QE_FLTR_TAD_SIZE 8 101 102/* QE extended filtering Termination Action Descriptor (TAD) */ 103struct qe_fltr_tad { 104 u8 serialized[QE_FLTR_TAD_SIZE]; 105} __attribute__ ((packed)); 106 107/* Communication Direction */ 108enum comm_dir { 109 COMM_DIR_NONE = 0, 110 COMM_DIR_RX = 1, 111 COMM_DIR_TX = 2, 112 COMM_DIR_RX_AND_TX = 3 113}; 114 115/* Clocks and BRGs */ 116enum qe_clock { 117 QE_CLK_NONE = 0, 118 QE_BRG1, /* Baud Rate Generator 1 */ 119 QE_BRG2, /* Baud Rate Generator 2 */ 120 QE_BRG3, /* Baud Rate Generator 3 */ 121 QE_BRG4, /* Baud Rate Generator 4 */ 122 QE_BRG5, /* Baud Rate Generator 5 */ 123 QE_BRG6, /* Baud Rate Generator 6 */ 124 QE_BRG7, /* Baud Rate Generator 7 */ 125 QE_BRG8, /* Baud Rate Generator 8 */ 126 QE_BRG9, /* Baud Rate Generator 9 */ 127 QE_BRG10, /* Baud Rate Generator 10 */ 128 QE_BRG11, /* Baud Rate Generator 11 */ 129 QE_BRG12, /* Baud Rate Generator 12 */ 130 QE_BRG13, /* Baud Rate Generator 13 */ 131 QE_BRG14, /* Baud Rate Generator 14 */ 132 QE_BRG15, /* Baud Rate Generator 15 */ 133 QE_BRG16, /* Baud Rate Generator 16 */ 134 QE_CLK1, /* Clock 1 */ 135 QE_CLK2, /* Clock 2 */ 136 QE_CLK3, /* Clock 3 */ 137 QE_CLK4, /* Clock 4 */ 138 QE_CLK5, /* Clock 5 */ 139 QE_CLK6, /* Clock 6 */ 140 QE_CLK7, /* Clock 7 */ 141 QE_CLK8, /* Clock 8 */ 142 QE_CLK9, /* Clock 9 */ 143 QE_CLK10, /* Clock 10 */ 144 QE_CLK11, /* Clock 11 */ 145 QE_CLK12, /* Clock 12 */ 146 QE_CLK13, /* Clock 13 */ 147 QE_CLK14, /* Clock 14 */ 148 QE_CLK15, /* Clock 15 */ 149 QE_CLK16, /* Clock 16 */ 150 QE_CLK17, /* Clock 17 */ 151 QE_CLK18, /* Clock 18 */ 152 QE_CLK19, /* Clock 19 */ 153 QE_CLK20, /* Clock 20 */ 154 QE_CLK21, /* Clock 21 */ 155 QE_CLK22, /* Clock 22 */ 156 QE_CLK23, /* Clock 23 */ 157 QE_CLK24, /* Clock 24 */ 158 QE_CLK_DUMMY, 159}; 160 161/* QE CMXUCR Registers. 162 * There are two UCCs represented in each of the four CMXUCR registers. 163 * These values are for the UCC in the LSBs 164 */ 165#define QE_CMXUCR_MII_ENET_MNG 0x00007000 166#define QE_CMXUCR_MII_ENET_MNG_SHIFT 12 167#define QE_CMXUCR_GRANT 0x00008000 168#define QE_CMXUCR_TSA 0x00004000 169#define QE_CMXUCR_BKPT 0x00000100 170#define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F 171 172/* QE CMXGCR Registers. 173*/ 174#define QE_CMXGCR_MII_ENET_MNG 0x00007000 175#define QE_CMXGCR_MII_ENET_MNG_SHIFT 12 176#define QE_CMXGCR_USBCS 0x0000000f 177 178/* QE CECR Commands. 179*/ 180#define QE_CR_FLG 0x00010000 181#define QE_RESET 0x80000000 182#define QE_INIT_TX_RX 0x00000000 183#define QE_INIT_RX 0x00000001 184#define QE_INIT_TX 0x00000002 185#define QE_ENTER_HUNT_MODE 0x00000003 186#define QE_STOP_TX 0x00000004 187#define QE_GRACEFUL_STOP_TX 0x00000005 188#define QE_RESTART_TX 0x00000006 189#define QE_CLOSE_RX_BD 0x00000007 190#define QE_SWITCH_COMMAND 0x00000007 191#define QE_SET_GROUP_ADDRESS 0x00000008 192#define QE_START_IDMA 0x00000009 193#define QE_MCC_STOP_RX 0x00000009 194#define QE_ATM_TRANSMIT 0x0000000a 195#define QE_HPAC_CLEAR_ALL 0x0000000b 196#define QE_GRACEFUL_STOP_RX 0x0000001a 197#define QE_RESTART_RX 0x0000001b 198#define QE_HPAC_SET_PRIORITY 0x0000010b 199#define QE_HPAC_STOP_TX 0x0000020b 200#define QE_HPAC_STOP_RX 0x0000030b 201#define QE_HPAC_GRACEFUL_STOP_TX 0x0000040b 202#define QE_HPAC_GRACEFUL_STOP_RX 0x0000050b 203#define QE_HPAC_START_TX 0x0000060b 204#define QE_HPAC_START_RX 0x0000070b 205#define QE_USB_STOP_TX 0x0000000a 206#define QE_USB_RESTART_TX 0x0000000b 207#define QE_QMC_STOP_TX 0x0000000c 208#define QE_QMC_STOP_RX 0x0000000d 209#define QE_SS7_SU_FIL_RESET 0x0000000e 210/* jonathbr added from here down for 83xx */ 211#define QE_RESET_BCS 0x0000000a 212#define QE_MCC_INIT_TX_RX_16 0x00000003 213#define QE_MCC_STOP_TX 0x00000004 214#define QE_MCC_INIT_TX_1 0x00000005 215#define QE_MCC_INIT_RX_1 0x00000006 216#define QE_MCC_RESET 0x00000007 217#define QE_SET_TIMER 0x00000008 218#define QE_RANDOM_NUMBER 0x0000000c 219#define QE_ATM_MULTI_THREAD_INIT 0x00000011 220#define QE_ASSIGN_PAGE 0x00000012 221#define QE_ADD_REMOVE_HASH_ENTRY 0x00000013 222#define QE_START_FLOW_CONTROL 0x00000014 223#define QE_STOP_FLOW_CONTROL 0x00000015 224#define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016 225 226#define QE_ASSIGN_RISC 0x00000010 227#define QE_CR_MCN_NORMAL_SHIFT 6 228#define QE_CR_MCN_USB_SHIFT 4 229#define QE_CR_MCN_RISC_ASSIGN_SHIFT 8 230#define QE_CR_SNUM_SHIFT 17 231 232/* QE CECR Sub Block - sub block of QE command. 233*/ 234#define QE_CR_SUBBLOCK_INVALID 0x00000000 235#define QE_CR_SUBBLOCK_USB 0x03200000 236#define QE_CR_SUBBLOCK_UCCFAST1 0x02000000 237#define QE_CR_SUBBLOCK_UCCFAST2 0x02200000 238#define QE_CR_SUBBLOCK_UCCFAST3 0x02400000 239#define QE_CR_SUBBLOCK_UCCFAST4 0x02600000 240#define QE_CR_SUBBLOCK_UCCFAST5 0x02800000 241#define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000 242#define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000 243#define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000 244#define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000 245#define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000 246#define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000 247#define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000 248#define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000 249#define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000 250#define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000 251#define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000 252#define QE_CR_SUBBLOCK_MCC1 0x03800000 253#define QE_CR_SUBBLOCK_MCC2 0x03a00000 254#define QE_CR_SUBBLOCK_MCC3 0x03000000 255#define QE_CR_SUBBLOCK_IDMA1 0x02800000 256#define QE_CR_SUBBLOCK_IDMA2 0x02a00000 257#define QE_CR_SUBBLOCK_IDMA3 0x02c00000 258#define QE_CR_SUBBLOCK_IDMA4 0x02e00000 259#define QE_CR_SUBBLOCK_HPAC 0x01e00000 260#define QE_CR_SUBBLOCK_SPI1 0x01400000 261#define QE_CR_SUBBLOCK_SPI2 0x01600000 262#define QE_CR_SUBBLOCK_RAND 0x01c00000 263#define QE_CR_SUBBLOCK_TIMER 0x01e00000 264#define QE_CR_SUBBLOCK_GENERAL 0x03c00000 265 266/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */ 267#define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */ 268#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00 269#define QE_CR_PROTOCOL_ATM_POS 0x0A 270#define QE_CR_PROTOCOL_ETHERNET 0x0C 271#define QE_CR_PROTOCOL_L2_SWITCH 0x0D 272 273/* BMR byte order */ 274#define QE_BMR_BYTE_ORDER_BO_PPC 0x08 /* powerpc little endian */ 275#define QE_BMR_BYTE_ORDER_BO_MOT 0x10 /* motorola big endian */ 276#define QE_BMR_BYTE_ORDER_BO_MAX 0x18 277 278/* BRG configuration register */ 279#define QE_BRGC_ENABLE 0x00010000 280#define QE_BRGC_DIVISOR_SHIFT 1 281#define QE_BRGC_DIVISOR_MAX 0xFFF 282#define QE_BRGC_DIV16 1 283 284/* QE Timers registers */ 285#define QE_GTCFR1_PCAS 0x80 286#define QE_GTCFR1_STP2 0x20 287#define QE_GTCFR1_RST2 0x10 288#define QE_GTCFR1_GM2 0x08 289#define QE_GTCFR1_GM1 0x04 290#define QE_GTCFR1_STP1 0x02 291#define QE_GTCFR1_RST1 0x01 292 293/* SDMA registers */ 294#define QE_SDSR_BER1 0x02000000 295#define QE_SDSR_BER2 0x01000000 296 297#define QE_SDMR_GLB_1_MSK 0x80000000 298#define QE_SDMR_ADR_SEL 0x20000000 299#define QE_SDMR_BER1_MSK 0x02000000 300#define QE_SDMR_BER2_MSK 0x01000000 301#define QE_SDMR_EB1_MSK 0x00800000 302#define QE_SDMR_ER1_MSK 0x00080000 303#define QE_SDMR_ER2_MSK 0x00040000 304#define QE_SDMR_CEN_MASK 0x0000E000 305#define QE_SDMR_SBER_1 0x00000200 306#define QE_SDMR_SBER_2 0x00000200 307#define QE_SDMR_EB1_PR_MASK 0x000000C0 308#define QE_SDMR_ER1_PR 0x00000008 309 310#define QE_SDMR_CEN_SHIFT 13 311#define QE_SDMR_EB1_PR_SHIFT 6 312 313#define QE_SDTM_MSNUM_SHIFT 24 314 315#define QE_SDEBCR_BA_MASK 0x01FFFFFF 316 317/* UPC */ 318#define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */ 319#define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */ 320#define UPGCR_RMS 0x20000000 /* Receive master/slave mode */ 321#define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing */ 322#define UPGCR_DIAG 0x01000000 /* Diagnostic mode */ 323 324/* UCC */ 325#define UCC_GUEMR_MODE_MASK_RX 0x02 326#define UCC_GUEMR_MODE_MASK_TX 0x01 327#define UCC_GUEMR_MODE_FAST_RX 0x02 328#define UCC_GUEMR_MODE_FAST_TX 0x01 329#define UCC_GUEMR_MODE_SLOW_RX 0x00 330#define UCC_GUEMR_MODE_SLOW_TX 0x00 331#define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 in the guemr is reserved but 332 must be set 1 */ 333 334/* structure representing UCC SLOW parameter RAM */ 335struct ucc_slow_pram { 336 u16 rbase; /* RX BD base address */ 337 u16 tbase; /* TX BD base address */ 338 u8 rfcr; /* Rx function code */ 339 u8 tfcr; /* Tx function code */ 340 u16 mrblr; /* Rx buffer length */ 341 u32 rstate; /* Rx internal state */ 342 u32 rptr; /* Rx internal data pointer */ 343 u16 rbptr; /* rb BD Pointer */ 344 u16 rcount; /* Rx internal byte count */ 345 u32 rtemp; /* Rx temp */ 346 u32 tstate; /* Tx internal state */ 347 u32 tptr; /* Tx internal data pointer */ 348 u16 tbptr; /* Tx BD pointer */ 349 u16 tcount; /* Tx byte count */ 350 u32 ttemp; /* Tx temp */ 351 u32 rcrc; /* temp receive CRC */ 352 u32 tcrc; /* temp transmit CRC */ 353} __attribute__ ((packed)); 354 355/* General UCC SLOW Mode Register (GUMRH & GUMRL) */ 356#define UCC_SLOW_GUMR_H_CRC16 0x00004000 357#define UCC_SLOW_GUMR_H_CRC16CCITT 0x00000000 358#define UCC_SLOW_GUMR_H_CRC32CCITT 0x00008000 359#define UCC_SLOW_GUMR_H_REVD 0x00002000 360#define UCC_SLOW_GUMR_H_TRX 0x00001000 361#define UCC_SLOW_GUMR_H_TTX 0x00000800 362#define UCC_SLOW_GUMR_H_CDP 0x00000400 363#define UCC_SLOW_GUMR_H_CTSP 0x00000200 364#define UCC_SLOW_GUMR_H_CDS 0x00000100 365#define UCC_SLOW_GUMR_H_CTSS 0x00000080 366#define UCC_SLOW_GUMR_H_TFL 0x00000040 367#define UCC_SLOW_GUMR_H_RFW 0x00000020 368#define UCC_SLOW_GUMR_H_TXSY 0x00000010 369#define UCC_SLOW_GUMR_H_4SYNC 0x00000004 370#define UCC_SLOW_GUMR_H_8SYNC 0x00000008 371#define UCC_SLOW_GUMR_H_16SYNC 0x0000000c 372#define UCC_SLOW_GUMR_H_RTSM 0x00000002 373#define UCC_SLOW_GUMR_H_RSYN 0x00000001 374 375#define UCC_SLOW_GUMR_L_TCI 0x10000000 376#define UCC_SLOW_GUMR_L_RINV 0x02000000 377#define UCC_SLOW_GUMR_L_TINV 0x01000000 378#define UCC_SLOW_GUMR_L_TEND 0x00020000 379#define UCC_SLOW_GUMR_L_ENR 0x00000020 380#define UCC_SLOW_GUMR_L_ENT 0x00000010 381 382/* General UCC FAST Mode Register */ 383#define UCC_FAST_GUMR_TCI 0x20000000 384#define UCC_FAST_GUMR_TRX 0x10000000 385#define UCC_FAST_GUMR_TTX 0x08000000 386#define UCC_FAST_GUMR_CDP 0x04000000 387#define UCC_FAST_GUMR_CTSP 0x02000000 388#define UCC_FAST_GUMR_CDS 0x01000000 389#define UCC_FAST_GUMR_CTSS 0x00800000 390#define UCC_FAST_GUMR_TXSY 0x00020000 391#define UCC_FAST_GUMR_RSYN 0x00010000 392#define UCC_FAST_GUMR_RTSM 0x00002000 393#define UCC_FAST_GUMR_REVD 0x00000400 394#define UCC_FAST_GUMR_ENR 0x00000020 395#define UCC_FAST_GUMR_ENT 0x00000010 396 397/* Slow UCC Event Register (UCCE) */ 398#define UCC_SLOW_UCCE_GLR 0x1000 399#define UCC_SLOW_UCCE_GLT 0x0800 400#define UCC_SLOW_UCCE_DCC 0x0400 401#define UCC_SLOW_UCCE_FLG 0x0200 402#define UCC_SLOW_UCCE_AB 0x0200 403#define UCC_SLOW_UCCE_IDLE 0x0100 404#define UCC_SLOW_UCCE_GRA 0x0080 405#define UCC_SLOW_UCCE_TXE 0x0010 406#define UCC_SLOW_UCCE_RXF 0x0008 407#define UCC_SLOW_UCCE_CCR 0x0008 408#define UCC_SLOW_UCCE_RCH 0x0008 409#define UCC_SLOW_UCCE_BSY 0x0004 410#define UCC_SLOW_UCCE_TXB 0x0002 411#define UCC_SLOW_UCCE_TX 0x0002 412#define UCC_SLOW_UCCE_RX 0x0001 413#define UCC_SLOW_UCCE_GOV 0x0001 414#define UCC_SLOW_UCCE_GUN 0x0002 415#define UCC_SLOW_UCCE_GINT 0x0004 416#define UCC_SLOW_UCCE_IQOV 0x0008 417 418#define UCC_SLOW_UCCE_HDLC_SET (UCC_SLOW_UCCE_TXE | UCC_SLOW_UCCE_BSY | \ 419 UCC_SLOW_UCCE_GRA | UCC_SLOW_UCCE_TXB | UCC_SLOW_UCCE_RXF | \ 420 UCC_SLOW_UCCE_DCC | UCC_SLOW_UCCE_GLT | UCC_SLOW_UCCE_GLR) 421#define UCC_SLOW_UCCE_ENET_SET (UCC_SLOW_UCCE_TXE | UCC_SLOW_UCCE_BSY | \ 422 UCC_SLOW_UCCE_GRA | UCC_SLOW_UCCE_TXB | UCC_SLOW_UCCE_RXF) 423#define UCC_SLOW_UCCE_TRANS_SET (UCC_SLOW_UCCE_TXE | UCC_SLOW_UCCE_BSY | \ 424 UCC_SLOW_UCCE_GRA | UCC_SLOW_UCCE_TX | UCC_SLOW_UCCE_RX | \ 425 UCC_SLOW_UCCE_DCC | UCC_SLOW_UCCE_GLT | UCC_SLOW_UCCE_GLR) 426#define UCC_SLOW_UCCE_UART_SET (UCC_SLOW_UCCE_BSY | UCC_SLOW_UCCE_GRA | \ 427 UCC_SLOW_UCCE_TXB | UCC_SLOW_UCCE_TX | UCC_SLOW_UCCE_RX | \ 428 UCC_SLOW_UCCE_GLT | UCC_SLOW_UCCE_GLR) 429#define UCC_SLOW_UCCE_QMC_SET (UCC_SLOW_UCCE_IQOV | UCC_SLOW_UCCE_GINT | \ 430 UCC_SLOW_UCCE_GUN | UCC_SLOW_UCCE_GOV) 431 432#define UCC_SLOW_UCCE_OTHER (UCC_SLOW_UCCE_TXE | UCC_SLOW_UCCE_BSY | \ 433 UCC_SLOW_UCCE_GRA | UCC_SLOW_UCCE_DCC | UCC_SLOW_UCCE_GLT | \ 434 UCC_SLOW_UCCE_GLR) 435 436#define UCC_SLOW_INTR_TX UCC_SLOW_UCCE_TXB 437#define UCC_SLOW_INTR_RX (UCC_SLOW_UCCE_RXF | UCC_SLOW_UCCE_RX) 438#define UCC_SLOW_INTR (UCC_SLOW_INTR_TX | UCC_SLOW_INTR_RX) 439 440/* UCC Transmit On Demand Register (UTODR) */ 441#define UCC_SLOW_TOD 0x8000 442#define UCC_FAST_TOD 0x8000 443 444/* Function code masks */ 445#define FC_GBL 0x20 446#define FC_DTB_LCL 0x02 447#define UCC_FAST_FUNCTION_CODE_GBL 0x20 448#define UCC_FAST_FUNCTION_CODE_DTB_LCL 0x02 449#define UCC_FAST_FUNCTION_CODE_BDB_LCL 0x01 450 451#endif /* __KERNEL__ */ 452#endif /* _ASM_POWERPC_QE_H */ 453