1/*
2 * include/asm-powerpc/paca.h
3 *
4 * This control block defines the PACA which defines the processor
5 * specific data for each logical processor on the system.
6 * There are some pointers defined that are utilized by PLIC.
7 *
8 * C 2001 PPC 64 Team, IBM Corp
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15#ifndef _ASM_POWERPC_PACA_H
16#define _ASM_POWERPC_PACA_H
17#ifdef __KERNEL__
18
19#include	<asm/types.h>
20#include	<asm/lppaca.h>
21#include	<asm/mmu.h>
22
23register struct paca_struct *local_paca asm("r13");
24#define get_paca()	local_paca
25#define get_lppaca()	(get_paca()->lppaca_ptr)
26#define get_slb_shadow()	(get_paca()->slb_shadow_ptr)
27
28struct task_struct;
29
30/*
31 * Defines the layout of the paca.
32 *
33 * This structure is not directly accessed by firmware or the service
34 * processor except for the first two pointers that point to the
35 * lppaca area and the ItLpRegSave area for this CPU.  The lppaca
36 * object is currently contained within the PACA but it doesn't need
37 * to be.
38 */
39struct paca_struct {
40	/*
41	 * Because hw_cpu_id, unlike other paca fields, is accessed
42	 * routinely from other CPUs (from the IRQ code), we stick to
43	 * read-only (after boot) fields in the first cacheline to
44	 * avoid cacheline bouncing.
45	 */
46
47	/*
48	 * MAGIC: These first two pointers can't be moved - they're
49	 * accessed by the firmware
50	 */
51	struct lppaca *lppaca_ptr;	/* Pointer to LpPaca for PLIC */
52#ifdef CONFIG_PPC_ISERIES
53	void *reg_save_ptr; /* Pointer to LpRegSave for PLIC */
54#endif /* CONFIG_PPC_ISERIES */
55
56	/*
57	 * MAGIC: the spinlock functions in arch/powerpc/lib/locks.c
58	 * load lock_token and paca_index with a single lwz
59	 * instruction.  They must travel together and be properly
60	 * aligned.
61	 */
62	u16 lock_token;			/* Constant 0x8000, used in locks */
63	u16 paca_index;			/* Logical processor number */
64
65	u64 kernel_toc;			/* Kernel TOC address */
66	u64 stab_real;			/* Absolute address of segment table */
67	u64 stab_addr;			/* Virtual address of segment table */
68	void *emergency_sp;		/* pointer to emergency stack */
69	u64 data_offset;		/* per cpu data offset */
70	s16 hw_cpu_id;			/* Physical processor number */
71	u8 cpu_start;			/* At startup, processor spins until */
72					/* this becomes non-zero. */
73	struct slb_shadow *slb_shadow_ptr;
74
75	/*
76	 * Now, starting in cacheline 2, the exception save areas
77	 */
78	/* used for most interrupts/exceptions */
79	u64 exgen[10] __attribute__((aligned(0x80)));
80	u64 exmc[10];		/* used for machine checks */
81	u64 exslb[10];		/* used for SLB/segment table misses
82 				 * on the linear mapping */
83
84	mm_context_t context;
85	u16 vmalloc_sllp;
86	u16 slb_cache_ptr;
87	u16 slb_cache[SLB_CACHE_ENTRIES];
88
89	/*
90	 * then miscellaneous read-write fields
91	 */
92	struct task_struct *__current;	/* Pointer to current */
93	u64 kstack;			/* Saved Kernel stack addr */
94	u64 stab_rr;			/* stab/slb round-robin counter */
95	u64 saved_r1;			/* r1 save for RTAS calls */
96	u64 saved_msr;			/* MSR saved here by enter_rtas */
97	u16 trap_save;			/* Used when bad stack is encountered */
98	u8 soft_enabled;		/* irq soft-enable flag */
99	u8 hard_enabled;		/* set if irqs are enabled in MSR */
100	u8 io_sync;			/* writel() needs spin_unlock sync */
101
102	/* Stuff for accurate time accounting */
103	u64 user_time;			/* accumulated usermode TB ticks */
104	u64 system_time;		/* accumulated system TB ticks */
105	u64 startpurr;			/* PURR/TB value snapshot */
106};
107
108extern struct paca_struct paca[];
109
110void setup_boot_paca(void);
111
112#endif /* __KERNEL__ */
113#endif /* _ASM_POWERPC_PACA_H */
114