1/* 2 * Common definitions for TX3927/TX4927 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 2000 Toshiba Corporation 9 */ 10#ifndef __ASM_TXX927_H 11#define __ASM_TXX927_H 12 13struct txx927_tmr_reg { 14 volatile unsigned long tcr; 15 volatile unsigned long tisr; 16 volatile unsigned long cpra; 17 volatile unsigned long cprb; 18 volatile unsigned long itmr; 19 volatile unsigned long unused0[3]; 20 volatile unsigned long ccdr; 21 volatile unsigned long unused1[3]; 22 volatile unsigned long pgmr; 23 volatile unsigned long unused2[3]; 24 volatile unsigned long wtmr; 25 volatile unsigned long unused3[43]; 26 volatile unsigned long trr; 27}; 28 29struct txx927_sio_reg { 30 volatile unsigned long lcr; 31 volatile unsigned long dicr; 32 volatile unsigned long disr; 33 volatile unsigned long cisr; 34 volatile unsigned long fcr; 35 volatile unsigned long flcr; 36 volatile unsigned long bgr; 37 volatile unsigned long tfifo; 38 volatile unsigned long rfifo; 39}; 40 41struct txx927_pio_reg { 42 volatile unsigned long dout; 43 volatile unsigned long din; 44 volatile unsigned long dir; 45 volatile unsigned long od; 46 volatile unsigned long flag[2]; 47 volatile unsigned long pol; 48 volatile unsigned long intc; 49 volatile unsigned long maskcpu; 50 volatile unsigned long maskext; 51}; 52 53/* 54 * TMR 55 */ 56/* TMTCR : Timer Control */ 57#define TXx927_TMTCR_TCE 0x00000080 58#define TXx927_TMTCR_CCDE 0x00000040 59#define TXx927_TMTCR_CRE 0x00000020 60#define TXx927_TMTCR_ECES 0x00000008 61#define TXx927_TMTCR_CCS 0x00000004 62#define TXx927_TMTCR_TMODE_MASK 0x00000003 63#define TXx927_TMTCR_TMODE_ITVL 0x00000000 64 65/* TMTISR : Timer Int. Status */ 66#define TXx927_TMTISR_TPIBS 0x00000004 67#define TXx927_TMTISR_TPIAS 0x00000002 68#define TXx927_TMTISR_TIIS 0x00000001 69 70/* TMTITMR : Interval Timer Mode */ 71#define TXx927_TMTITMR_TIIE 0x00008000 72#define TXx927_TMTITMR_TZCE 0x00000001 73 74/* 75 * SIO 76 */ 77/* SILCR : Line Control */ 78#define TXx927_SILCR_SCS_MASK 0x00000060 79#define TXx927_SILCR_SCS_IMCLK 0x00000000 80#define TXx927_SILCR_SCS_IMCLK_BG 0x00000020 81#define TXx927_SILCR_SCS_SCLK 0x00000040 82#define TXx927_SILCR_SCS_SCLK_BG 0x00000060 83#define TXx927_SILCR_UEPS 0x00000010 84#define TXx927_SILCR_UPEN 0x00000008 85#define TXx927_SILCR_USBL_MASK 0x00000004 86#define TXx927_SILCR_USBL_1BIT 0x00000004 87#define TXx927_SILCR_USBL_2BIT 0x00000000 88#define TXx927_SILCR_UMODE_MASK 0x00000003 89#define TXx927_SILCR_UMODE_8BIT 0x00000000 90#define TXx927_SILCR_UMODE_7BIT 0x00000001 91 92/* SIDICR : DMA/Int. Control */ 93#define TXx927_SIDICR_TDE 0x00008000 94#define TXx927_SIDICR_RDE 0x00004000 95#define TXx927_SIDICR_TIE 0x00002000 96#define TXx927_SIDICR_RIE 0x00001000 97#define TXx927_SIDICR_SPIE 0x00000800 98#define TXx927_SIDICR_CTSAC 0x00000600 99#define TXx927_SIDICR_STIE_MASK 0x0000003f 100#define TXx927_SIDICR_STIE_OERS 0x00000020 101#define TXx927_SIDICR_STIE_CTSS 0x00000010 102#define TXx927_SIDICR_STIE_RBRKD 0x00000008 103#define TXx927_SIDICR_STIE_TRDY 0x00000004 104#define TXx927_SIDICR_STIE_TXALS 0x00000002 105#define TXx927_SIDICR_STIE_UBRKD 0x00000001 106 107/* SIDISR : DMA/Int. Status */ 108#define TXx927_SIDISR_UBRK 0x00008000 109#define TXx927_SIDISR_UVALID 0x00004000 110#define TXx927_SIDISR_UFER 0x00002000 111#define TXx927_SIDISR_UPER 0x00001000 112#define TXx927_SIDISR_UOER 0x00000800 113#define TXx927_SIDISR_ERI 0x00000400 114#define TXx927_SIDISR_TOUT 0x00000200 115#define TXx927_SIDISR_TDIS 0x00000100 116#define TXx927_SIDISR_RDIS 0x00000080 117#define TXx927_SIDISR_STIS 0x00000040 118#define TXx927_SIDISR_RFDN_MASK 0x0000001f 119 120/* SICISR : Change Int. Status */ 121#define TXx927_SICISR_OERS 0x00000020 122#define TXx927_SICISR_CTSS 0x00000010 123#define TXx927_SICISR_RBRKD 0x00000008 124#define TXx927_SICISR_TRDY 0x00000004 125#define TXx927_SICISR_TXALS 0x00000002 126#define TXx927_SICISR_UBRKD 0x00000001 127 128/* SIFCR : FIFO Control */ 129#define TXx927_SIFCR_SWRST 0x00008000 130#define TXx927_SIFCR_RDIL_MASK 0x00000180 131#define TXx927_SIFCR_RDIL_1 0x00000000 132#define TXx927_SIFCR_RDIL_4 0x00000080 133#define TXx927_SIFCR_RDIL_8 0x00000100 134#define TXx927_SIFCR_RDIL_12 0x00000180 135#define TXx927_SIFCR_RDIL_MAX 0x00000180 136#define TXx927_SIFCR_TDIL_MASK 0x00000018 137#define TXx927_SIFCR_TDIL_MASK 0x00000018 138#define TXx927_SIFCR_TDIL_1 0x00000000 139#define TXx927_SIFCR_TDIL_4 0x00000001 140#define TXx927_SIFCR_TDIL_8 0x00000010 141#define TXx927_SIFCR_TDIL_MAX 0x00000010 142#define TXx927_SIFCR_TFRST 0x00000004 143#define TXx927_SIFCR_RFRST 0x00000002 144#define TXx927_SIFCR_FRSTE 0x00000001 145#define TXx927_SIO_TX_FIFO 8 146#define TXx927_SIO_RX_FIFO 16 147 148/* SIFLCR : Flow Control */ 149#define TXx927_SIFLCR_RCS 0x00001000 150#define TXx927_SIFLCR_TES 0x00000800 151#define TXx927_SIFLCR_RTSSC 0x00000200 152#define TXx927_SIFLCR_RSDE 0x00000100 153#define TXx927_SIFLCR_TSDE 0x00000080 154#define TXx927_SIFLCR_RTSTL_MASK 0x0000001e 155#define TXx927_SIFLCR_RTSTL_MAX 0x0000001e 156#define TXx927_SIFLCR_TBRK 0x00000001 157 158/* SIBGR : Baudrate Control */ 159#define TXx927_SIBGR_BCLK_MASK 0x00000300 160#define TXx927_SIBGR_BCLK_T0 0x00000000 161#define TXx927_SIBGR_BCLK_T2 0x00000100 162#define TXx927_SIBGR_BCLK_T4 0x00000200 163#define TXx927_SIBGR_BCLK_T6 0x00000300 164#define TXx927_SIBGR_BRD_MASK 0x000000ff 165 166/* 167 * PIO 168 */ 169 170#endif /* __ASM_TXX927_H */ 171