1/****************************************************************************/ 2 3/* 4 * mcfuart.h -- ColdFire internal UART support defines. 5 * 6 * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com) 7 * (C) Copyright 2000, Lineo Inc. (www.lineo.com) 8 */ 9 10/****************************************************************************/ 11#ifndef mcfuart_h 12#define mcfuart_h 13/****************************************************************************/ 14 15 16/* 17 * Define the base address of the UARTS within the MBAR address 18 * space. 19 */ 20#if defined(CONFIG_M5272) 21#define MCFUART_BASE1 0x100 /* Base address of UART1 */ 22#define MCFUART_BASE2 0x140 /* Base address of UART2 */ 23#elif defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e) 24#if defined(CONFIG_NETtel) 25#define MCFUART_BASE1 0x180 /* Base address of UART1 */ 26#define MCFUART_BASE2 0x140 /* Base address of UART2 */ 27#else 28#define MCFUART_BASE1 0x140 /* Base address of UART1 */ 29#define MCFUART_BASE2 0x180 /* Base address of UART2 */ 30#endif 31#elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) 32#define MCFUART_BASE1 0x200 /* Base address of UART1 */ 33#define MCFUART_BASE2 0x240 /* Base address of UART2 */ 34#define MCFUART_BASE3 0x280 /* Base address of UART3 */ 35#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) 36#if defined(CONFIG_NETtel) || defined(CONFIG_DISKtel) || defined(CONFIG_SECUREEDGEMP3) 37#define MCFUART_BASE1 0x200 /* Base address of UART1 */ 38#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */ 39#else 40#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ 41#define MCFUART_BASE2 0x200 /* Base address of UART2 */ 42#endif 43#elif defined(CONFIG_M520x) 44#define MCFUART_BASE1 0x60000 /* Base address of UART1 */ 45#define MCFUART_BASE2 0x64000 /* Base address of UART2 */ 46#define MCFUART_BASE3 0x68000 /* Base address of UART2 */ 47#elif defined(CONFIG_M532x) 48#define MCFUART_BASE1 0xfc060000 /* Base address of UART1 */ 49#define MCFUART_BASE2 0xfc064000 /* Base address of UART2 */ 50#define MCFUART_BASE3 0xfc068000 /* Base address of UART3 */ 51#endif 52 53 54/* 55 * Define the ColdFire UART register set addresses. 56 */ 57#define MCFUART_UMR 0x00 /* Mode register (r/w) */ 58#define MCFUART_USR 0x04 /* Status register (r) */ 59#define MCFUART_UCSR 0x04 /* Clock Select (w) */ 60#define MCFUART_UCR 0x08 /* Command register (w) */ 61#define MCFUART_URB 0x0c /* Receiver Buffer (r) */ 62#define MCFUART_UTB 0x0c /* Transmit Buffer (w) */ 63#define MCFUART_UIPCR 0x10 /* Input Port Change (r) */ 64#define MCFUART_UACR 0x10 /* Auxiliary Control (w) */ 65#define MCFUART_UISR 0x14 /* Interrup Status (r) */ 66#define MCFUART_UIMR 0x14 /* Interrupt Mask (w) */ 67#define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */ 68#define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */ 69#ifdef CONFIG_M5272 70#define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */ 71#define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */ 72#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */ 73#else 74#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */ 75#endif 76#define MCFUART_UIPR 0x34 /* Input Port (r) */ 77#define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */ 78#define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */ 79 80 81/* 82 * Define bit flags in Mode Register 1 (MR1). 83 */ 84#define MCFUART_MR1_RXRTS 0x80 /* Auto RTS flow control */ 85#define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */ 86#define MCFUART_MR1_RXIRQRDY 0x00 /* RX IRQ type RDY */ 87#define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */ 88#define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */ 89 90#define MCFUART_MR1_PARITYNONE 0x10 /* No parity */ 91#define MCFUART_MR1_PARITYEVEN 0x00 /* Even parity */ 92#define MCFUART_MR1_PARITYODD 0x04 /* Odd parity */ 93#define MCFUART_MR1_PARITYSPACE 0x08 /* Space parity */ 94#define MCFUART_MR1_PARITYMARK 0x0c /* Mark parity */ 95 96#define MCFUART_MR1_CS5 0x00 /* 5 bits per char */ 97#define MCFUART_MR1_CS6 0x01 /* 6 bits per char */ 98#define MCFUART_MR1_CS7 0x02 /* 7 bits per char */ 99#define MCFUART_MR1_CS8 0x03 /* 8 bits per char */ 100 101/* 102 * Define bit flags in Mode Register 2 (MR2). 103 */ 104#define MCFUART_MR2_LOOPBACK 0x80 /* Loopback mode */ 105#define MCFUART_MR2_REMOTELOOP 0xc0 /* Remote loopback mode */ 106#define MCFUART_MR2_AUTOECHO 0x40 /* Automatic echo */ 107#define MCFUART_MR2_TXRTS 0x20 /* Assert RTS on TX */ 108#define MCFUART_MR2_TXCTS 0x10 /* Auto CTS flow control */ 109 110#define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */ 111#define MCFUART_MR2_STOP15 0x08 /* 1.5 stop bits */ 112#define MCFUART_MR2_STOP2 0x0f /* 2 stop bits */ 113 114/* 115 * Define bit flags in Status Register (USR). 116 */ 117#define MCFUART_USR_RXBREAK 0x80 /* Received BREAK */ 118#define MCFUART_USR_RXFRAMING 0x40 /* Received framing error */ 119#define MCFUART_USR_RXPARITY 0x20 /* Received parity error */ 120#define MCFUART_USR_RXOVERRUN 0x10 /* Received overrun error */ 121#define MCFUART_USR_TXEMPTY 0x08 /* Transmitter empty */ 122#define MCFUART_USR_TXREADY 0x04 /* Transmitter ready */ 123#define MCFUART_USR_RXFULL 0x02 /* Receiver full */ 124#define MCFUART_USR_RXREADY 0x01 /* Receiver ready */ 125 126#define MCFUART_USR_RXERR (MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \ 127 MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN) 128 129/* 130 * Define bit flags in Clock Select Register (UCSR). 131 */ 132#define MCFUART_UCSR_RXCLKTIMER 0xd0 /* RX clock is timer */ 133#define MCFUART_UCSR_RXCLKEXT16 0xe0 /* RX clock is external x16 */ 134#define MCFUART_UCSR_RXCLKEXT1 0xf0 /* RX clock is external x1 */ 135 136#define MCFUART_UCSR_TXCLKTIMER 0x0d /* TX clock is timer */ 137#define MCFUART_UCSR_TXCLKEXT16 0x0e /* TX clock is external x16 */ 138#define MCFUART_UCSR_TXCLKEXT1 0x0f /* TX clock is external x1 */ 139 140/* 141 * Define bit flags in Command Register (UCR). 142 */ 143#define MCFUART_UCR_CMDNULL 0x00 /* No command */ 144#define MCFUART_UCR_CMDRESETMRPTR 0x10 /* Reset MR pointer */ 145#define MCFUART_UCR_CMDRESETRX 0x20 /* Reset receiver */ 146#define MCFUART_UCR_CMDRESETTX 0x30 /* Reset transmitter */ 147#define MCFUART_UCR_CMDRESETERR 0x40 /* Reset error status */ 148#define MCFUART_UCR_CMDRESETBREAK 0x50 /* Reset BREAK change */ 149#define MCFUART_UCR_CMDBREAKSTART 0x60 /* Start BREAK */ 150#define MCFUART_UCR_CMDBREAKSTOP 0x70 /* Stop BREAK */ 151 152#define MCFUART_UCR_TXNULL 0x00 /* No TX command */ 153#define MCFUART_UCR_TXENABLE 0x04 /* Enable TX */ 154#define MCFUART_UCR_TXDISABLE 0x08 /* Disable TX */ 155#define MCFUART_UCR_RXNULL 0x00 /* No RX command */ 156#define MCFUART_UCR_RXENABLE 0x01 /* Enable RX */ 157#define MCFUART_UCR_RXDISABLE 0x02 /* Disable RX */ 158 159/* 160 * Define bit flags in Input Port Change Register (UIPCR). 161 */ 162#define MCFUART_UIPCR_CTSCOS 0x10 /* CTS change of state */ 163#define MCFUART_UIPCR_CTS 0x01 /* CTS value */ 164 165/* 166 * Define bit flags in Input Port Register (UIP). 167 */ 168#define MCFUART_UIPR_CTS 0x01 /* CTS value */ 169 170/* 171 * Define bit flags in Output Port Registers (UOP). 172 * Clear bit by writing to UOP0, set by writing to UOP1. 173 */ 174#define MCFUART_UOP_RTS 0x01 /* RTS set or clear */ 175 176/* 177 * Define bit flags in the Auxiliary Control Register (UACR). 178 */ 179#define MCFUART_UACR_IEC 0x01 /* Input enable control */ 180 181/* 182 * Define bit flags in Interrupt Status Register (UISR). 183 * These same bits are used for the Interrupt Mask Register (UIMR). 184 */ 185#define MCFUART_UIR_COS 0x80 /* Change of state (CTS) */ 186#define MCFUART_UIR_DELTABREAK 0x04 /* Break start or stop */ 187#define MCFUART_UIR_RXREADY 0x02 /* Receiver ready */ 188#define MCFUART_UIR_TXREADY 0x01 /* Transmitter ready */ 189 190#ifdef CONFIG_M5272 191/* 192 * Define bit flags in the Transmitter FIFO Register (UTF). 193 */ 194#define MCFUART_UTF_TXB 0x1f /* Transmitter data level */ 195#define MCFUART_UTF_FULL 0x20 /* Transmitter fifo full */ 196#define MCFUART_UTF_TXS 0xc0 /* Transmitter status */ 197 198/* 199 * Define bit flags in the Receiver FIFO Register (URF). 200 */ 201#define MCFUART_URF_RXB 0x1f /* Receiver data level */ 202#define MCFUART_URF_FULL 0x20 /* Receiver fifo full */ 203#define MCFUART_URF_RXS 0xc0 /* Receiver status */ 204#endif 205 206/****************************************************************************/ 207#endif /* mcfuart_h */ 208