1#ifndef __iop_sap_out_defs_asm_h 2#define __iop_sap_out_defs_asm_h 3 4/* 5 * This file is autogenerated from 6 * file: ../../inst/io_proc/rtl/iop_sap_out.r 7 * id: <not found> 8 * last modfied: Mon Apr 11 16:08:46 2005 9 * 10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sap_out_defs_asm.h ../../inst/io_proc/rtl/iop_sap_out.r 11 * id: $Id: iop_sap_out_defs_asm.h,v 1.1.1.1 2007/08/03 18:53:23 Exp $ 12 * Any changes here will be lost. 13 * 14 * -*- buffer-read-only: t -*- 15 */ 16 17#ifndef REG_FIELD 18#define REG_FIELD( scope, reg, field, value ) \ 19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) 20#define REG_FIELD_X_( value, shift ) ((value) << shift) 21#endif 22 23#ifndef REG_STATE 24#define REG_STATE( scope, reg, field, symbolic_value ) \ 25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) 26#define REG_STATE_X_( k, shift ) (k << shift) 27#endif 28 29#ifndef REG_MASK 30#define REG_MASK( scope, reg, field ) \ 31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) 32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) 33#endif 34 35#ifndef REG_LSB 36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb 37#endif 38 39#ifndef REG_BIT 40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit 41#endif 42 43#ifndef REG_ADDR 44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) 45#define REG_ADDR_X_( inst, offs ) ((inst) + offs) 46#endif 47 48#ifndef REG_ADDR_VECT 49#define REG_ADDR_VECT( scope, inst, reg, index ) \ 50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ 51 STRIDE_##scope##_##reg ) 52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ 53 ((inst) + offs + (index) * stride) 54#endif 55 56/* Register rw_gen_gated, scope iop_sap_out, type rw */ 57#define reg_iop_sap_out_rw_gen_gated___clk0_src___lsb 0 58#define reg_iop_sap_out_rw_gen_gated___clk0_src___width 2 59#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___lsb 2 60#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___width 2 61#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___lsb 4 62#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___width 3 63#define reg_iop_sap_out_rw_gen_gated___clk1_src___lsb 7 64#define reg_iop_sap_out_rw_gen_gated___clk1_src___width 2 65#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___lsb 9 66#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___width 2 67#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___lsb 11 68#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___width 3 69#define reg_iop_sap_out_rw_gen_gated___clk2_src___lsb 14 70#define reg_iop_sap_out_rw_gen_gated___clk2_src___width 2 71#define reg_iop_sap_out_rw_gen_gated___clk2_gate_src___lsb 16 72#define reg_iop_sap_out_rw_gen_gated___clk2_gate_src___width 2 73#define reg_iop_sap_out_rw_gen_gated___clk2_force_src___lsb 18 74#define reg_iop_sap_out_rw_gen_gated___clk2_force_src___width 3 75#define reg_iop_sap_out_rw_gen_gated___clk3_src___lsb 21 76#define reg_iop_sap_out_rw_gen_gated___clk3_src___width 2 77#define reg_iop_sap_out_rw_gen_gated___clk3_gate_src___lsb 23 78#define reg_iop_sap_out_rw_gen_gated___clk3_gate_src___width 2 79#define reg_iop_sap_out_rw_gen_gated___clk3_force_src___lsb 25 80#define reg_iop_sap_out_rw_gen_gated___clk3_force_src___width 3 81#define reg_iop_sap_out_rw_gen_gated_offset 0 82 83/* Register rw_bus0, scope iop_sap_out, type rw */ 84#define reg_iop_sap_out_rw_bus0___byte0_clk_sel___lsb 0 85#define reg_iop_sap_out_rw_bus0___byte0_clk_sel___width 3 86#define reg_iop_sap_out_rw_bus0___byte0_gated_clk___lsb 3 87#define reg_iop_sap_out_rw_bus0___byte0_gated_clk___width 2 88#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___lsb 5 89#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___width 1 90#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___bit 5 91#define reg_iop_sap_out_rw_bus0___byte1_clk_sel___lsb 6 92#define reg_iop_sap_out_rw_bus0___byte1_clk_sel___width 3 93#define reg_iop_sap_out_rw_bus0___byte1_gated_clk___lsb 9 94#define reg_iop_sap_out_rw_bus0___byte1_gated_clk___width 2 95#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___lsb 11 96#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___width 1 97#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___bit 11 98#define reg_iop_sap_out_rw_bus0___byte2_clk_sel___lsb 12 99#define reg_iop_sap_out_rw_bus0___byte2_clk_sel___width 3 100#define reg_iop_sap_out_rw_bus0___byte2_gated_clk___lsb 15 101#define reg_iop_sap_out_rw_bus0___byte2_gated_clk___width 2 102#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___lsb 17 103#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___width 1 104#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___bit 17 105#define reg_iop_sap_out_rw_bus0___byte3_clk_sel___lsb 18 106#define reg_iop_sap_out_rw_bus0___byte3_clk_sel___width 3 107#define reg_iop_sap_out_rw_bus0___byte3_gated_clk___lsb 21 108#define reg_iop_sap_out_rw_bus0___byte3_gated_clk___width 2 109#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___lsb 23 110#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___width 1 111#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___bit 23 112#define reg_iop_sap_out_rw_bus0_offset 4 113 114/* Register rw_bus1, scope iop_sap_out, type rw */ 115#define reg_iop_sap_out_rw_bus1___byte0_clk_sel___lsb 0 116#define reg_iop_sap_out_rw_bus1___byte0_clk_sel___width 3 117#define reg_iop_sap_out_rw_bus1___byte0_gated_clk___lsb 3 118#define reg_iop_sap_out_rw_bus1___byte0_gated_clk___width 2 119#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___lsb 5 120#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___width 1 121#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___bit 5 122#define reg_iop_sap_out_rw_bus1___byte1_clk_sel___lsb 6 123#define reg_iop_sap_out_rw_bus1___byte1_clk_sel___width 3 124#define reg_iop_sap_out_rw_bus1___byte1_gated_clk___lsb 9 125#define reg_iop_sap_out_rw_bus1___byte1_gated_clk___width 2 126#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___lsb 11 127#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___width 1 128#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___bit 11 129#define reg_iop_sap_out_rw_bus1___byte2_clk_sel___lsb 12 130#define reg_iop_sap_out_rw_bus1___byte2_clk_sel___width 3 131#define reg_iop_sap_out_rw_bus1___byte2_gated_clk___lsb 15 132#define reg_iop_sap_out_rw_bus1___byte2_gated_clk___width 2 133#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___lsb 17 134#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___width 1 135#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___bit 17 136#define reg_iop_sap_out_rw_bus1___byte3_clk_sel___lsb 18 137#define reg_iop_sap_out_rw_bus1___byte3_clk_sel___width 3 138#define reg_iop_sap_out_rw_bus1___byte3_gated_clk___lsb 21 139#define reg_iop_sap_out_rw_bus1___byte3_gated_clk___width 2 140#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___lsb 23 141#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___width 1 142#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___bit 23 143#define reg_iop_sap_out_rw_bus1_offset 8 144 145/* Register rw_bus0_lo_oe, scope iop_sap_out, type rw */ 146#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_sel___lsb 0 147#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_sel___width 3 148#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_ext___lsb 3 149#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_ext___width 3 150#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_gated_clk___lsb 6 151#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_gated_clk___width 2 152#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___lsb 8 153#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___width 1 154#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___bit 8 155#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_logic___lsb 9 156#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_logic___width 2 157#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_sel___lsb 11 158#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_sel___width 3 159#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_ext___lsb 14 160#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_ext___width 3 161#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_gated_clk___lsb 17 162#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_gated_clk___width 2 163#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___lsb 19 164#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___width 1 165#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___bit 19 166#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_logic___lsb 20 167#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_logic___width 2 168#define reg_iop_sap_out_rw_bus0_lo_oe_offset 12 169 170/* Register rw_bus0_hi_oe, scope iop_sap_out, type rw */ 171#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_sel___lsb 0 172#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_sel___width 3 173#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_ext___lsb 3 174#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_ext___width 3 175#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_gated_clk___lsb 6 176#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_gated_clk___width 2 177#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___lsb 8 178#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___width 1 179#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___bit 8 180#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_logic___lsb 9 181#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_logic___width 2 182#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_sel___lsb 11 183#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_sel___width 3 184#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_ext___lsb 14 185#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_ext___width 3 186#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_gated_clk___lsb 17 187#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_gated_clk___width 2 188#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___lsb 19 189#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___width 1 190#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___bit 19 191#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_logic___lsb 20 192#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_logic___width 2 193#define reg_iop_sap_out_rw_bus0_hi_oe_offset 16 194 195/* Register rw_bus1_lo_oe, scope iop_sap_out, type rw */ 196#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_sel___lsb 0 197#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_sel___width 3 198#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_ext___lsb 3 199#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_ext___width 3 200#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_gated_clk___lsb 6 201#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_gated_clk___width 2 202#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___lsb 8 203#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___width 1 204#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___bit 8 205#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_logic___lsb 9 206#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_logic___width 2 207#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_sel___lsb 11 208#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_sel___width 3 209#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_ext___lsb 14 210#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_ext___width 3 211#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_gated_clk___lsb 17 212#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_gated_clk___width 2 213#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___lsb 19 214#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___width 1 215#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___bit 19 216#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_logic___lsb 20 217#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_logic___width 2 218#define reg_iop_sap_out_rw_bus1_lo_oe_offset 20 219 220/* Register rw_bus1_hi_oe, scope iop_sap_out, type rw */ 221#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_sel___lsb 0 222#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_sel___width 3 223#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_ext___lsb 3 224#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_ext___width 3 225#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_gated_clk___lsb 6 226#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_gated_clk___width 2 227#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___lsb 8 228#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___width 1 229#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___bit 8 230#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_logic___lsb 9 231#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_logic___width 2 232#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_sel___lsb 11 233#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_sel___width 3 234#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_ext___lsb 14 235#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_ext___width 3 236#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_gated_clk___lsb 17 237#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_gated_clk___width 2 238#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___lsb 19 239#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___width 1 240#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___bit 19 241#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_logic___lsb 20 242#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_logic___width 2 243#define reg_iop_sap_out_rw_bus1_hi_oe_offset 24 244 245#define STRIDE_iop_sap_out_rw_gio 4 246/* Register rw_gio, scope iop_sap_out, type rw */ 247#define reg_iop_sap_out_rw_gio___out_clk_sel___lsb 0 248#define reg_iop_sap_out_rw_gio___out_clk_sel___width 3 249#define reg_iop_sap_out_rw_gio___out_clk_ext___lsb 3 250#define reg_iop_sap_out_rw_gio___out_clk_ext___width 4 251#define reg_iop_sap_out_rw_gio___out_gated_clk___lsb 7 252#define reg_iop_sap_out_rw_gio___out_gated_clk___width 2 253#define reg_iop_sap_out_rw_gio___out_clk_inv___lsb 9 254#define reg_iop_sap_out_rw_gio___out_clk_inv___width 1 255#define reg_iop_sap_out_rw_gio___out_clk_inv___bit 9 256#define reg_iop_sap_out_rw_gio___out_logic___lsb 10 257#define reg_iop_sap_out_rw_gio___out_logic___width 1 258#define reg_iop_sap_out_rw_gio___out_logic___bit 10 259#define reg_iop_sap_out_rw_gio___oe_clk_sel___lsb 11 260#define reg_iop_sap_out_rw_gio___oe_clk_sel___width 3 261#define reg_iop_sap_out_rw_gio___oe_clk_ext___lsb 14 262#define reg_iop_sap_out_rw_gio___oe_clk_ext___width 3 263#define reg_iop_sap_out_rw_gio___oe_gated_clk___lsb 17 264#define reg_iop_sap_out_rw_gio___oe_gated_clk___width 2 265#define reg_iop_sap_out_rw_gio___oe_clk_inv___lsb 19 266#define reg_iop_sap_out_rw_gio___oe_clk_inv___width 1 267#define reg_iop_sap_out_rw_gio___oe_clk_inv___bit 19 268#define reg_iop_sap_out_rw_gio___oe_logic___lsb 20 269#define reg_iop_sap_out_rw_gio___oe_logic___width 2 270#define reg_iop_sap_out_rw_gio_offset 28 271 272 273/* Constants */ 274#define regk_iop_sap_out_and 0x00000002 275#define regk_iop_sap_out_clk0 0x00000000 276#define regk_iop_sap_out_clk1 0x00000001 277#define regk_iop_sap_out_clk12 0x00000002 278#define regk_iop_sap_out_clk2 0x00000002 279#define regk_iop_sap_out_clk200 0x00000001 280#define regk_iop_sap_out_clk3 0x00000003 281#define regk_iop_sap_out_ext 0x00000003 282#define regk_iop_sap_out_gated 0x00000004 283#define regk_iop_sap_out_gio1 0x00000000 284#define regk_iop_sap_out_gio13 0x00000002 285#define regk_iop_sap_out_gio13_clk 0x0000000c 286#define regk_iop_sap_out_gio15 0x00000001 287#define regk_iop_sap_out_gio18 0x00000003 288#define regk_iop_sap_out_gio18_clk 0x0000000d 289#define regk_iop_sap_out_gio1_clk 0x00000008 290#define regk_iop_sap_out_gio21_clk 0x0000000e 291#define regk_iop_sap_out_gio23 0x00000002 292#define regk_iop_sap_out_gio29_clk 0x0000000f 293#define regk_iop_sap_out_gio31 0x00000003 294#define regk_iop_sap_out_gio5 0x00000001 295#define regk_iop_sap_out_gio5_clk 0x00000009 296#define regk_iop_sap_out_gio6_clk 0x0000000a 297#define regk_iop_sap_out_gio7 0x00000000 298#define regk_iop_sap_out_gio7_clk 0x0000000b 299#define regk_iop_sap_out_gio_in13 0x00000001 300#define regk_iop_sap_out_gio_in21 0x00000002 301#define regk_iop_sap_out_gio_in29 0x00000003 302#define regk_iop_sap_out_gio_in5 0x00000000 303#define regk_iop_sap_out_inv 0x00000001 304#define regk_iop_sap_out_nand 0x00000003 305#define regk_iop_sap_out_no 0x00000000 306#define regk_iop_sap_out_none 0x00000000 307#define regk_iop_sap_out_rw_bus0_default 0x00000000 308#define regk_iop_sap_out_rw_bus0_hi_oe_default 0x00000000 309#define regk_iop_sap_out_rw_bus0_lo_oe_default 0x00000000 310#define regk_iop_sap_out_rw_bus1_default 0x00000000 311#define regk_iop_sap_out_rw_bus1_hi_oe_default 0x00000000 312#define regk_iop_sap_out_rw_bus1_lo_oe_default 0x00000000 313#define regk_iop_sap_out_rw_gen_gated_default 0x00000000 314#define regk_iop_sap_out_rw_gio_default 0x00000000 315#define regk_iop_sap_out_rw_gio_size 0x00000020 316#define regk_iop_sap_out_spu0_gio0 0x00000002 317#define regk_iop_sap_out_spu0_gio1 0x00000003 318#define regk_iop_sap_out_spu0_gio12 0x00000004 319#define regk_iop_sap_out_spu0_gio13 0x00000004 320#define regk_iop_sap_out_spu0_gio14 0x00000004 321#define regk_iop_sap_out_spu0_gio15 0x00000004 322#define regk_iop_sap_out_spu0_gio2 0x00000002 323#define regk_iop_sap_out_spu0_gio3 0x00000003 324#define regk_iop_sap_out_spu0_gio4 0x00000002 325#define regk_iop_sap_out_spu0_gio5 0x00000003 326#define regk_iop_sap_out_spu0_gio6 0x00000002 327#define regk_iop_sap_out_spu0_gio7 0x00000003 328#define regk_iop_sap_out_spu1_gio0 0x00000005 329#define regk_iop_sap_out_spu1_gio1 0x00000006 330#define regk_iop_sap_out_spu1_gio12 0x00000007 331#define regk_iop_sap_out_spu1_gio13 0x00000007 332#define regk_iop_sap_out_spu1_gio14 0x00000007 333#define regk_iop_sap_out_spu1_gio15 0x00000007 334#define regk_iop_sap_out_spu1_gio2 0x00000005 335#define regk_iop_sap_out_spu1_gio3 0x00000006 336#define regk_iop_sap_out_spu1_gio4 0x00000005 337#define regk_iop_sap_out_spu1_gio5 0x00000006 338#define regk_iop_sap_out_spu1_gio6 0x00000005 339#define regk_iop_sap_out_spu1_gio7 0x00000006 340#define regk_iop_sap_out_timer_grp0_tmr2 0x00000004 341#define regk_iop_sap_out_timer_grp1_tmr2 0x00000005 342#define regk_iop_sap_out_timer_grp2_tmr2 0x00000006 343#define regk_iop_sap_out_timer_grp3_tmr2 0x00000007 344#define regk_iop_sap_out_tmr 0x00000005 345#define regk_iop_sap_out_yes 0x00000001 346#endif /* __iop_sap_out_defs_asm_h */ 347