1#ifndef __sser_defs_asm_h 2#define __sser_defs_asm_h 3 4/* 5 * This file is autogenerated from 6 * file: ../../inst/syncser/rtl/sser_regs.r 7 * id: sser_regs.r,v 1.24 2005/02/11 14:27:36 gunnard Exp 8 * last modfied: Mon Apr 11 16:09:48 2005 9 * 10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/sser_defs_asm.h ../../inst/syncser/rtl/sser_regs.r 11 * id: $Id: sser_defs_asm.h,v 1.1.1.1 2007/08/03 18:53:23 Exp $ 12 * Any changes here will be lost. 13 * 14 * -*- buffer-read-only: t -*- 15 */ 16 17#ifndef REG_FIELD 18#define REG_FIELD( scope, reg, field, value ) \ 19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) 20#define REG_FIELD_X_( value, shift ) ((value) << shift) 21#endif 22 23#ifndef REG_STATE 24#define REG_STATE( scope, reg, field, symbolic_value ) \ 25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) 26#define REG_STATE_X_( k, shift ) (k << shift) 27#endif 28 29#ifndef REG_MASK 30#define REG_MASK( scope, reg, field ) \ 31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) 32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) 33#endif 34 35#ifndef REG_LSB 36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb 37#endif 38 39#ifndef REG_BIT 40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit 41#endif 42 43#ifndef REG_ADDR 44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) 45#define REG_ADDR_X_( inst, offs ) ((inst) + offs) 46#endif 47 48#ifndef REG_ADDR_VECT 49#define REG_ADDR_VECT( scope, inst, reg, index ) \ 50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ 51 STRIDE_##scope##_##reg ) 52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ 53 ((inst) + offs + (index) * stride) 54#endif 55 56/* Register rw_cfg, scope sser, type rw */ 57#define reg_sser_rw_cfg___clk_div___lsb 0 58#define reg_sser_rw_cfg___clk_div___width 16 59#define reg_sser_rw_cfg___base_freq___lsb 16 60#define reg_sser_rw_cfg___base_freq___width 3 61#define reg_sser_rw_cfg___gate_clk___lsb 19 62#define reg_sser_rw_cfg___gate_clk___width 1 63#define reg_sser_rw_cfg___gate_clk___bit 19 64#define reg_sser_rw_cfg___clkgate_ctrl___lsb 20 65#define reg_sser_rw_cfg___clkgate_ctrl___width 1 66#define reg_sser_rw_cfg___clkgate_ctrl___bit 20 67#define reg_sser_rw_cfg___clkgate_in___lsb 21 68#define reg_sser_rw_cfg___clkgate_in___width 1 69#define reg_sser_rw_cfg___clkgate_in___bit 21 70#define reg_sser_rw_cfg___clk_dir___lsb 22 71#define reg_sser_rw_cfg___clk_dir___width 1 72#define reg_sser_rw_cfg___clk_dir___bit 22 73#define reg_sser_rw_cfg___clk_od_mode___lsb 23 74#define reg_sser_rw_cfg___clk_od_mode___width 1 75#define reg_sser_rw_cfg___clk_od_mode___bit 23 76#define reg_sser_rw_cfg___out_clk_pol___lsb 24 77#define reg_sser_rw_cfg___out_clk_pol___width 1 78#define reg_sser_rw_cfg___out_clk_pol___bit 24 79#define reg_sser_rw_cfg___out_clk_src___lsb 25 80#define reg_sser_rw_cfg___out_clk_src___width 2 81#define reg_sser_rw_cfg___clk_in_sel___lsb 27 82#define reg_sser_rw_cfg___clk_in_sel___width 1 83#define reg_sser_rw_cfg___clk_in_sel___bit 27 84#define reg_sser_rw_cfg___hold_pol___lsb 28 85#define reg_sser_rw_cfg___hold_pol___width 1 86#define reg_sser_rw_cfg___hold_pol___bit 28 87#define reg_sser_rw_cfg___prepare___lsb 29 88#define reg_sser_rw_cfg___prepare___width 1 89#define reg_sser_rw_cfg___prepare___bit 29 90#define reg_sser_rw_cfg___en___lsb 30 91#define reg_sser_rw_cfg___en___width 1 92#define reg_sser_rw_cfg___en___bit 30 93#define reg_sser_rw_cfg_offset 0 94 95/* Register rw_frm_cfg, scope sser, type rw */ 96#define reg_sser_rw_frm_cfg___wordrate___lsb 0 97#define reg_sser_rw_frm_cfg___wordrate___width 10 98#define reg_sser_rw_frm_cfg___rec_delay___lsb 10 99#define reg_sser_rw_frm_cfg___rec_delay___width 3 100#define reg_sser_rw_frm_cfg___tr_delay___lsb 13 101#define reg_sser_rw_frm_cfg___tr_delay___width 3 102#define reg_sser_rw_frm_cfg___early_wend___lsb 16 103#define reg_sser_rw_frm_cfg___early_wend___width 1 104#define reg_sser_rw_frm_cfg___early_wend___bit 16 105#define reg_sser_rw_frm_cfg___level___lsb 17 106#define reg_sser_rw_frm_cfg___level___width 2 107#define reg_sser_rw_frm_cfg___type___lsb 19 108#define reg_sser_rw_frm_cfg___type___width 1 109#define reg_sser_rw_frm_cfg___type___bit 19 110#define reg_sser_rw_frm_cfg___clk_pol___lsb 20 111#define reg_sser_rw_frm_cfg___clk_pol___width 1 112#define reg_sser_rw_frm_cfg___clk_pol___bit 20 113#define reg_sser_rw_frm_cfg___fr_in_rxclk___lsb 21 114#define reg_sser_rw_frm_cfg___fr_in_rxclk___width 1 115#define reg_sser_rw_frm_cfg___fr_in_rxclk___bit 21 116#define reg_sser_rw_frm_cfg___clk_src___lsb 22 117#define reg_sser_rw_frm_cfg___clk_src___width 1 118#define reg_sser_rw_frm_cfg___clk_src___bit 22 119#define reg_sser_rw_frm_cfg___out_off___lsb 23 120#define reg_sser_rw_frm_cfg___out_off___width 1 121#define reg_sser_rw_frm_cfg___out_off___bit 23 122#define reg_sser_rw_frm_cfg___out_on___lsb 24 123#define reg_sser_rw_frm_cfg___out_on___width 1 124#define reg_sser_rw_frm_cfg___out_on___bit 24 125#define reg_sser_rw_frm_cfg___frame_pin_dir___lsb 25 126#define reg_sser_rw_frm_cfg___frame_pin_dir___width 1 127#define reg_sser_rw_frm_cfg___frame_pin_dir___bit 25 128#define reg_sser_rw_frm_cfg___frame_pin_use___lsb 26 129#define reg_sser_rw_frm_cfg___frame_pin_use___width 2 130#define reg_sser_rw_frm_cfg___status_pin_dir___lsb 28 131#define reg_sser_rw_frm_cfg___status_pin_dir___width 1 132#define reg_sser_rw_frm_cfg___status_pin_dir___bit 28 133#define reg_sser_rw_frm_cfg___status_pin_use___lsb 29 134#define reg_sser_rw_frm_cfg___status_pin_use___width 2 135#define reg_sser_rw_frm_cfg_offset 4 136 137/* Register rw_tr_cfg, scope sser, type rw */ 138#define reg_sser_rw_tr_cfg___tr_en___lsb 0 139#define reg_sser_rw_tr_cfg___tr_en___width 1 140#define reg_sser_rw_tr_cfg___tr_en___bit 0 141#define reg_sser_rw_tr_cfg___stop___lsb 1 142#define reg_sser_rw_tr_cfg___stop___width 1 143#define reg_sser_rw_tr_cfg___stop___bit 1 144#define reg_sser_rw_tr_cfg___urun_stop___lsb 2 145#define reg_sser_rw_tr_cfg___urun_stop___width 1 146#define reg_sser_rw_tr_cfg___urun_stop___bit 2 147#define reg_sser_rw_tr_cfg___eop_stop___lsb 3 148#define reg_sser_rw_tr_cfg___eop_stop___width 1 149#define reg_sser_rw_tr_cfg___eop_stop___bit 3 150#define reg_sser_rw_tr_cfg___sample_size___lsb 4 151#define reg_sser_rw_tr_cfg___sample_size___width 6 152#define reg_sser_rw_tr_cfg___sh_dir___lsb 10 153#define reg_sser_rw_tr_cfg___sh_dir___width 1 154#define reg_sser_rw_tr_cfg___sh_dir___bit 10 155#define reg_sser_rw_tr_cfg___clk_pol___lsb 11 156#define reg_sser_rw_tr_cfg___clk_pol___width 1 157#define reg_sser_rw_tr_cfg___clk_pol___bit 11 158#define reg_sser_rw_tr_cfg___clk_src___lsb 12 159#define reg_sser_rw_tr_cfg___clk_src___width 1 160#define reg_sser_rw_tr_cfg___clk_src___bit 12 161#define reg_sser_rw_tr_cfg___use_dma___lsb 13 162#define reg_sser_rw_tr_cfg___use_dma___width 1 163#define reg_sser_rw_tr_cfg___use_dma___bit 13 164#define reg_sser_rw_tr_cfg___mode___lsb 14 165#define reg_sser_rw_tr_cfg___mode___width 2 166#define reg_sser_rw_tr_cfg___frm_src___lsb 16 167#define reg_sser_rw_tr_cfg___frm_src___width 1 168#define reg_sser_rw_tr_cfg___frm_src___bit 16 169#define reg_sser_rw_tr_cfg___use60958___lsb 17 170#define reg_sser_rw_tr_cfg___use60958___width 1 171#define reg_sser_rw_tr_cfg___use60958___bit 17 172#define reg_sser_rw_tr_cfg___iec60958_ckdiv___lsb 18 173#define reg_sser_rw_tr_cfg___iec60958_ckdiv___width 2 174#define reg_sser_rw_tr_cfg___rate_ctrl___lsb 20 175#define reg_sser_rw_tr_cfg___rate_ctrl___width 1 176#define reg_sser_rw_tr_cfg___rate_ctrl___bit 20 177#define reg_sser_rw_tr_cfg___use_md___lsb 21 178#define reg_sser_rw_tr_cfg___use_md___width 1 179#define reg_sser_rw_tr_cfg___use_md___bit 21 180#define reg_sser_rw_tr_cfg___dual_i2s___lsb 22 181#define reg_sser_rw_tr_cfg___dual_i2s___width 1 182#define reg_sser_rw_tr_cfg___dual_i2s___bit 22 183#define reg_sser_rw_tr_cfg___data_pin_use___lsb 23 184#define reg_sser_rw_tr_cfg___data_pin_use___width 2 185#define reg_sser_rw_tr_cfg___od_mode___lsb 25 186#define reg_sser_rw_tr_cfg___od_mode___width 1 187#define reg_sser_rw_tr_cfg___od_mode___bit 25 188#define reg_sser_rw_tr_cfg___bulk_wspace___lsb 26 189#define reg_sser_rw_tr_cfg___bulk_wspace___width 2 190#define reg_sser_rw_tr_cfg_offset 8 191 192/* Register rw_rec_cfg, scope sser, type rw */ 193#define reg_sser_rw_rec_cfg___rec_en___lsb 0 194#define reg_sser_rw_rec_cfg___rec_en___width 1 195#define reg_sser_rw_rec_cfg___rec_en___bit 0 196#define reg_sser_rw_rec_cfg___force_eop___lsb 1 197#define reg_sser_rw_rec_cfg___force_eop___width 1 198#define reg_sser_rw_rec_cfg___force_eop___bit 1 199#define reg_sser_rw_rec_cfg___stop___lsb 2 200#define reg_sser_rw_rec_cfg___stop___width 1 201#define reg_sser_rw_rec_cfg___stop___bit 2 202#define reg_sser_rw_rec_cfg___orun_stop___lsb 3 203#define reg_sser_rw_rec_cfg___orun_stop___width 1 204#define reg_sser_rw_rec_cfg___orun_stop___bit 3 205#define reg_sser_rw_rec_cfg___eop_stop___lsb 4 206#define reg_sser_rw_rec_cfg___eop_stop___width 1 207#define reg_sser_rw_rec_cfg___eop_stop___bit 4 208#define reg_sser_rw_rec_cfg___sample_size___lsb 5 209#define reg_sser_rw_rec_cfg___sample_size___width 6 210#define reg_sser_rw_rec_cfg___sh_dir___lsb 11 211#define reg_sser_rw_rec_cfg___sh_dir___width 1 212#define reg_sser_rw_rec_cfg___sh_dir___bit 11 213#define reg_sser_rw_rec_cfg___clk_pol___lsb 12 214#define reg_sser_rw_rec_cfg___clk_pol___width 1 215#define reg_sser_rw_rec_cfg___clk_pol___bit 12 216#define reg_sser_rw_rec_cfg___clk_src___lsb 13 217#define reg_sser_rw_rec_cfg___clk_src___width 1 218#define reg_sser_rw_rec_cfg___clk_src___bit 13 219#define reg_sser_rw_rec_cfg___use_dma___lsb 14 220#define reg_sser_rw_rec_cfg___use_dma___width 1 221#define reg_sser_rw_rec_cfg___use_dma___bit 14 222#define reg_sser_rw_rec_cfg___mode___lsb 15 223#define reg_sser_rw_rec_cfg___mode___width 2 224#define reg_sser_rw_rec_cfg___frm_src___lsb 17 225#define reg_sser_rw_rec_cfg___frm_src___width 2 226#define reg_sser_rw_rec_cfg___use60958___lsb 19 227#define reg_sser_rw_rec_cfg___use60958___width 1 228#define reg_sser_rw_rec_cfg___use60958___bit 19 229#define reg_sser_rw_rec_cfg___iec60958_ui_len___lsb 20 230#define reg_sser_rw_rec_cfg___iec60958_ui_len___width 5 231#define reg_sser_rw_rec_cfg___slave2_en___lsb 25 232#define reg_sser_rw_rec_cfg___slave2_en___width 1 233#define reg_sser_rw_rec_cfg___slave2_en___bit 25 234#define reg_sser_rw_rec_cfg___slave3_en___lsb 26 235#define reg_sser_rw_rec_cfg___slave3_en___width 1 236#define reg_sser_rw_rec_cfg___slave3_en___bit 26 237#define reg_sser_rw_rec_cfg___fifo_thr___lsb 27 238#define reg_sser_rw_rec_cfg___fifo_thr___width 2 239#define reg_sser_rw_rec_cfg_offset 12 240 241/* Register rw_tr_data, scope sser, type rw */ 242#define reg_sser_rw_tr_data___data___lsb 0 243#define reg_sser_rw_tr_data___data___width 16 244#define reg_sser_rw_tr_data___md___lsb 16 245#define reg_sser_rw_tr_data___md___width 1 246#define reg_sser_rw_tr_data___md___bit 16 247#define reg_sser_rw_tr_data_offset 16 248 249/* Register r_rec_data, scope sser, type r */ 250#define reg_sser_r_rec_data___data___lsb 0 251#define reg_sser_r_rec_data___data___width 16 252#define reg_sser_r_rec_data___md___lsb 16 253#define reg_sser_r_rec_data___md___width 1 254#define reg_sser_r_rec_data___md___bit 16 255#define reg_sser_r_rec_data___ext_clk___lsb 17 256#define reg_sser_r_rec_data___ext_clk___width 1 257#define reg_sser_r_rec_data___ext_clk___bit 17 258#define reg_sser_r_rec_data___status_in___lsb 18 259#define reg_sser_r_rec_data___status_in___width 1 260#define reg_sser_r_rec_data___status_in___bit 18 261#define reg_sser_r_rec_data___frame_in___lsb 19 262#define reg_sser_r_rec_data___frame_in___width 1 263#define reg_sser_r_rec_data___frame_in___bit 19 264#define reg_sser_r_rec_data___din___lsb 20 265#define reg_sser_r_rec_data___din___width 1 266#define reg_sser_r_rec_data___din___bit 20 267#define reg_sser_r_rec_data___data_in___lsb 21 268#define reg_sser_r_rec_data___data_in___width 1 269#define reg_sser_r_rec_data___data_in___bit 21 270#define reg_sser_r_rec_data___clk_in___lsb 22 271#define reg_sser_r_rec_data___clk_in___width 1 272#define reg_sser_r_rec_data___clk_in___bit 22 273#define reg_sser_r_rec_data_offset 20 274 275/* Register rw_extra, scope sser, type rw */ 276#define reg_sser_rw_extra___clkoff_cycles___lsb 0 277#define reg_sser_rw_extra___clkoff_cycles___width 20 278#define reg_sser_rw_extra___clkoff_en___lsb 20 279#define reg_sser_rw_extra___clkoff_en___width 1 280#define reg_sser_rw_extra___clkoff_en___bit 20 281#define reg_sser_rw_extra___clkon_en___lsb 21 282#define reg_sser_rw_extra___clkon_en___width 1 283#define reg_sser_rw_extra___clkon_en___bit 21 284#define reg_sser_rw_extra___dout_delay___lsb 22 285#define reg_sser_rw_extra___dout_delay___width 5 286#define reg_sser_rw_extra_offset 24 287 288/* Register rw_intr_mask, scope sser, type rw */ 289#define reg_sser_rw_intr_mask___trdy___lsb 0 290#define reg_sser_rw_intr_mask___trdy___width 1 291#define reg_sser_rw_intr_mask___trdy___bit 0 292#define reg_sser_rw_intr_mask___rdav___lsb 1 293#define reg_sser_rw_intr_mask___rdav___width 1 294#define reg_sser_rw_intr_mask___rdav___bit 1 295#define reg_sser_rw_intr_mask___tidle___lsb 2 296#define reg_sser_rw_intr_mask___tidle___width 1 297#define reg_sser_rw_intr_mask___tidle___bit 2 298#define reg_sser_rw_intr_mask___rstop___lsb 3 299#define reg_sser_rw_intr_mask___rstop___width 1 300#define reg_sser_rw_intr_mask___rstop___bit 3 301#define reg_sser_rw_intr_mask___urun___lsb 4 302#define reg_sser_rw_intr_mask___urun___width 1 303#define reg_sser_rw_intr_mask___urun___bit 4 304#define reg_sser_rw_intr_mask___orun___lsb 5 305#define reg_sser_rw_intr_mask___orun___width 1 306#define reg_sser_rw_intr_mask___orun___bit 5 307#define reg_sser_rw_intr_mask___md_rec___lsb 6 308#define reg_sser_rw_intr_mask___md_rec___width 1 309#define reg_sser_rw_intr_mask___md_rec___bit 6 310#define reg_sser_rw_intr_mask___md_sent___lsb 7 311#define reg_sser_rw_intr_mask___md_sent___width 1 312#define reg_sser_rw_intr_mask___md_sent___bit 7 313#define reg_sser_rw_intr_mask___r958err___lsb 8 314#define reg_sser_rw_intr_mask___r958err___width 1 315#define reg_sser_rw_intr_mask___r958err___bit 8 316#define reg_sser_rw_intr_mask_offset 28 317 318/* Register rw_ack_intr, scope sser, type rw */ 319#define reg_sser_rw_ack_intr___trdy___lsb 0 320#define reg_sser_rw_ack_intr___trdy___width 1 321#define reg_sser_rw_ack_intr___trdy___bit 0 322#define reg_sser_rw_ack_intr___rdav___lsb 1 323#define reg_sser_rw_ack_intr___rdav___width 1 324#define reg_sser_rw_ack_intr___rdav___bit 1 325#define reg_sser_rw_ack_intr___tidle___lsb 2 326#define reg_sser_rw_ack_intr___tidle___width 1 327#define reg_sser_rw_ack_intr___tidle___bit 2 328#define reg_sser_rw_ack_intr___rstop___lsb 3 329#define reg_sser_rw_ack_intr___rstop___width 1 330#define reg_sser_rw_ack_intr___rstop___bit 3 331#define reg_sser_rw_ack_intr___urun___lsb 4 332#define reg_sser_rw_ack_intr___urun___width 1 333#define reg_sser_rw_ack_intr___urun___bit 4 334#define reg_sser_rw_ack_intr___orun___lsb 5 335#define reg_sser_rw_ack_intr___orun___width 1 336#define reg_sser_rw_ack_intr___orun___bit 5 337#define reg_sser_rw_ack_intr___md_rec___lsb 6 338#define reg_sser_rw_ack_intr___md_rec___width 1 339#define reg_sser_rw_ack_intr___md_rec___bit 6 340#define reg_sser_rw_ack_intr___md_sent___lsb 7 341#define reg_sser_rw_ack_intr___md_sent___width 1 342#define reg_sser_rw_ack_intr___md_sent___bit 7 343#define reg_sser_rw_ack_intr___r958err___lsb 8 344#define reg_sser_rw_ack_intr___r958err___width 1 345#define reg_sser_rw_ack_intr___r958err___bit 8 346#define reg_sser_rw_ack_intr_offset 32 347 348/* Register r_intr, scope sser, type r */ 349#define reg_sser_r_intr___trdy___lsb 0 350#define reg_sser_r_intr___trdy___width 1 351#define reg_sser_r_intr___trdy___bit 0 352#define reg_sser_r_intr___rdav___lsb 1 353#define reg_sser_r_intr___rdav___width 1 354#define reg_sser_r_intr___rdav___bit 1 355#define reg_sser_r_intr___tidle___lsb 2 356#define reg_sser_r_intr___tidle___width 1 357#define reg_sser_r_intr___tidle___bit 2 358#define reg_sser_r_intr___rstop___lsb 3 359#define reg_sser_r_intr___rstop___width 1 360#define reg_sser_r_intr___rstop___bit 3 361#define reg_sser_r_intr___urun___lsb 4 362#define reg_sser_r_intr___urun___width 1 363#define reg_sser_r_intr___urun___bit 4 364#define reg_sser_r_intr___orun___lsb 5 365#define reg_sser_r_intr___orun___width 1 366#define reg_sser_r_intr___orun___bit 5 367#define reg_sser_r_intr___md_rec___lsb 6 368#define reg_sser_r_intr___md_rec___width 1 369#define reg_sser_r_intr___md_rec___bit 6 370#define reg_sser_r_intr___md_sent___lsb 7 371#define reg_sser_r_intr___md_sent___width 1 372#define reg_sser_r_intr___md_sent___bit 7 373#define reg_sser_r_intr___r958err___lsb 8 374#define reg_sser_r_intr___r958err___width 1 375#define reg_sser_r_intr___r958err___bit 8 376#define reg_sser_r_intr_offset 36 377 378/* Register r_masked_intr, scope sser, type r */ 379#define reg_sser_r_masked_intr___trdy___lsb 0 380#define reg_sser_r_masked_intr___trdy___width 1 381#define reg_sser_r_masked_intr___trdy___bit 0 382#define reg_sser_r_masked_intr___rdav___lsb 1 383#define reg_sser_r_masked_intr___rdav___width 1 384#define reg_sser_r_masked_intr___rdav___bit 1 385#define reg_sser_r_masked_intr___tidle___lsb 2 386#define reg_sser_r_masked_intr___tidle___width 1 387#define reg_sser_r_masked_intr___tidle___bit 2 388#define reg_sser_r_masked_intr___rstop___lsb 3 389#define reg_sser_r_masked_intr___rstop___width 1 390#define reg_sser_r_masked_intr___rstop___bit 3 391#define reg_sser_r_masked_intr___urun___lsb 4 392#define reg_sser_r_masked_intr___urun___width 1 393#define reg_sser_r_masked_intr___urun___bit 4 394#define reg_sser_r_masked_intr___orun___lsb 5 395#define reg_sser_r_masked_intr___orun___width 1 396#define reg_sser_r_masked_intr___orun___bit 5 397#define reg_sser_r_masked_intr___md_rec___lsb 6 398#define reg_sser_r_masked_intr___md_rec___width 1 399#define reg_sser_r_masked_intr___md_rec___bit 6 400#define reg_sser_r_masked_intr___md_sent___lsb 7 401#define reg_sser_r_masked_intr___md_sent___width 1 402#define reg_sser_r_masked_intr___md_sent___bit 7 403#define reg_sser_r_masked_intr___r958err___lsb 8 404#define reg_sser_r_masked_intr___r958err___width 1 405#define reg_sser_r_masked_intr___r958err___bit 8 406#define reg_sser_r_masked_intr_offset 40 407 408 409/* Constants */ 410#define regk_sser_both 0x00000002 411#define regk_sser_bulk 0x00000001 412#define regk_sser_clk100 0x00000000 413#define regk_sser_clk_in 0x00000000 414#define regk_sser_const0 0x00000003 415#define regk_sser_dout 0x00000002 416#define regk_sser_edge 0x00000000 417#define regk_sser_ext 0x00000001 418#define regk_sser_ext_clk 0x00000001 419#define regk_sser_f100 0x00000000 420#define regk_sser_f29_493 0x00000004 421#define regk_sser_f32 0x00000005 422#define regk_sser_f32_768 0x00000006 423#define regk_sser_frm 0x00000003 424#define regk_sser_gio0 0x00000000 425#define regk_sser_gio1 0x00000001 426#define regk_sser_hispeed 0x00000001 427#define regk_sser_hold 0x00000002 428#define regk_sser_in 0x00000000 429#define regk_sser_inf 0x00000003 430#define regk_sser_intern 0x00000000 431#define regk_sser_intern_clk 0x00000001 432#define regk_sser_intern_tb 0x00000000 433#define regk_sser_iso 0x00000000 434#define regk_sser_level 0x00000001 435#define regk_sser_lospeed 0x00000000 436#define regk_sser_lsbfirst 0x00000000 437#define regk_sser_msbfirst 0x00000001 438#define regk_sser_neg 0x00000001 439#define regk_sser_neg_lo 0x00000000 440#define regk_sser_no 0x00000000 441#define regk_sser_no_clk 0x00000007 442#define regk_sser_nojitter 0x00000002 443#define regk_sser_out 0x00000001 444#define regk_sser_pos 0x00000000 445#define regk_sser_pos_hi 0x00000001 446#define regk_sser_rec 0x00000000 447#define regk_sser_rw_cfg_default 0x00000000 448#define regk_sser_rw_extra_default 0x00000000 449#define regk_sser_rw_frm_cfg_default 0x00000000 450#define regk_sser_rw_intr_mask_default 0x00000000 451#define regk_sser_rw_rec_cfg_default 0x00000000 452#define regk_sser_rw_tr_cfg_default 0x01800000 453#define regk_sser_rw_tr_data_default 0x00000000 454#define regk_sser_thr16 0x00000001 455#define regk_sser_thr32 0x00000002 456#define regk_sser_thr8 0x00000000 457#define regk_sser_tr 0x00000001 458#define regk_sser_ts_out 0x00000003 459#define regk_sser_tx_bulk 0x00000002 460#define regk_sser_wiresave 0x00000002 461#define regk_sser_yes 0x00000001 462#endif /* __sser_defs_asm_h */ 463