1#include <linux/serial.h> 2#include <asm/dma.h> 3 4#define NR_PORTS 1 5 6#define OFFSET_THR 0x00 /* Transmit Holding register */ 7#define OFFSET_RBR 0x00 /* Receive Buffer register */ 8#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ 9#define OFFSET_IER 0x04 /* Interrupt Enable Register */ 10#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ 11#define OFFSET_IIR 0x08 /* Interrupt Identification Register */ 12#define OFFSET_LCR 0x0C /* Line Control Register */ 13#define OFFSET_MCR 0x10 /* Modem Control Register */ 14#define OFFSET_LSR 0x14 /* Line Status Register */ 15#define OFFSET_MSR 0x18 /* Modem Status Register */ 16#define OFFSET_SCR 0x1C /* SCR Scratch Register */ 17#define OFFSET_GCTL 0x24 /* Global Control Register */ 18 19#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) 20#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) 21#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER)) 22#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) 23#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR)) 24#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) 25#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR)) 26#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) 27 28#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) 29#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) 30#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v) 31#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v) 32#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) 33#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) 34 35#ifdef CONFIG_BFIN_UART0_CTSRTS 36# define CONFIG_SERIAL_BFIN_CTSRTS 37# ifndef CONFIG_UART0_CTS_PIN 38# define CONFIG_UART0_CTS_PIN -1 39# endif 40# ifndef CONFIG_UART0_RTS_PIN 41# define CONFIG_UART0_RTS_PIN -1 42# endif 43#endif 44 45struct bfin_serial_port { 46 struct uart_port port; 47 unsigned int old_status; 48#ifdef CONFIG_SERIAL_BFIN_DMA 49 int tx_done; 50 int tx_count; 51 struct circ_buf rx_dma_buf; 52 struct timer_list rx_dma_timer; 53 int rx_dma_nrows; 54 unsigned int tx_dma_channel; 55 unsigned int rx_dma_channel; 56 struct work_struct tx_dma_workqueue; 57#else 58 struct work_struct cts_workqueue; 59#endif 60#ifdef CONFIG_SERIAL_BFIN_CTSRTS 61 int cts_pin; 62 int rts_pin; 63#endif 64}; 65 66struct bfin_serial_port bfin_serial_ports[NR_PORTS]; 67struct bfin_serial_res { 68 unsigned long uart_base_addr; 69 int uart_irq; 70#ifdef CONFIG_SERIAL_BFIN_DMA 71 unsigned int uart_tx_dma_channel; 72 unsigned int uart_rx_dma_channel; 73#endif 74#ifdef CONFIG_SERIAL_BFIN_CTSRTS 75 int uart_cts_pin; 76 int uart_rts_pin; 77#endif 78}; 79 80struct bfin_serial_res bfin_serial_resource[] = { 81 { 82 0xFFC00400, 83 IRQ_UART_RX, 84#ifdef CONFIG_SERIAL_BFIN_DMA 85 CH_UART_TX, 86 CH_UART_RX, 87#endif 88#ifdef CONFIG_BFIN_UART0_CTSRTS 89 CONFIG_UART0_CTS_PIN, 90 CONFIG_UART0_RTS_PIN, 91#endif 92 } 93}; 94 95 96int nr_ports = NR_PORTS; 97static void bfin_serial_hw_init(struct bfin_serial_port *uart) 98{ 99 100#ifdef CONFIG_SERIAL_BFIN_CTSRTS 101 if (uart->cts_pin >= 0) { 102 gpio_request(uart->cts_pin, NULL); 103 gpio_direction_input(uart->cts_pin); 104 } 105 if (uart->rts_pin >= 0) { 106 gpio_request(uart->rts_pin, NULL); 107 gpio_direction_input(uart->rts_pin); 108 } 109#endif 110} 111