1#include <linux/serial.h> 2#include <asm/dma.h> 3 4#define NR_PORTS 2 5 6#define OFFSET_THR 0x00 /* Transmit Holding register */ 7#define OFFSET_RBR 0x00 /* Receive Buffer register */ 8#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ 9#define OFFSET_IER 0x04 /* Interrupt Enable Register */ 10#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ 11#define OFFSET_IIR 0x08 /* Interrupt Identification Register */ 12#define OFFSET_LCR 0x0C /* Line Control Register */ 13#define OFFSET_MCR 0x10 /* Modem Control Register */ 14#define OFFSET_LSR 0x14 /* Line Status Register */ 15#define OFFSET_MSR 0x18 /* Modem Status Register */ 16#define OFFSET_SCR 0x1C /* SCR Scratch Register */ 17#define OFFSET_GCTL 0x24 /* Global Control Register */ 18 19#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) 20#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) 21#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER)) 22#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) 23#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR)) 24#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) 25#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR)) 26#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) 27 28#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) 29#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) 30#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v) 31#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v) 32#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) 33#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) 34 35#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) 36# define CONFIG_SERIAL_BFIN_CTSRTS 37 38# ifndef CONFIG_UART0_CTS_PIN 39# define CONFIG_UART0_CTS_PIN -1 40# endif 41 42# ifndef CONFIG_UART0_RTS_PIN 43# define CONFIG_UART0_RTS_PIN -1 44# endif 45 46# ifndef CONFIG_UART1_CTS_PIN 47# define CONFIG_UART1_CTS_PIN -1 48# endif 49 50# ifndef CONFIG_UART1_RTS_PIN 51# define CONFIG_UART1_RTS_PIN -1 52# endif 53#endif 54/* 55 * The pin configuration is different from schematic 56 */ 57struct bfin_serial_port { 58 struct uart_port port; 59 unsigned int old_status; 60#ifdef CONFIG_SERIAL_BFIN_DMA 61 int tx_done; 62 int tx_count; 63 struct circ_buf rx_dma_buf; 64 struct timer_list rx_dma_timer; 65 int rx_dma_nrows; 66 unsigned int tx_dma_channel; 67 unsigned int rx_dma_channel; 68 struct work_struct tx_dma_workqueue; 69#else 70 struct work_struct cts_workqueue; 71#endif 72#ifdef CONFIG_SERIAL_BFIN_CTSRTS 73 int cts_pin; 74 int rts_pin; 75#endif 76}; 77 78struct bfin_serial_port bfin_serial_ports[NR_PORTS]; 79struct bfin_serial_res { 80 unsigned long uart_base_addr; 81 int uart_irq; 82#ifdef CONFIG_SERIAL_BFIN_DMA 83 unsigned int uart_tx_dma_channel; 84 unsigned int uart_rx_dma_channel; 85#endif 86#ifdef CONFIG_SERIAL_BFIN_CTSRTS 87 int uart_cts_pin; 88 int uart_rts_pin; 89#endif 90}; 91 92struct bfin_serial_res bfin_serial_resource[] = { 93#ifdef CONFIG_SERIAL_BFIN_UART0 94 { 95 0xFFC00400, 96 IRQ_UART0_RX, 97#ifdef CONFIG_SERIAL_BFIN_DMA 98 CH_UART0_TX, 99 CH_UART0_RX, 100#endif 101#ifdef CONFIG_BFIN_UART0_CTSRTS 102 CONFIG_UART0_CTS_PIN, 103 CONFIG_UART0_RTS_PIN, 104#endif 105 }, 106#endif 107#ifdef CONFIG_SERIAL_BFIN_UART1 108 { 109 0xFFC02000, 110 IRQ_UART1_RX, 111#ifdef CONFIG_SERIAL_BFIN_DMA 112 CH_UART1_TX, 113 CH_UART1_RX, 114#endif 115#ifdef CONFIG_BFIN_UART1_CTSRTS 116 CONFIG_UART1_CTS_PIN, 117 CONFIG_UART1_RTS_PIN, 118#endif 119 }, 120#endif 121}; 122 123int nr_ports = ARRAY_SIZE(bfin_serial_resource); 124 125static void bfin_serial_hw_init(struct bfin_serial_port *uart) 126{ 127 unsigned short val; 128 val = bfin_read16(BFIN_PORT_MUX); 129 val &= ~(PFDE | PFTE); 130 bfin_write16(BFIN_PORT_MUX, val); 131 132 val = bfin_read16(PORTF_FER); 133 val |= 0xF; 134 bfin_write16(PORTF_FER, val); 135 136#ifdef CONFIG_SERIAL_BFIN_CTSRTS 137 if (uart->cts_pin >= 0) { 138 gpio_request(uart->cts_pin, NULL); 139 gpio_direction_input(uart->cts_pin); 140 } 141 142 if (uart->rts_pin >= 0) { 143 gpio_request(uart->rts_pin, NULL); 144 gpio_direction_output(uart->rts_pin); 145 } 146#endif 147} 148