1/*
2 * linux/include/asm-arm/arch-omap/pm.h
3 *
4 * Header file for OMAP Power Management Routines
5 *
6 * Author: MontaVista Software, Inc.
7 *	   support@mvista.com
8 *
9 * Copyright 2002 MontaVista Software Inc.
10 *
11 * Cleanup 2004 for Linux 2.6 by Dirk Behme <dirk.behme@de.bosch.com>
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
24 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 */
33
34#ifndef __ASM_ARCH_OMAP_PM_H
35#define __ASM_ARCH_OMAP_PM_H
36
37/*
38 * ----------------------------------------------------------------------------
39 * Register and offset definitions to be used in PM assembler code
40 * ----------------------------------------------------------------------------
41 */
42#define CLKGEN_REG_ASM_BASE		io_p2v(0xfffece00)
43#define ARM_IDLECT1_ASM_OFFSET		0x04
44#define ARM_IDLECT2_ASM_OFFSET		0x08
45
46#define TCMIF_ASM_BASE			io_p2v(0xfffecc00)
47#define EMIFS_CONFIG_ASM_OFFSET		0x0c
48#define EMIFF_SDRAM_CONFIG_ASM_OFFSET	0x20
49
50/*
51 * ----------------------------------------------------------------------------
52 * Power management bitmasks
53 * ----------------------------------------------------------------------------
54 */
55#define IDLE_WAIT_CYCLES		0x00000fff
56#define PERIPHERAL_ENABLE		0x2
57
58#define SELF_REFRESH_MODE		0x0c000001
59#define IDLE_EMIFS_REQUEST		0xc
60#define MODEM_32K_EN			0x1
61#define PER_EN				0x1
62
63#define CPU_SUSPEND_SIZE		200
64#define ULPD_LOW_PWR_EN			0x0001
65#define ULPD_DEEP_SLEEP_TRANSITION_EN	0x0010
66#define ULPD_SETUP_ANALOG_CELL_3_VAL	0
67#define ULPD_POWER_CTRL_REG_VAL		0x0219
68
69#define DSP_IDLE_DELAY			10
70#define DSP_IDLE			0x0040
71#define DSP_RST				0x0004
72#define DSP_ENABLE			0x0002
73#define SUFFICIENT_DSP_RESET_TIME	1000
74#define DEFAULT_MPUI_CONFIG		0x05cf
75#define ENABLE_XORCLK			0x2
76#define DSP_CLOCK_ENABLE		0x2000
77#define DSP_IDLE_MODE			0x2
78#define TC_IDLE_REQUEST			(0x0000000c)
79
80#define IRQ_LEVEL2			(1<<0)
81#define IRQ_KEYBOARD			(1<<1)
82#define IRQ_UART2			(1<<15)
83
84#define PDE_BIT				0x08
85#define PWD_EN_BIT			0x04
86#define EN_PERCK_BIT			0x04
87
88#define OMAP1510_DEEP_SLEEP_REQUEST	0x0ec7
89#define OMAP1510_BIG_SLEEP_REQUEST	0x0cc5
90#define OMAP1510_IDLE_LOOP_REQUEST	0x0c00
91#define OMAP1510_IDLE_CLOCK_DOMAINS	0x2
92
93/* Both big sleep and deep sleep use same values. Difference is in ULPD. */
94#define OMAP1610_IDLECT1_SLEEP_VAL	0x13c7
95#define OMAP1610_IDLECT2_SLEEP_VAL	0x09c7
96#define OMAP1610_IDLECT3_VAL		0x3f
97#define OMAP1610_IDLECT3_SLEEP_ORMASK	0x2c
98#define OMAP1610_IDLECT3		0xfffece24
99#define OMAP1610_IDLE_LOOP_REQUEST	0x0400
100
101#define OMAP730_IDLECT1_SLEEP_VAL	0x16c7
102#define OMAP730_IDLECT2_SLEEP_VAL	0x09c7
103#define OMAP730_IDLECT3_VAL		0x3f
104#define OMAP730_IDLECT3		0xfffece24
105#define OMAP730_IDLE_LOOP_REQUEST	0x0C00
106
107#if     !defined(CONFIG_ARCH_OMAP730) && !defined(CONFIG_ARCH_OMAP15XX) && \
108	!defined(CONFIG_ARCH_OMAP16XX) && !defined(CONFIG_ARCH_OMAP24XX)
109#error "Power management for this processor not implemented yet"
110#endif
111
112#ifndef __ASSEMBLER__
113
114#include <linux/clk.h>
115
116extern void prevent_idle_sleep(void);
117extern void allow_idle_sleep(void);
118
119/**
120 * clk_deny_idle - Prevents the clock from being idled during MPU idle
121 * @clk: clock signal handle
122 */
123void clk_deny_idle(struct clk *clk);
124
125/**
126 * clk_allow_idle - Counters previous clk_deny_idle
127 * @clk: clock signal handle
128 */
129void clk_deny_idle(struct clk *clk);
130
131extern void omap_pm_idle(void);
132extern void omap_pm_suspend(void);
133extern void omap730_cpu_suspend(unsigned short, unsigned short);
134extern void omap1510_cpu_suspend(unsigned short, unsigned short);
135extern void omap1610_cpu_suspend(unsigned short, unsigned short);
136extern void omap24xx_cpu_suspend(u32 dll_ctrl, u32 cpu_revision);
137extern void omap730_idle_loop_suspend(void);
138extern void omap1510_idle_loop_suspend(void);
139extern void omap1610_idle_loop_suspend(void);
140extern void omap24xx_idle_loop_suspend(void);
141
142extern unsigned int omap730_cpu_suspend_sz;
143extern unsigned int omap1510_cpu_suspend_sz;
144extern unsigned int omap1610_cpu_suspend_sz;
145extern unsigned int omap24xx_cpu_suspend_sz;
146extern unsigned int omap730_idle_loop_suspend_sz;
147extern unsigned int omap1510_idle_loop_suspend_sz;
148extern unsigned int omap1610_idle_loop_suspend_sz;
149extern unsigned int omap24xx_idle_loop_suspend_sz;
150
151#ifdef CONFIG_OMAP_SERIAL_WAKE
152extern void omap_serial_wake_trigger(int enable);
153#else
154#define omap_serial_wakeup_init()	{}
155#define omap_serial_wake_trigger(x)	{}
156#endif	/* CONFIG_OMAP_SERIAL_WAKE */
157
158#define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = omap_readl(x)
159#define ARM_RESTORE(x) omap_writel((arm_sleep_save[ARM_SLEEP_SAVE_##x]), (x))
160#define ARM_SHOW(x) arm_sleep_save[ARM_SLEEP_SAVE_##x]
161
162#define DSP_SAVE(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x] = __raw_readw(x)
163#define DSP_RESTORE(x) __raw_writew((dsp_sleep_save[DSP_SLEEP_SAVE_##x]), (x))
164#define DSP_SHOW(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x]
165
166#define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = omap_readw(x)
167#define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x))
168#define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]
169
170#define MPUI730_SAVE(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x] = omap_readl(x)
171#define MPUI730_RESTORE(x) omap_writel((mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]), (x))
172#define MPUI730_SHOW(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]
173
174#define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x)
175#define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x))
176#define MPUI1510_SHOW(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]
177
178#define MPUI1610_SAVE(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x] = omap_readl(x)
179#define MPUI1610_RESTORE(x) omap_writel((mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]), (x))
180#define MPUI1610_SHOW(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]
181
182#define OMAP24XX_SAVE(x) omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x] = x
183#define OMAP24XX_RESTORE(x) x = omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x]
184#define OMAP24XX_SHOW(x) omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x]
185
186/*
187 * List of global OMAP registers to preserve.
188 * More ones like CP and general purpose register values are preserved
189 * with the stack pointer in sleep.S.
190 */
191
192enum arm_save_state {
193	ARM_SLEEP_SAVE_START = 0,
194	/*
195	 * MPU control registers 32 bits
196	 */
197	ARM_SLEEP_SAVE_ARM_CKCTL,
198	ARM_SLEEP_SAVE_ARM_IDLECT1,
199	ARM_SLEEP_SAVE_ARM_IDLECT2,
200	ARM_SLEEP_SAVE_ARM_IDLECT3,
201	ARM_SLEEP_SAVE_ARM_EWUPCT,
202	ARM_SLEEP_SAVE_ARM_RSTCT1,
203	ARM_SLEEP_SAVE_ARM_RSTCT2,
204	ARM_SLEEP_SAVE_ARM_SYSST,
205	ARM_SLEEP_SAVE_SIZE
206};
207
208enum dsp_save_state {
209	DSP_SLEEP_SAVE_START = 0,
210	/*
211	 * DSP registers 16 bits
212	 */
213	DSP_SLEEP_SAVE_DSP_IDLECT2,
214	DSP_SLEEP_SAVE_SIZE
215};
216
217enum ulpd_save_state {
218	ULPD_SLEEP_SAVE_START = 0,
219	/*
220	 * ULPD registers 16 bits
221	 */
222	ULPD_SLEEP_SAVE_ULPD_IT_STATUS,
223	ULPD_SLEEP_SAVE_ULPD_CLOCK_CTRL,
224	ULPD_SLEEP_SAVE_ULPD_SOFT_REQ,
225	ULPD_SLEEP_SAVE_ULPD_STATUS_REQ,
226	ULPD_SLEEP_SAVE_ULPD_DPLL_CTRL,
227	ULPD_SLEEP_SAVE_ULPD_POWER_CTRL,
228	ULPD_SLEEP_SAVE_SIZE
229};
230
231enum mpui1510_save_state {
232	MPUI1510_SLEEP_SAVE_START = 0,
233	/*
234	 * MPUI registers 32 bits
235	 */
236	MPUI1510_SLEEP_SAVE_MPUI_CTRL,
237	MPUI1510_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
238	MPUI1510_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
239	MPUI1510_SLEEP_SAVE_MPUI_DSP_STATUS,
240	MPUI1510_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
241	MPUI1510_SLEEP_SAVE_EMIFS_CONFIG,
242	MPUI1510_SLEEP_SAVE_OMAP_IH1_MIR,
243	MPUI1510_SLEEP_SAVE_OMAP_IH2_MIR,
244#if defined(CONFIG_ARCH_OMAP15XX)
245	MPUI1510_SLEEP_SAVE_SIZE
246#else
247	MPUI1510_SLEEP_SAVE_SIZE = 0
248#endif
249};
250
251enum mpui730_save_state {
252	MPUI730_SLEEP_SAVE_START = 0,
253	/*
254	 * MPUI registers 32 bits
255	 */
256	MPUI730_SLEEP_SAVE_MPUI_CTRL,
257	MPUI730_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
258	MPUI730_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
259	MPUI730_SLEEP_SAVE_MPUI_DSP_STATUS,
260	MPUI730_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
261	MPUI730_SLEEP_SAVE_EMIFS_CONFIG,
262	MPUI730_SLEEP_SAVE_OMAP_IH1_MIR,
263	MPUI730_SLEEP_SAVE_OMAP_IH2_0_MIR,
264	MPUI730_SLEEP_SAVE_OMAP_IH2_1_MIR,
265#if defined(CONFIG_ARCH_OMAP730)
266	MPUI730_SLEEP_SAVE_SIZE
267#else
268	MPUI730_SLEEP_SAVE_SIZE = 0
269#endif
270};
271
272enum mpui1610_save_state {
273	MPUI1610_SLEEP_SAVE_START = 0,
274	/*
275	 * MPUI registers 32 bits
276	 */
277	MPUI1610_SLEEP_SAVE_MPUI_CTRL,
278	MPUI1610_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
279	MPUI1610_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
280	MPUI1610_SLEEP_SAVE_MPUI_DSP_STATUS,
281	MPUI1610_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
282	MPUI1610_SLEEP_SAVE_EMIFS_CONFIG,
283	MPUI1610_SLEEP_SAVE_OMAP_IH1_MIR,
284	MPUI1610_SLEEP_SAVE_OMAP_IH2_0_MIR,
285	MPUI1610_SLEEP_SAVE_OMAP_IH2_1_MIR,
286	MPUI1610_SLEEP_SAVE_OMAP_IH2_2_MIR,
287	MPUI1610_SLEEP_SAVE_OMAP_IH2_3_MIR,
288#if defined(CONFIG_ARCH_OMAP16XX)
289	MPUI1610_SLEEP_SAVE_SIZE
290#else
291	MPUI1610_SLEEP_SAVE_SIZE = 0
292#endif
293};
294
295enum omap24xx_save_state {
296	OMAP24XX_SLEEP_SAVE_START = 0,
297	OMAP24XX_SLEEP_SAVE_INTC_MIR0,
298	OMAP24XX_SLEEP_SAVE_INTC_MIR1,
299	OMAP24XX_SLEEP_SAVE_INTC_MIR2,
300
301	OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_MPU,
302	OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_CORE,
303	OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_GFX,
304	OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_DSP,
305	OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_MDM,
306
307	OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_MPU,
308	OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_CORE,
309	OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_GFX,
310	OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_DSP,
311	OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_MDM,
312
313	OMAP24XX_SLEEP_SAVE_CM_IDLEST1_CORE,
314	OMAP24XX_SLEEP_SAVE_CM_IDLEST2_CORE,
315	OMAP24XX_SLEEP_SAVE_CM_IDLEST3_CORE,
316	OMAP24XX_SLEEP_SAVE_CM_IDLEST4_CORE,
317	OMAP24XX_SLEEP_SAVE_CM_IDLEST_GFX,
318	OMAP24XX_SLEEP_SAVE_CM_IDLEST_WKUP,
319	OMAP24XX_SLEEP_SAVE_CM_IDLEST_CKGEN,
320	OMAP24XX_SLEEP_SAVE_CM_IDLEST_DSP,
321	OMAP24XX_SLEEP_SAVE_CM_IDLEST_MDM,
322
323	OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE1_CORE,
324	OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE2_CORE,
325	OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE3_CORE,
326	OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE4_CORE,
327	OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_WKUP,
328	OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_PLL,
329	OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_DSP,
330	OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_MDM,
331
332	OMAP24XX_SLEEP_SAVE_CM_FCLKEN1_CORE,
333	OMAP24XX_SLEEP_SAVE_CM_FCLKEN2_CORE,
334	OMAP24XX_SLEEP_SAVE_CM_ICLKEN1_CORE,
335	OMAP24XX_SLEEP_SAVE_CM_ICLKEN2_CORE,
336	OMAP24XX_SLEEP_SAVE_CM_ICLKEN3_CORE,
337	OMAP24XX_SLEEP_SAVE_CM_ICLKEN4_CORE,
338	OMAP24XX_SLEEP_SAVE_GPIO1_IRQENABLE1,
339	OMAP24XX_SLEEP_SAVE_GPIO2_IRQENABLE1,
340	OMAP24XX_SLEEP_SAVE_GPIO3_IRQENABLE1,
341	OMAP24XX_SLEEP_SAVE_GPIO4_IRQENABLE1,
342	OMAP24XX_SLEEP_SAVE_GPIO3_OE,
343	OMAP24XX_SLEEP_SAVE_GPIO4_OE,
344	OMAP24XX_SLEEP_SAVE_GPIO3_RISINGDETECT,
345	OMAP24XX_SLEEP_SAVE_GPIO3_FALLINGDETECT,
346	OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SPI1_NCS2,
347	OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_MCBSP1_DX,
348	OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SSI1_FLAG_TX,
349	OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SYS_NIRQW0,
350	OMAP24XX_SLEEP_SAVE_SIZE
351};
352
353#endif /* ASSEMBLER */
354#endif /* __ASM_ARCH_OMAP_PM_H */
355