1/* 2 * linux/include/asm-arm/arch-ks8695/regs-uart.h 3 * 4 * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> 5 * Copyright (C) 2006 Simtec Electronics 6 * 7 * KS8695 - UART register and bit definitions. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14#ifndef KS8695_UART_H 15#define KS8695_UART_H 16 17#define KS8695_UART_OFFSET (0xF0000 + 0xE000) 18#define KS8695_UART_VA (KS8695_IO_VA + KS8695_UART_OFFSET) 19#define KS8695_UART_PA (KS8695_IO_PA + KS8695_UART_OFFSET) 20 21 22/* 23 * UART registers 24 */ 25#define KS8695_URRB (0x00) /* Receive Buffer Register */ 26#define KS8695_URTH (0x04) /* Transmit Holding Register */ 27#define KS8695_URFC (0x08) /* FIFO Control Register */ 28#define KS8695_URLC (0x0C) /* Line Control Register */ 29#define KS8695_URMC (0x10) /* Modem Control Register */ 30#define KS8695_URLS (0x14) /* Line Status Register */ 31#define KS8695_URMS (0x18) /* Modem Status Register */ 32#define KS8695_URBD (0x1C) /* Baud Rate Divisor Register */ 33#define KS8695_USR (0x20) /* Status Register */ 34 35 36/* FIFO Control Register */ 37#define URFC_URFRT (3 << 6) /* Receive FIFO Trigger Level */ 38#define URFC_URFRT_1 (0 << 6) 39#define URFC_URFRT_4 (1 << 6) 40#define URFC_URFRT_8 (2 << 6) 41#define URFC_URFRT_14 (3 << 6) 42#define URFC_URTFR (1 << 2) /* Transmit FIFO Reset */ 43#define URFC_URRFR (1 << 1) /* Receive FIFO Reset */ 44#define URFC_URFE (1 << 0) /* FIFO Enable */ 45 46/* Line Control Register */ 47#define URLC_URSBC (1 << 6) /* Set Break Condition */ 48#define URLC_PARITY (7 << 3) /* Parity */ 49#define URPE_NONE (0 << 3) 50#define URPE_ODD (1 << 3) 51#define URPE_EVEN (3 << 3) 52#define URPE_MARK (5 << 3) 53#define URPE_SPACE (7 << 3) 54#define URLC_URSB (1 << 2) /* Stop Bits */ 55#define URLC_URCL (3 << 0) /* Character Length */ 56#define URCL_5 (0 << 0) 57#define URCL_6 (1 << 0) 58#define URCL_7 (2 << 0) 59#define URCL_8 (3 << 0) 60 61/* Modem Control Register */ 62#define URMC_URLB (1 << 4) /* Loop-back mode */ 63#define URMC_UROUT2 (1 << 3) /* OUT2 signal */ 64#define URMC_UROUT1 (1 << 2) /* OUT1 signal */ 65#define URMC_URRTS (1 << 1) /* Request to Send */ 66#define URMC_URDTR (1 << 0) /* Data Terminal Ready */ 67 68/* Line Status Register */ 69#define URLS_URRFE (1 << 7) /* Receive FIFO Error */ 70#define URLS_URTE (1 << 6) /* Transmit Empty */ 71#define URLS_URTHRE (1 << 5) /* Transmit Holding Register Empty */ 72#define URLS_URBI (1 << 4) /* Break Interrupt */ 73#define URLS_URFE (1 << 3) /* Framing Error */ 74#define URLS_URPE (1 << 2) /* Parity Error */ 75#define URLS_URROE (1 << 1) /* Receive Overrun Error */ 76#define URLS_URDR (1 << 0) /* Receive Data Ready */ 77 78/* Modem Status Register */ 79#define URMS_URDCD (1 << 7) /* Data Carrier Detect */ 80#define URMS_URRI (1 << 6) /* Ring Indicator */ 81#define URMS_URDSR (1 << 5) /* Data Set Ready */ 82#define URMS_URCTS (1 << 4) /* Clear to Send */ 83#define URMS_URDDCD (1 << 3) /* Delta Data Carrier Detect */ 84#define URMS_URTERI (1 << 2) /* Trailing Edge Ring Indicator */ 85#define URMS_URDDST (1 << 1) /* Delta Data Set Ready */ 86#define URMS_URDCTS (1 << 0) /* Delta Clear to Send */ 87 88/* Status Register */ 89#define USR_UTI (1 << 0) /* Timeout Indication */ 90 91 92#endif 93