1/* 2 * include/asm-arm/arch-at91/at91_ssc.h 3 * 4 * Copyright (C) SAN People 5 * 6 * Serial Synchronous Controller (SSC) registers. 7 * Based on AT91RM9200 datasheet revision E. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 */ 14 15#ifndef AT91_SSC_H 16#define AT91_SSC_H 17 18#define AT91_SSC_CR 0x00 /* Control Register */ 19#define AT91_SSC_RXEN (1 << 0) /* Receive Enable */ 20#define AT91_SSC_RXDIS (1 << 1) /* Receive Disable */ 21#define AT91_SSC_TXEN (1 << 8) /* Transmit Enable */ 22#define AT91_SSC_TXDIS (1 << 9) /* Transmit Disable */ 23#define AT91_SSC_SWRST (1 << 15) /* Software Reset */ 24 25#define AT91_SSC_CMR 0x04 /* Clock Mode Register */ 26#define AT91_SSC_CMR_DIV (0xfff << 0) /* Clock Divider */ 27 28#define AT91_SSC_RCMR 0x10 /* Receive Clock Mode Register */ 29#define AT91_SSC_CKS (3 << 0) /* Clock Selection */ 30#define AT91_SSC_CKS_DIV (0 << 0) 31#define AT91_SSC_CKS_CLOCK (1 << 0) 32#define AT91_SSC_CKS_PIN (2 << 0) 33#define AT91_SSC_CKO (7 << 2) /* Clock Output Mode Selection */ 34#define AT91_SSC_CKO_NONE (0 << 2) 35#define AT91_SSC_CKO_CONTINUOUS (1 << 2) 36#define AT91_SSC_CKI (1 << 5) /* Clock Inversion */ 37#define AT91_SSC_CKI_FALLING (0 << 5) 38#define AT91_SSC_CK_RISING (1 << 5) 39#define AT91_SSC_CKG (1 << 6) /* Receive Clock Gating Selection [AT91SAM9261 only] */ 40#define AT91_SSC_CKG_NONE (0 << 6) 41#define AT91_SSC_CKG_RFLOW (1 << 6) 42#define AT91_SSC_CKG_RFHIGH (2 << 6) 43#define AT91_SSC_START (0xf << 8) /* Start Selection */ 44#define AT91_SSC_START_CONTINUOUS (0 << 8) 45#define AT91_SSC_START_TX_RX (1 << 8) 46#define AT91_SSC_START_LOW_RF (2 << 8) 47#define AT91_SSC_START_HIGH_RF (3 << 8) 48#define AT91_SSC_START_FALLING_RF (4 << 8) 49#define AT91_SSC_START_RISING_RF (5 << 8) 50#define AT91_SSC_START_LEVEL_RF (6 << 8) 51#define AT91_SSC_START_EDGE_RF (7 << 8) 52#define AT91_SSC_STOP (1 << 12) /* Receive Stop Selection [AT91SAM9261 only] */ 53#define AT91_SSC_STTDLY (0xff << 16) /* Start Delay */ 54#define AT91_SSC_PERIOD (0xff << 24) /* Period Divider Selection */ 55 56#define AT91_SSC_RFMR 0x14 /* Receive Frame Mode Register */ 57#define AT91_SSC_DATALEN (0x1f << 0) /* Data Length */ 58#define AT91_SSC_LOOP (1 << 5) /* Loop Mode */ 59#define AT91_SSC_MSBF (1 << 7) /* Most Significant Bit First */ 60#define AT91_SSC_DATNB (0xf << 8) /* Data Number per Frame */ 61#define AT91_SSC_FSLEN (0xf << 16) /* Frame Sync Length */ 62#define AT91_SSC_FSOS (7 << 20) /* Frame Sync Output Selection */ 63#define AT91_SSC_FSOS_NONE (0 << 20) 64#define AT91_SSC_FSOS_NEGATIVE (1 << 20) 65#define AT91_SSC_FSOS_POSITIVE (2 << 20) 66#define AT91_SSC_FSOS_LOW (3 << 20) 67#define AT91_SSC_FSOS_HIGH (4 << 20) 68#define AT91_SSC_FSOS_TOGGLE (5 << 20) 69#define AT91_SSC_FSEDGE (1 << 24) /* Frame Sync Edge Detection */ 70#define AT91_SSC_FSEDGE_POSITIVE (0 << 24) 71#define AT91_SSC_FSEDGE_NEGATIVE (1 << 24) 72 73#define AT91_SSC_TCMR 0x18 /* Transmit Clock Mode Register */ 74#define AT91_SSC_TFMR 0x1c /* Transmit Fram Mode Register */ 75#define AT91_SSC_DATDEF (1 << 5) /* Data Default Value */ 76#define AT91_SSC_FSDEN (1 << 23) /* Frame Sync Data Enable */ 77 78#define AT91_SSC_RHR 0x20 /* Receive Holding Register */ 79#define AT91_SSC_THR 0x24 /* Transmit Holding Register */ 80#define AT91_SSC_RSHR 0x30 /* Receive Sync Holding Register */ 81#define AT91_SSC_TSHR 0x34 /* Transmit Sync Holding Register */ 82 83#define AT91_SSC_RC0R 0x38 /* Receive Compare 0 Register [AT91SAM9261 only] */ 84#define AT91_SSC_RC1R 0x3c /* Receive Compare 1 Register [AT91SAM9261 only] */ 85 86#define AT91_SSC_SR 0x40 /* Status Register */ 87#define AT91_SSC_TXRDY (1 << 0) /* Transmit Ready */ 88#define AT91_SSC_TXEMPTY (1 << 1) /* Transmit Empty */ 89#define AT91_SSC_ENDTX (1 << 2) /* End of Transmission */ 90#define AT91_SSC_TXBUFE (1 << 3) /* Transmit Buffer Empty */ 91#define AT91_SSC_RXRDY (1 << 4) /* Receive Ready */ 92#define AT91_SSC_OVRUN (1 << 5) /* Receive Overrun */ 93#define AT91_SSC_ENDRX (1 << 6) /* End of Reception */ 94#define AT91_SSC_RXBUFF (1 << 7) /* Receive Buffer Full */ 95#define AT91_SSC_CP0 (1 << 8) /* Compare 0 [AT91SAM9261 only] */ 96#define AT91_SSC_CP1 (1 << 9) /* Compare 1 [AT91SAM9261 only] */ 97#define AT91_SSC_TXSYN (1 << 10) /* Transmit Sync */ 98#define AT91_SSC_RXSYN (1 << 11) /* Receive Sync */ 99#define AT91_SSC_TXENA (1 << 16) /* Transmit Enable */ 100#define AT91_SSC_RXENA (1 << 17) /* Receive Enable */ 101 102#define AT91_SSC_IER 0x44 /* Interrupt Enable Register */ 103#define AT91_SSC_IDR 0x48 /* Interrupt Disable Register */ 104#define AT91_SSC_IMR 0x4c /* Interrupt Mask Register */ 105 106#endif 107