1#ifndef __ALPHA_T2__H__ 2#define __ALPHA_T2__H__ 3 4#include <linux/types.h> 5#include <linux/spinlock.h> 6#include <asm/compiler.h> 7#include <asm/system.h> 8 9/* 10 * T2 is the internal name for the core logic chipset which provides 11 * memory controller and PCI access for the SABLE-based systems. 12 * 13 * This file is based on: 14 * 15 * SABLE I/O Specification 16 * Revision/Update Information: 1.3 17 * 18 * jestabro@amt.tay1.dec.com Initial Version. 19 * 20 */ 21 22#define T2_MEM_R1_MASK 0x07ffffff /* Mem sparse region 1 mask is 26 bits */ 23 24/* GAMMA-SABLE is a SABLE with EV5-based CPUs */ 25/* All LYNX machines, EV4 or EV5, use the GAMMA bias also */ 26#define _GAMMA_BIAS 0x8000000000UL 27 28#if defined(CONFIG_ALPHA_GENERIC) 29#define GAMMA_BIAS alpha_mv.sys.t2.gamma_bias 30#elif defined(CONFIG_ALPHA_GAMMA) 31#define GAMMA_BIAS _GAMMA_BIAS 32#else 33#define GAMMA_BIAS 0 34#endif 35 36/* 37 * Memory spaces: 38 */ 39#define T2_CONF (IDENT_ADDR + GAMMA_BIAS + 0x390000000UL) 40#define T2_IO (IDENT_ADDR + GAMMA_BIAS + 0x3a0000000UL) 41#define T2_SPARSE_MEM (IDENT_ADDR + GAMMA_BIAS + 0x200000000UL) 42#define T2_DENSE_MEM (IDENT_ADDR + GAMMA_BIAS + 0x3c0000000UL) 43 44#define T2_IOCSR (IDENT_ADDR + GAMMA_BIAS + 0x38e000000UL) 45#define T2_CERR1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000020UL) 46#define T2_CERR2 (IDENT_ADDR + GAMMA_BIAS + 0x38e000040UL) 47#define T2_CERR3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000060UL) 48#define T2_PERR1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000080UL) 49#define T2_PERR2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0000a0UL) 50#define T2_PSCR (IDENT_ADDR + GAMMA_BIAS + 0x38e0000c0UL) 51#define T2_HAE_1 (IDENT_ADDR + GAMMA_BIAS + 0x38e0000e0UL) 52#define T2_HAE_2 (IDENT_ADDR + GAMMA_BIAS + 0x38e000100UL) 53#define T2_HBASE (IDENT_ADDR + GAMMA_BIAS + 0x38e000120UL) 54#define T2_WBASE1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000140UL) 55#define T2_WMASK1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000160UL) 56#define T2_TBASE1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000180UL) 57#define T2_WBASE2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0001a0UL) 58#define T2_WMASK2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0001c0UL) 59#define T2_TBASE2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0001e0UL) 60#define T2_TLBBR (IDENT_ADDR + GAMMA_BIAS + 0x38e000200UL) 61#define T2_IVR (IDENT_ADDR + GAMMA_BIAS + 0x38e000220UL) 62#define T2_HAE_3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000240UL) 63#define T2_HAE_4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000260UL) 64 65/* The CSRs below are T3/T4 only */ 66#define T2_WBASE3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000280UL) 67#define T2_WMASK3 (IDENT_ADDR + GAMMA_BIAS + 0x38e0002a0UL) 68#define T2_TBASE3 (IDENT_ADDR + GAMMA_BIAS + 0x38e0002c0UL) 69 70#define T2_TDR0 (IDENT_ADDR + GAMMA_BIAS + 0x38e000300UL) 71#define T2_TDR1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000320UL) 72#define T2_TDR2 (IDENT_ADDR + GAMMA_BIAS + 0x38e000340UL) 73#define T2_TDR3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000360UL) 74#define T2_TDR4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000380UL) 75#define T2_TDR5 (IDENT_ADDR + GAMMA_BIAS + 0x38e0003a0UL) 76#define T2_TDR6 (IDENT_ADDR + GAMMA_BIAS + 0x38e0003c0UL) 77#define T2_TDR7 (IDENT_ADDR + GAMMA_BIAS + 0x38e0003e0UL) 78 79#define T2_WBASE4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000400UL) 80#define T2_WMASK4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000420UL) 81#define T2_TBASE4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000440UL) 82 83#define T2_AIR (IDENT_ADDR + GAMMA_BIAS + 0x38e000460UL) 84#define T2_VAR (IDENT_ADDR + GAMMA_BIAS + 0x38e000480UL) 85#define T2_DIR (IDENT_ADDR + GAMMA_BIAS + 0x38e0004a0UL) 86#define T2_ICE (IDENT_ADDR + GAMMA_BIAS + 0x38e0004c0UL) 87 88#define T2_HAE_ADDRESS T2_HAE_1 89 90/* T2 CSRs are in the non-cachable primary IO space from 3.8000.0000 to 91 3.8fff.ffff 92 * 93 * +--------------+ 3 8000 0000 94 * | CPU 0 CSRs | 95 * +--------------+ 3 8100 0000 96 * | CPU 1 CSRs | 97 * +--------------+ 3 8200 0000 98 * | CPU 2 CSRs | 99 * +--------------+ 3 8300 0000 100 * | CPU 3 CSRs | 101 * +--------------+ 3 8400 0000 102 * | CPU Reserved | 103 * +--------------+ 3 8700 0000 104 * | Mem Reserved | 105 * +--------------+ 3 8800 0000 106 * | Mem 0 CSRs | 107 * +--------------+ 3 8900 0000 108 * | Mem 1 CSRs | 109 * +--------------+ 3 8a00 0000 110 * | Mem 2 CSRs | 111 * +--------------+ 3 8b00 0000 112 * | Mem 3 CSRs | 113 * +--------------+ 3 8c00 0000 114 * | Mem Reserved | 115 * +--------------+ 3 8e00 0000 116 * | PCI Bridge | 117 * +--------------+ 3 8f00 0000 118 * | Expansion IO | 119 * +--------------+ 3 9000 0000 120 * 121 * 122 */ 123#define T2_CPU0_BASE (IDENT_ADDR + GAMMA_BIAS + 0x380000000L) 124#define T2_CPU1_BASE (IDENT_ADDR + GAMMA_BIAS + 0x381000000L) 125#define T2_CPU2_BASE (IDENT_ADDR + GAMMA_BIAS + 0x382000000L) 126#define T2_CPU3_BASE (IDENT_ADDR + GAMMA_BIAS + 0x383000000L) 127 128#define T2_CPUn_BASE(n) (T2_CPU0_BASE + (((n)&3) * 0x001000000L)) 129 130#define T2_MEM0_BASE (IDENT_ADDR + GAMMA_BIAS + 0x388000000L) 131#define T2_MEM1_BASE (IDENT_ADDR + GAMMA_BIAS + 0x389000000L) 132#define T2_MEM2_BASE (IDENT_ADDR + GAMMA_BIAS + 0x38a000000L) 133#define T2_MEM3_BASE (IDENT_ADDR + GAMMA_BIAS + 0x38b000000L) 134 135 136/* 137 * Sable CPU Module CSRS 138 * 139 * These are CSRs for hardware other than the CPU chip on the CPU module. 140 * The CPU module has Backup Cache control logic, Cbus control logic, and 141 * interrupt control logic on it. There is a duplicate tag store to speed 142 * up maintaining cache coherency. 143 */ 144 145struct sable_cpu_csr { 146 unsigned long bcc; long fill_00[3]; /* Backup Cache Control */ 147 unsigned long bcce; long fill_01[3]; /* Backup Cache Correctable Error */ 148 unsigned long bccea; long fill_02[3]; /* B-Cache Corr Err Address Latch */ 149 unsigned long bcue; long fill_03[3]; /* B-Cache Uncorrectable Error */ 150 unsigned long bcuea; long fill_04[3]; /* B-Cache Uncorr Err Addr Latch */ 151 unsigned long dter; long fill_05[3]; /* Duplicate Tag Error */ 152 unsigned long cbctl; long fill_06[3]; /* CBus Control */ 153 unsigned long cbe; long fill_07[3]; /* CBus Error */ 154 unsigned long cbeal; long fill_08[3]; /* CBus Error Addr Latch low */ 155 unsigned long cbeah; long fill_09[3]; /* CBus Error Addr Latch high */ 156 unsigned long pmbx; long fill_10[3]; /* Processor Mailbox */ 157 unsigned long ipir; long fill_11[3]; /* Inter-Processor Int Request */ 158 unsigned long sic; long fill_12[3]; /* System Interrupt Clear */ 159 unsigned long adlk; long fill_13[3]; /* Address Lock (LDxL/STxC) */ 160 unsigned long madrl; long fill_14[3]; /* CBus Miss Address */ 161 unsigned long rev; long fill_15[3]; /* CMIC Revision */ 162}; 163 164/* 165 * Data structure for handling T2 machine checks: 166 */ 167struct el_t2_frame_header { 168 unsigned int elcf_fid; /* Frame ID (from above) */ 169 unsigned int elcf_size; /* Size of frame in bytes */ 170}; 171 172struct el_t2_procdata_mcheck { 173 unsigned long elfmc_paltemp[32]; /* PAL TEMP REGS. */ 174 /* EV4-specific fields */ 175 unsigned long elfmc_exc_addr; /* Addr of excepting insn. */ 176 unsigned long elfmc_exc_sum; /* Summary of arith traps. */ 177 unsigned long elfmc_exc_mask; /* Exception mask (from exc_sum). */ 178 unsigned long elfmc_iccsr; /* IBox hardware enables. */ 179 unsigned long elfmc_pal_base; /* Base address for PALcode. */ 180 unsigned long elfmc_hier; /* Hardware Interrupt Enable. */ 181 unsigned long elfmc_hirr; /* Hardware Interrupt Request. */ 182 unsigned long elfmc_mm_csr; /* D-stream fault info. */ 183 unsigned long elfmc_dc_stat; /* D-cache status (ECC/Parity Err). */ 184 unsigned long elfmc_dc_addr; /* EV3 Phys Addr for ECC/DPERR. */ 185 unsigned long elfmc_abox_ctl; /* ABox Control Register. */ 186 unsigned long elfmc_biu_stat; /* BIU Status. */ 187 unsigned long elfmc_biu_addr; /* BUI Address. */ 188 unsigned long elfmc_biu_ctl; /* BIU Control. */ 189 unsigned long elfmc_fill_syndrome; /* For correcting ECC errors. */ 190 unsigned long elfmc_fill_addr;/* Cache block which was being read. */ 191 unsigned long elfmc_va; /* Effective VA of fault or miss. */ 192 unsigned long elfmc_bc_tag; /* Backup Cache Tag Probe Results. */ 193}; 194 195/* 196 * Sable processor specific Machine Check Data segment. 197 */ 198 199struct el_t2_logout_header { 200 unsigned int elfl_size; /* size in bytes of logout area. */ 201 unsigned int elfl_sbz1:31; /* Should be zero. */ 202 unsigned int elfl_retry:1; /* Retry flag. */ 203 unsigned int elfl_procoffset; /* Processor-specific offset. */ 204 unsigned int elfl_sysoffset; /* Offset of system-specific. */ 205 unsigned int elfl_error_type; /* PAL error type code. */ 206 unsigned int elfl_frame_rev; /* PAL Frame revision. */ 207}; 208struct el_t2_sysdata_mcheck { 209 unsigned long elcmc_bcc; /* CSR 0 */ 210 unsigned long elcmc_bcce; /* CSR 1 */ 211 unsigned long elcmc_bccea; /* CSR 2 */ 212 unsigned long elcmc_bcue; /* CSR 3 */ 213 unsigned long elcmc_bcuea; /* CSR 4 */ 214 unsigned long elcmc_dter; /* CSR 5 */ 215 unsigned long elcmc_cbctl; /* CSR 6 */ 216 unsigned long elcmc_cbe; /* CSR 7 */ 217 unsigned long elcmc_cbeal; /* CSR 8 */ 218 unsigned long elcmc_cbeah; /* CSR 9 */ 219 unsigned long elcmc_pmbx; /* CSR 10 */ 220 unsigned long elcmc_ipir; /* CSR 11 */ 221 unsigned long elcmc_sic; /* CSR 12 */ 222 unsigned long elcmc_adlk; /* CSR 13 */ 223 unsigned long elcmc_madrl; /* CSR 14 */ 224 unsigned long elcmc_crrev4; /* CSR 15 */ 225}; 226 227/* 228 * Sable memory error frame - sable pfms section 3.42 229 */ 230struct el_t2_data_memory { 231 struct el_t2_frame_header elcm_hdr; /* ID$MEM-FERR = 0x08 */ 232 unsigned int elcm_module; /* Module id. */ 233 unsigned int elcm_res04; /* Reserved. */ 234 unsigned long elcm_merr; /* CSR0: Error Reg 1. */ 235 unsigned long elcm_mcmd1; /* CSR1: Command Trap 1. */ 236 unsigned long elcm_mcmd2; /* CSR2: Command Trap 2. */ 237 unsigned long elcm_mconf; /* CSR3: Configuration. */ 238 unsigned long elcm_medc1; /* CSR4: EDC Status 1. */ 239 unsigned long elcm_medc2; /* CSR5: EDC Status 2. */ 240 unsigned long elcm_medcc; /* CSR6: EDC Control. */ 241 unsigned long elcm_msctl; /* CSR7: Stream Buffer Control. */ 242 unsigned long elcm_mref; /* CSR8: Refresh Control. */ 243 unsigned long elcm_filter; /* CSR9: CRD Filter Control. */ 244}; 245 246 247/* 248 * Sable other CPU error frame - sable pfms section 3.43 249 */ 250struct el_t2_data_other_cpu { 251 short elco_cpuid; /* CPU ID */ 252 short elco_res02[3]; 253 unsigned long elco_bcc; /* CSR 0 */ 254 unsigned long elco_bcce; /* CSR 1 */ 255 unsigned long elco_bccea; /* CSR 2 */ 256 unsigned long elco_bcue; /* CSR 3 */ 257 unsigned long elco_bcuea; /* CSR 4 */ 258 unsigned long elco_dter; /* CSR 5 */ 259 unsigned long elco_cbctl; /* CSR 6 */ 260 unsigned long elco_cbe; /* CSR 7 */ 261 unsigned long elco_cbeal; /* CSR 8 */ 262 unsigned long elco_cbeah; /* CSR 9 */ 263 unsigned long elco_pmbx; /* CSR 10 */ 264 unsigned long elco_ipir; /* CSR 11 */ 265 unsigned long elco_sic; /* CSR 12 */ 266 unsigned long elco_adlk; /* CSR 13 */ 267 unsigned long elco_madrl; /* CSR 14 */ 268 unsigned long elco_crrev4; /* CSR 15 */ 269}; 270 271/* 272 * Sable other CPU error frame - sable pfms section 3.44 273 */ 274struct el_t2_data_t2{ 275 struct el_t2_frame_header elct_hdr; /* ID$T2-FRAME */ 276 unsigned long elct_iocsr; /* IO Control and Status Register */ 277 unsigned long elct_cerr1; /* Cbus Error Register 1 */ 278 unsigned long elct_cerr2; /* Cbus Error Register 2 */ 279 unsigned long elct_cerr3; /* Cbus Error Register 3 */ 280 unsigned long elct_perr1; /* PCI Error Register 1 */ 281 unsigned long elct_perr2; /* PCI Error Register 2 */ 282 unsigned long elct_hae0_1; /* High Address Extension Register 1 */ 283 unsigned long elct_hae0_2; /* High Address Extension Register 2 */ 284 unsigned long elct_hbase; /* High Base Register */ 285 unsigned long elct_wbase1; /* Window Base Register 1 */ 286 unsigned long elct_wmask1; /* Window Mask Register 1 */ 287 unsigned long elct_tbase1; /* Translated Base Register 1 */ 288 unsigned long elct_wbase2; /* Window Base Register 2 */ 289 unsigned long elct_wmask2; /* Window Mask Register 2 */ 290 unsigned long elct_tbase2; /* Translated Base Register 2 */ 291 unsigned long elct_tdr0; /* TLB Data Register 0 */ 292 unsigned long elct_tdr1; /* TLB Data Register 1 */ 293 unsigned long elct_tdr2; /* TLB Data Register 2 */ 294 unsigned long elct_tdr3; /* TLB Data Register 3 */ 295 unsigned long elct_tdr4; /* TLB Data Register 4 */ 296 unsigned long elct_tdr5; /* TLB Data Register 5 */ 297 unsigned long elct_tdr6; /* TLB Data Register 6 */ 298 unsigned long elct_tdr7; /* TLB Data Register 7 */ 299}; 300 301/* 302 * Sable error log data structure - sable pfms section 3.40 303 */ 304struct el_t2_data_corrected { 305 unsigned long elcpb_biu_stat; 306 unsigned long elcpb_biu_addr; 307 unsigned long elcpb_biu_ctl; 308 unsigned long elcpb_fill_syndrome; 309 unsigned long elcpb_fill_addr; 310 unsigned long elcpb_bc_tag; 311}; 312 313/* 314 * Sable error log data structure 315 * Note there are 4 memory slots on sable (see t2.h) 316 */ 317struct el_t2_frame_mcheck { 318 struct el_t2_frame_header elfmc_header; /* ID$P-FRAME_MCHECK */ 319 struct el_t2_logout_header elfmc_hdr; 320 struct el_t2_procdata_mcheck elfmc_procdata; 321 struct el_t2_sysdata_mcheck elfmc_sysdata; 322 struct el_t2_data_t2 elfmc_t2data; 323 struct el_t2_data_memory elfmc_memdata[4]; 324 struct el_t2_frame_header elfmc_footer; /* empty */ 325}; 326 327 328/* 329 * Sable error log data structures on memory errors 330 */ 331struct el_t2_frame_corrected { 332 struct el_t2_frame_header elfcc_header; /* ID$P-BC-COR */ 333 struct el_t2_logout_header elfcc_hdr; 334 struct el_t2_data_corrected elfcc_procdata; 335/* struct el_t2_data_t2 elfcc_t2data; */ 336/* struct el_t2_data_memory elfcc_memdata[4]; */ 337 struct el_t2_frame_header elfcc_footer; /* empty */ 338}; 339 340 341#ifdef __KERNEL__ 342 343#ifndef __EXTERN_INLINE 344#define __EXTERN_INLINE extern inline 345#define __IO_EXTERN_INLINE 346#endif 347 348/* 349 * I/O functions: 350 * 351 * T2 (the core logic PCI/memory support chipset for the SABLE 352 * series of processors uses a sparse address mapping scheme to 353 * get at PCI memory and I/O. 354 */ 355 356#define vip volatile int * 357#define vuip volatile unsigned int * 358 359static inline u8 t2_inb(unsigned long addr) 360{ 361 long result = *(vip) ((addr << 5) + T2_IO + 0x00); 362 return __kernel_extbl(result, addr & 3); 363} 364 365static inline void t2_outb(u8 b, unsigned long addr) 366{ 367 unsigned long w; 368 369 w = __kernel_insbl(b, addr & 3); 370 *(vuip) ((addr << 5) + T2_IO + 0x00) = w; 371 mb(); 372} 373 374static inline u16 t2_inw(unsigned long addr) 375{ 376 long result = *(vip) ((addr << 5) + T2_IO + 0x08); 377 return __kernel_extwl(result, addr & 3); 378} 379 380static inline void t2_outw(u16 b, unsigned long addr) 381{ 382 unsigned long w; 383 384 w = __kernel_inswl(b, addr & 3); 385 *(vuip) ((addr << 5) + T2_IO + 0x08) = w; 386 mb(); 387} 388 389static inline u32 t2_inl(unsigned long addr) 390{ 391 return *(vuip) ((addr << 5) + T2_IO + 0x18); 392} 393 394static inline void t2_outl(u32 b, unsigned long addr) 395{ 396 *(vuip) ((addr << 5) + T2_IO + 0x18) = b; 397 mb(); 398} 399 400 401/* 402 * Memory functions. 403 * 404 * For reading and writing 8 and 16 bit quantities we need to 405 * go through one of the three sparse address mapping regions 406 * and use the HAE_MEM CSR to provide some bits of the address. 407 * The following few routines use only sparse address region 1 408 * which gives 1Gbyte of accessible space which relates exactly 409 * to the amount of PCI memory mapping *into* system address space. 410 * See p 6-17 of the specification but it looks something like this: 411 * 412 * 21164 Address: 413 * 414 * 3 2 1 415 * 9876543210987654321098765432109876543210 416 * 1ZZZZ0.PCI.QW.Address............BBLL 417 * 418 * ZZ = SBZ 419 * BB = Byte offset 420 * LL = Transfer length 421 * 422 * PCI Address: 423 * 424 * 3 2 1 425 * 10987654321098765432109876543210 426 * HHH....PCI.QW.Address........ 00 427 * 428 * HHH = 31:29 HAE_MEM CSR 429 * 430 */ 431 432#define t2_set_hae { \ 433 msb = addr >> 27; \ 434 addr &= T2_MEM_R1_MASK; \ 435 set_hae(msb); \ 436} 437 438static DEFINE_SPINLOCK(t2_hae_lock); 439 440/* 441 * NOTE: take T2_DENSE_MEM off in each readX/writeX routine, since 442 * they may be called directly, rather than through the 443 * ioreadNN/iowriteNN routines. 444 */ 445 446__EXTERN_INLINE u8 t2_readb(const volatile void __iomem *xaddr) 447{ 448 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; 449 unsigned long result, msb; 450 unsigned long flags; 451 spin_lock_irqsave(&t2_hae_lock, flags); 452 453 t2_set_hae; 454 455 result = *(vip) ((addr << 5) + T2_SPARSE_MEM + 0x00); 456 spin_unlock_irqrestore(&t2_hae_lock, flags); 457 return __kernel_extbl(result, addr & 3); 458} 459 460__EXTERN_INLINE u16 t2_readw(const volatile void __iomem *xaddr) 461{ 462 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; 463 unsigned long result, msb; 464 unsigned long flags; 465 spin_lock_irqsave(&t2_hae_lock, flags); 466 467 t2_set_hae; 468 469 result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08); 470 spin_unlock_irqrestore(&t2_hae_lock, flags); 471 return __kernel_extwl(result, addr & 3); 472} 473 474/* 475 * On SABLE with T2, we must use SPARSE memory even for 32-bit access, 476 * because we cannot access all of DENSE without changing its HAE. 477 */ 478__EXTERN_INLINE u32 t2_readl(const volatile void __iomem *xaddr) 479{ 480 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; 481 unsigned long result, msb; 482 unsigned long flags; 483 spin_lock_irqsave(&t2_hae_lock, flags); 484 485 t2_set_hae; 486 487 result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18); 488 spin_unlock_irqrestore(&t2_hae_lock, flags); 489 return result & 0xffffffffUL; 490} 491 492__EXTERN_INLINE u64 t2_readq(const volatile void __iomem *xaddr) 493{ 494 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; 495 unsigned long r0, r1, work, msb; 496 unsigned long flags; 497 spin_lock_irqsave(&t2_hae_lock, flags); 498 499 t2_set_hae; 500 501 work = (addr << 5) + T2_SPARSE_MEM + 0x18; 502 r0 = *(vuip)(work); 503 r1 = *(vuip)(work + (4 << 5)); 504 spin_unlock_irqrestore(&t2_hae_lock, flags); 505 return r1 << 32 | r0; 506} 507 508__EXTERN_INLINE void t2_writeb(u8 b, volatile void __iomem *xaddr) 509{ 510 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; 511 unsigned long msb, w; 512 unsigned long flags; 513 spin_lock_irqsave(&t2_hae_lock, flags); 514 515 t2_set_hae; 516 517 w = __kernel_insbl(b, addr & 3); 518 *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x00) = w; 519 spin_unlock_irqrestore(&t2_hae_lock, flags); 520} 521 522__EXTERN_INLINE void t2_writew(u16 b, volatile void __iomem *xaddr) 523{ 524 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; 525 unsigned long msb, w; 526 unsigned long flags; 527 spin_lock_irqsave(&t2_hae_lock, flags); 528 529 t2_set_hae; 530 531 w = __kernel_inswl(b, addr & 3); 532 *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08) = w; 533 spin_unlock_irqrestore(&t2_hae_lock, flags); 534} 535 536/* 537 * On SABLE with T2, we must use SPARSE memory even for 32-bit access, 538 * because we cannot access all of DENSE without changing its HAE. 539 */ 540__EXTERN_INLINE void t2_writel(u32 b, volatile void __iomem *xaddr) 541{ 542 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; 543 unsigned long msb; 544 unsigned long flags; 545 spin_lock_irqsave(&t2_hae_lock, flags); 546 547 t2_set_hae; 548 549 *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18) = b; 550 spin_unlock_irqrestore(&t2_hae_lock, flags); 551} 552 553__EXTERN_INLINE void t2_writeq(u64 b, volatile void __iomem *xaddr) 554{ 555 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; 556 unsigned long msb, work; 557 unsigned long flags; 558 spin_lock_irqsave(&t2_hae_lock, flags); 559 560 t2_set_hae; 561 562 work = (addr << 5) + T2_SPARSE_MEM + 0x18; 563 *(vuip)work = b; 564 *(vuip)(work + (4 << 5)) = b >> 32; 565 spin_unlock_irqrestore(&t2_hae_lock, flags); 566} 567 568__EXTERN_INLINE void __iomem *t2_ioportmap(unsigned long addr) 569{ 570 return (void __iomem *)(addr + T2_IO); 571} 572 573__EXTERN_INLINE void __iomem *t2_ioremap(unsigned long addr, 574 unsigned long size) 575{ 576 return (void __iomem *)(addr + T2_DENSE_MEM); 577} 578 579__EXTERN_INLINE int t2_is_ioaddr(unsigned long addr) 580{ 581 return (long)addr >= 0; 582} 583 584__EXTERN_INLINE int t2_is_mmio(const volatile void __iomem *addr) 585{ 586 return (unsigned long)addr >= T2_DENSE_MEM; 587} 588 589/* New-style ioread interface. The mmio routines are so ugly for T2 that 590 it doesn't make sense to merge the pio and mmio routines. */ 591 592#define IOPORT(OS, NS) \ 593__EXTERN_INLINE unsigned int t2_ioread##NS(void __iomem *xaddr) \ 594{ \ 595 if (t2_is_mmio(xaddr)) \ 596 return t2_read##OS(xaddr); \ 597 else \ 598 return t2_in##OS((unsigned long)xaddr - T2_IO); \ 599} \ 600__EXTERN_INLINE void t2_iowrite##NS(u##NS b, void __iomem *xaddr) \ 601{ \ 602 if (t2_is_mmio(xaddr)) \ 603 t2_write##OS(b, xaddr); \ 604 else \ 605 t2_out##OS(b, (unsigned long)xaddr - T2_IO); \ 606} 607 608IOPORT(b, 8) 609IOPORT(w, 16) 610IOPORT(l, 32) 611 612#undef IOPORT 613 614#undef vip 615#undef vuip 616 617#undef __IO_PREFIX 618#define __IO_PREFIX t2 619#define t2_trivial_rw_bw 0 620#define t2_trivial_rw_lq 0 621#define t2_trivial_io_bw 0 622#define t2_trivial_io_lq 0 623#define t2_trivial_iounmap 1 624#include <asm/io_trivial.h> 625 626#ifdef __IO_EXTERN_INLINE 627#undef __EXTERN_INLINE 628#undef __IO_EXTERN_INLINE 629#endif 630 631#endif /* __KERNEL__ */ 632 633#endif /* __ALPHA_T2__H__ */ 634