1/* 2 * linux/drivers/video/sstfb.c -- voodoo graphics frame buffer 3 * 4 * Copyright (c) 2000-2002 Ghozlane Toumi <gtoumi@laposte.net> 5 * 6 * Created 15 Jan 2000 by Ghozlane Toumi 7 * 8 * Contributions (and many thanks) : 9 * 10 * 03/2001 James Simmons <jsimmons@infradead.org> 11 * 04/2001 Paul Mundt <lethal@chaoticdreams.org> 12 * 05/2001 Urs Ganse <ursg@uni.de> 13 * (initial work on voodoo2 port, interlace) 14 * 09/2002 Helge Deller <deller@gmx.de> 15 * (enable driver on big-endian machines (hppa), ioctl fixes) 16 * 12/2002 Helge Deller <deller@gmx.de> 17 * (port driver to new frambuffer infrastructure) 18 * 01/2003 Helge Deller <deller@gmx.de> 19 * (initial work on fb hardware acceleration for voodoo2) 20 * 08/2006 Alan Cox <alan@redhat.com> 21 * Remove never finished and bogus 24/32bit support 22 * Clean up macro abuse 23 * Minor tidying for format. 24 * 12/2006 Helge Deller <deller@gmx.de> 25 * add /sys/class/graphics/fbX/vgapass sysfs-interface 26 * add module option "mode_option" to set initial screen mode 27 * use fbdev default videomode database 28 * remove debug functions from ioctl 29 */ 30 31/* 32 * The voodoo1 has the following memory mapped address space: 33 * 0x000000 - 0x3fffff : registers (4MB) 34 * 0x400000 - 0x7fffff : linear frame buffer (4MB) 35 * 0x800000 - 0xffffff : texture memory (8MB) 36 */ 37 38 39/* 40 * debug info 41 * SST_DEBUG : enable debugging 42 * SST_DEBUG_REG : debug registers 43 * 0 : no debug 44 * 1 : dac calls, [un]set_bits, FbiInit 45 * 2 : insane debug level (log every register read/write) 46 * SST_DEBUG_FUNC : functions 47 * 0 : no debug 48 * 1 : function call / debug ioctl 49 * 2 : variables 50 * 3 : flood . you don't want to do that. trust me. 51 * SST_DEBUG_VAR : debug display/var structs 52 * 0 : no debug 53 * 1 : dumps display, fb_var 54 * 55 * sstfb specific ioctls: 56 * toggle vga (0x46db) : toggle vga_pass_through 57 */ 58 59#undef SST_DEBUG 60 61 62/* 63 * Includes 64 */ 65 66#include <linux/string.h> 67#include <linux/kernel.h> 68#include <linux/module.h> 69#include <linux/fb.h> 70#include <linux/pci.h> 71#include <linux/delay.h> 72#include <linux/init.h> 73#include <linux/slab.h> 74#include <asm/io.h> 75#include <asm/uaccess.h> 76#include <video/sstfb.h> 77 78 79/* initialized by setup */ 80 81static int vgapass; /* enable VGA passthrough cable */ 82static int mem; /* mem size in MB, 0 = autodetect */ 83static int clipping = 1; /* use clipping (slower, safer) */ 84static int gfxclk; /* force FBI freq in Mhz . Dangerous */ 85static int slowpci; /* slow PCI settings */ 86 87/* 88 Possible default video modes: 800x600@60, 640x480@75, 1024x768@76, 640x480@60 89*/ 90#define DEFAULT_VIDEO_MODE "640x480@60" 91 92static char *mode_option __devinitdata = DEFAULT_VIDEO_MODE; 93 94enum { 95 ID_VOODOO1 = 0, 96 ID_VOODOO2 = 1, 97}; 98 99#define IS_VOODOO2(par) ((par)->type == ID_VOODOO2) 100 101static struct sst_spec voodoo_spec[] __devinitdata = { 102 { .name = "Voodoo Graphics", .default_gfx_clock = 50000, .max_gfxclk = 60 }, 103 { .name = "Voodoo2", .default_gfx_clock = 75000, .max_gfxclk = 85 }, 104}; 105 106 107/* 108 * debug functions 109 */ 110 111#if (SST_DEBUG_REG > 0) 112static void sst_dbg_print_read_reg(u32 reg, u32 val) { 113 const char *regname; 114 switch (reg) { 115 case FBIINIT0: regname = "FbiInit0"; break; 116 case FBIINIT1: regname = "FbiInit1"; break; 117 case FBIINIT2: regname = "FbiInit2"; break; 118 case FBIINIT3: regname = "FbiInit3"; break; 119 case FBIINIT4: regname = "FbiInit4"; break; 120 case FBIINIT5: regname = "FbiInit5"; break; 121 case FBIINIT6: regname = "FbiInit6"; break; 122 default: regname = NULL; break; 123 } 124 if (regname == NULL) 125 r_ddprintk("sst_read(%#x): %#x\n", reg, val); 126 else 127 r_dprintk(" sst_read(%s): %#x\n", regname, val); 128} 129 130static void sst_dbg_print_write_reg(u32 reg, u32 val) { 131 const char *regname; 132 switch (reg) { 133 case FBIINIT0: regname = "FbiInit0"; break; 134 case FBIINIT1: regname = "FbiInit1"; break; 135 case FBIINIT2: regname = "FbiInit2"; break; 136 case FBIINIT3: regname = "FbiInit3"; break; 137 case FBIINIT4: regname = "FbiInit4"; break; 138 case FBIINIT5: regname = "FbiInit5"; break; 139 case FBIINIT6: regname = "FbiInit6"; break; 140 default: regname = NULL; break; 141 } 142 if (regname == NULL) 143 r_ddprintk("sst_write(%#x, %#x)\n", reg, val); 144 else 145 r_dprintk(" sst_write(%s, %#x)\n", regname, val); 146} 147#else /* (SST_DEBUG_REG > 0) */ 148# define sst_dbg_print_read_reg(reg, val) do {} while(0) 149# define sst_dbg_print_write_reg(reg, val) do {} while(0) 150#endif /* (SST_DEBUG_REG > 0) */ 151 152/* 153 * hardware access functions 154 */ 155 156/* register access */ 157#define sst_read(reg) __sst_read(par->mmio_vbase, reg) 158#define sst_write(reg,val) __sst_write(par->mmio_vbase, reg, val) 159#define sst_set_bits(reg,val) __sst_set_bits(par->mmio_vbase, reg, val) 160#define sst_unset_bits(reg,val) __sst_unset_bits(par->mmio_vbase, reg, val) 161#define sst_dac_read(reg) __sst_dac_read(par->mmio_vbase, reg) 162#define sst_dac_write(reg,val) __sst_dac_write(par->mmio_vbase, reg, val) 163#define dac_i_read(reg) __dac_i_read(par->mmio_vbase, reg) 164#define dac_i_write(reg,val) __dac_i_write(par->mmio_vbase, reg, val) 165 166static inline u32 __sst_read(u8 __iomem *vbase, u32 reg) 167{ 168 u32 ret = readl(vbase + reg); 169 sst_dbg_print_read_reg(reg, ret); 170 return ret; 171} 172 173static inline void __sst_write(u8 __iomem *vbase, u32 reg, u32 val) 174{ 175 sst_dbg_print_write_reg(reg, val); 176 writel(val, vbase + reg); 177} 178 179static inline void __sst_set_bits(u8 __iomem *vbase, u32 reg, u32 val) 180{ 181 r_dprintk("sst_set_bits(%#x, %#x)\n", reg, val); 182 __sst_write(vbase, reg, __sst_read(vbase, reg) | val); 183} 184 185static inline void __sst_unset_bits(u8 __iomem *vbase, u32 reg, u32 val) 186{ 187 r_dprintk("sst_unset_bits(%#x, %#x)\n", reg, val); 188 __sst_write(vbase, reg, __sst_read(vbase, reg) & ~val); 189} 190 191/* 192 * wait for the fbi chip. ASK: what happens if the fbi is stuck ? 193 * 194 * the FBI is supposed to be ready if we receive 5 time 195 * in a row a "idle" answer to our requests 196 */ 197 198#define sst_wait_idle() __sst_wait_idle(par->mmio_vbase) 199 200static int __sst_wait_idle(u8 __iomem *vbase) 201{ 202 int count = 0; 203 204 /* if (doFBINOP) __sst_write(vbase, NOPCMD, 0); */ 205 206 while(1) { 207 if (__sst_read(vbase, STATUS) & STATUS_FBI_BUSY) { 208 f_dddprintk("status: busy\n"); 209 count = 0; 210 } else { 211 count++; 212 f_dddprintk("status: idle(%d)\n", count); 213 } 214 if (count >= 5) return 1; 215 } 216} 217 218 219/* dac access */ 220/* dac_read should be remaped to FbiInit2 (via the pci reg init_enable) */ 221static u8 __sst_dac_read(u8 __iomem *vbase, u8 reg) 222{ 223 u8 ret; 224 225 reg &= 0x07; 226 __sst_write(vbase, DAC_DATA, ((u32)reg << 8) | DAC_READ_CMD ); 227 __sst_wait_idle(vbase); 228 /* udelay(10); */ 229 ret = __sst_read(vbase, DAC_READ) & 0xff; 230 r_dprintk("sst_dac_read(%#x): %#x\n", reg, ret); 231 232 return ret; 233} 234 235static void __sst_dac_write(u8 __iomem *vbase, u8 reg, u8 val) 236{ 237 r_dprintk("sst_dac_write(%#x, %#x)\n", reg, val); 238 reg &= 0x07; 239 __sst_write(vbase, DAC_DATA,(((u32)reg << 8)) | (u32)val); 240 __sst_wait_idle(vbase); 241} 242 243/* indexed access to ti/att dacs */ 244static u32 __dac_i_read(u8 __iomem *vbase, u8 reg) 245{ 246 u32 ret; 247 248 __sst_dac_write(vbase, DACREG_ADDR_I, reg); 249 ret = __sst_dac_read(vbase, DACREG_DATA_I); 250 r_dprintk("sst_dac_read_i(%#x): %#x\n", reg, ret); 251 return ret; 252} 253static void __dac_i_write(u8 __iomem *vbase, u8 reg,u8 val) 254{ 255 r_dprintk("sst_dac_write_i(%#x, %#x)\n", reg, val); 256 __sst_dac_write(vbase, DACREG_ADDR_I, reg); 257 __sst_dac_write(vbase, DACREG_DATA_I, val); 258} 259 260/* compute the m,n,p , returns the real freq 261 * (ics datasheet : N <-> N1 , P <-> N2) 262 * 263 * Fout= Fref * (M+2)/( 2^P * (N+2)) 264 * we try to get close to the asked freq 265 * with P as high, and M as low as possible 266 * range: 267 * ti/att : 0 <= M <= 255; 0 <= P <= 3; 0<= N <= 63 268 * ics : 1 <= M <= 127; 0 <= P <= 3; 1<= N <= 31 269 * we'll use the lowest limitation, should be precise enouth 270 */ 271static int sst_calc_pll(const int freq, int *freq_out, struct pll_timing *t) 272{ 273 int m, m2, n, p, best_err, fout; 274 int best_n = -1; 275 int best_m = -1; 276 277 best_err = freq; 278 p = 3; 279 /* f * 2^P = vco should be less than VCOmax ~ 250 MHz for ics*/ 280 while (((1 << p) * freq > VCO_MAX) && (p >= 0)) 281 p--; 282 if (p == -1) 283 return -EINVAL; 284 for (n = 1; n < 32; n++) { 285 /* calc 2 * m so we can round it later*/ 286 m2 = (2 * freq * (1 << p) * (n + 2) ) / DAC_FREF - 4 ; 287 288 m = (m2 % 2 ) ? m2/2+1 : m2/2 ; 289 if (m >= 128) 290 break; 291 fout = (DAC_FREF * (m + 2)) / ((1 << p) * (n + 2)); 292 if ((abs(fout - freq) < best_err) && (m > 0)) { 293 best_n = n; 294 best_m = m; 295 best_err = abs(fout - freq); 296 /* we get the lowest m , allowing 0.5% error in freq*/ 297 if (200*best_err < freq) break; 298 } 299 } 300 if (best_n == -1) /* unlikely, but who knows ? */ 301 return -EINVAL; 302 t->p = p; 303 t->n = best_n; 304 t->m = best_m; 305 *freq_out = (DAC_FREF * (t->m + 2)) / ((1 << t->p) * (t->n + 2)); 306 f_ddprintk ("m: %d, n: %d, p: %d, F: %dKhz\n", 307 t->m, t->n, t->p, *freq_out); 308 return 0; 309} 310 311/* 312 * clear lfb screen 313 */ 314static void sstfb_clear_screen(struct fb_info *info) 315{ 316 /* clear screen */ 317 fb_memset(info->screen_base, 0, info->fix.smem_len); 318} 319 320 321/** 322 * sstfb_check_var - Optional function. Validates a var passed in. 323 * @var: frame buffer variable screen structure 324 * @info: frame buffer structure that represents a single frame buffer 325 * 326 * Limit to the abilities of a single chip as SLI is not supported 327 * by this driver. 328 */ 329 330static int sstfb_check_var(struct fb_var_screeninfo *var, 331 struct fb_info *info) 332{ 333 struct sstfb_par *par = info->par; 334 int hSyncOff = var->xres + var->right_margin + var->left_margin; 335 int vSyncOff = var->yres + var->lower_margin + var->upper_margin; 336 int vBackPorch = var->left_margin, yDim = var->yres; 337 int vSyncOn = var->vsync_len; 338 int tiles_in_X, real_length; 339 unsigned int freq; 340 341 if (sst_calc_pll(PICOS2KHZ(var->pixclock), &freq, &par->pll)) { 342 printk(KERN_ERR "sstfb: Pixclock at %ld KHZ out of range\n", 343 PICOS2KHZ(var->pixclock)); 344 return -EINVAL; 345 } 346 var->pixclock = KHZ2PICOS(freq); 347 348 if (var->vmode & FB_VMODE_INTERLACED) 349 vBackPorch += (vBackPorch % 2); 350 if (var->vmode & FB_VMODE_DOUBLE) { 351 vBackPorch <<= 1; 352 yDim <<=1; 353 vSyncOn <<=1; 354 vSyncOff <<=1; 355 } 356 357 switch (var->bits_per_pixel) { 358 case 0 ... 16 : 359 var->bits_per_pixel = 16; 360 break; 361 default : 362 printk(KERN_ERR "sstfb: Unsupported bpp %d\n", var->bits_per_pixel); 363 return -EINVAL; 364 } 365 366 /* validity tests */ 367 if (var->xres <= 1 || yDim <= 0 || var->hsync_len <= 1 || 368 hSyncOff <= 1 || var->left_margin <= 2 || vSyncOn <= 0 || 369 vSyncOff <= 0 || vBackPorch <= 0) { 370 return -EINVAL; 371 } 372 373 if (IS_VOODOO2(par)) { 374 /* Voodoo 2 limits */ 375 tiles_in_X = (var->xres + 63 ) / 64 * 2; 376 377 if (var->xres > POW2(11) || yDim >= POW2(11)) { 378 printk(KERN_ERR "sstfb: Unsupported resolution %dx%d\n", 379 var->xres, var->yres); 380 return -EINVAL; 381 } 382 383 if (var->hsync_len > POW2(9) || hSyncOff > POW2(11) || 384 var->left_margin - 2 >= POW2(9) || vSyncOn >= POW2(13) || 385 vSyncOff >= POW2(13) || vBackPorch >= POW2(9) || 386 tiles_in_X >= POW2(6) || tiles_in_X <= 0) { 387 printk(KERN_ERR "sstfb: Unsupported timings\n"); 388 return -EINVAL; 389 } 390 } else { 391 /* Voodoo limits */ 392 tiles_in_X = (var->xres + 63 ) / 64; 393 394 if (var->vmode) { 395 printk(KERN_ERR "sstfb: Interlace/doublescan not supported %#x\n", 396 var->vmode); 397 return -EINVAL; 398 } 399 if (var->xres > POW2(10) || var->yres >= POW2(10)) { 400 printk(KERN_ERR "sstfb: Unsupported resolution %dx%d\n", 401 var->xres, var->yres); 402 return -EINVAL; 403 } 404 if (var->hsync_len > POW2(8) || hSyncOff - 1 > POW2(10) || 405 var->left_margin - 2 >= POW2(8) || vSyncOn >= POW2(12) || 406 vSyncOff >= POW2(12) || vBackPorch >= POW2(8) || 407 tiles_in_X >= POW2(4) || tiles_in_X <= 0) { 408 printk(KERN_ERR "sstfb: Unsupported timings\n"); 409 return -EINVAL; 410 } 411 } 412 413 /* it seems that the fbi uses tiles of 64x16 pixels to "map" the mem */ 414 real_length = tiles_in_X * (IS_VOODOO2(par) ? 32 : 64 ) 415 * ((var->bits_per_pixel == 16) ? 2 : 4); 416 417 if (real_length * yDim > info->fix.smem_len) { 418 printk(KERN_ERR "sstfb: Not enough video memory\n"); 419 return -ENOMEM; 420 } 421 422 var->sync &= (FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT); 423 var->vmode &= (FB_VMODE_INTERLACED | FB_VMODE_DOUBLE); 424 var->xoffset = 0; 425 var->yoffset = 0; 426 var->height = -1; 427 var->width = -1; 428 429 /* 430 * correct the color bit fields 431 */ 432 /* var->{red|green|blue}.msb_right = 0; */ 433 434 switch (var->bits_per_pixel) { 435 case 16: /* RGB 565 LfbMode 0 */ 436 var->red.length = 5; 437 var->green.length = 6; 438 var->blue.length = 5; 439 var->transp.length = 0; 440 441 var->red.offset = 11; 442 var->green.offset = 5; 443 var->blue.offset = 0; 444 var->transp.offset = 0; 445 break; 446 default: 447 return -EINVAL; 448 } 449 return 0; 450} 451 452/** 453 * sstfb_set_par - Optional function. Alters the hardware state. 454 * @info: frame buffer structure that represents a single frame buffer 455 */ 456static int sstfb_set_par(struct fb_info *info) 457{ 458 struct sstfb_par *par = info->par; 459 u32 lfbmode, fbiinit1, fbiinit2, fbiinit3, fbiinit5, fbiinit6=0; 460 struct pci_dev *sst_dev = par->dev; 461 unsigned int freq; 462 int ntiles; 463 464 par->hSyncOff = info->var.xres + info->var.right_margin + info->var.left_margin; 465 466 par->yDim = info->var.yres; 467 par->vSyncOn = info->var.vsync_len; 468 par->vSyncOff = info->var.yres + info->var.lower_margin + info->var.upper_margin; 469 par->vBackPorch = info->var.upper_margin; 470 471 /* We need par->pll */ 472 sst_calc_pll(PICOS2KHZ(info->var.pixclock), &freq, &par->pll); 473 474 if (info->var.vmode & FB_VMODE_INTERLACED) 475 par->vBackPorch += (par->vBackPorch % 2); 476 if (info->var.vmode & FB_VMODE_DOUBLE) { 477 par->vBackPorch <<= 1; 478 par->yDim <<=1; 479 par->vSyncOn <<=1; 480 par->vSyncOff <<=1; 481 } 482 483 if (IS_VOODOO2(par)) { 484 /* voodoo2 has 32 pixel wide tiles , BUT stange things 485 happen with odd number of tiles */ 486 par->tiles_in_X = (info->var.xres + 63 ) / 64 * 2; 487 } else { 488 /* voodoo1 has 64 pixels wide tiles. */ 489 par->tiles_in_X = (info->var.xres + 63 ) / 64; 490 } 491 492 f_ddprintk("hsync_len hSyncOff vsync_len vSyncOff\n"); 493 f_ddprintk("%-7d %-8d %-7d %-8d\n", 494 info->var.hsync_len, par->hSyncOff, 495 par->vSyncOn, par->vSyncOff); 496 f_ddprintk("left_margin upper_margin xres yres Freq\n"); 497 f_ddprintk("%-10d %-10d %-4d %-4d %-8ld\n", 498 info->var.left_margin, info->var.upper_margin, 499 info->var.xres, info->var.yres, PICOS2KHZ(info->var.pixclock)); 500 501 sst_write(NOPCMD, 0); 502 sst_wait_idle(); 503 pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR); 504 sst_set_bits(FBIINIT1, VIDEO_RESET); 505 sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET); 506 sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH); 507 sst_wait_idle(); 508 509 /*sst_unset_bits (FBIINIT0, FBI_RESET); / reenable FBI ? */ 510 511 sst_write(BACKPORCH, par->vBackPorch << 16 | (info->var.left_margin - 2)); 512 sst_write(VIDEODIMENSIONS, par->yDim << 16 | (info->var.xres - 1)); 513 sst_write(HSYNC, (par->hSyncOff - 1) << 16 | (info->var.hsync_len - 1)); 514 sst_write(VSYNC, par->vSyncOff << 16 | par->vSyncOn); 515 516 fbiinit2 = sst_read(FBIINIT2); 517 fbiinit3 = sst_read(FBIINIT3); 518 519 /* everything is reset. we enable fbiinit2/3 remap : dac acces ok */ 520 pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, 521 PCI_EN_INIT_WR | PCI_REMAP_DAC ); 522 523 par->dac_sw.set_vidmod(info, info->var.bits_per_pixel); 524 525 /* set video clock */ 526 par->dac_sw.set_pll(info, &par->pll, VID_CLOCK); 527 528 /* disable fbiinit2/3 remap */ 529 pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, 530 PCI_EN_INIT_WR); 531 532 /* restore fbiinit2/3 */ 533 sst_write(FBIINIT2,fbiinit2); 534 sst_write(FBIINIT3,fbiinit3); 535 536 fbiinit1 = (sst_read(FBIINIT1) & VIDEO_MASK) 537 | EN_DATA_OE 538 | EN_BLANK_OE 539 | EN_HVSYNC_OE 540 | EN_DCLK_OE 541 /* | (15 << TILES_IN_X_SHIFT) */ 542 | SEL_INPUT_VCLK_2X 543 /* | (2 << VCLK_2X_SEL_DEL_SHIFT) 544 | (2 << VCLK_DEL_SHIFT) */; 545 546 ntiles = par->tiles_in_X; 547 if (IS_VOODOO2(par)) { 548 fbiinit1 |= ((ntiles & 0x20) >> 5) << TILES_IN_X_MSB_SHIFT 549 | ((ntiles & 0x1e) >> 1) << TILES_IN_X_SHIFT; 550/* as the only value of importance for us in fbiinit6 is tiles in X (lsb), 551 and as reading fbinit 6 will return crap (see FBIINIT6_DEFAULT) we just 552 write our value. BTW due to the dac unable to read odd number of tiles, this 553 field is always null ... */ 554 fbiinit6 = (ntiles & 0x1) << TILES_IN_X_LSB_SHIFT; 555 } 556 else 557 fbiinit1 |= ntiles << TILES_IN_X_SHIFT; 558 559 switch (info->var.bits_per_pixel) { 560 case 16: 561 fbiinit1 |= SEL_SOURCE_VCLK_2X_SEL; 562 break; 563 default: 564 return -EINVAL; 565 } 566 sst_write(FBIINIT1, fbiinit1); 567 if (IS_VOODOO2(par)) { 568 sst_write(FBIINIT6, fbiinit6); 569 fbiinit5=sst_read(FBIINIT5) & FBIINIT5_MASK ; 570 if (info->var.vmode & FB_VMODE_INTERLACED) 571 fbiinit5 |= INTERLACE; 572 if (info->var.vmode & FB_VMODE_DOUBLE) 573 fbiinit5 |= VDOUBLESCAN; 574 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) 575 fbiinit5 |= HSYNC_HIGH; 576 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) 577 fbiinit5 |= VSYNC_HIGH; 578 sst_write(FBIINIT5, fbiinit5); 579 } 580 sst_wait_idle(); 581 sst_unset_bits(FBIINIT1, VIDEO_RESET); 582 sst_unset_bits(FBIINIT0, FBI_RESET | FIFO_RESET); 583 sst_set_bits(FBIINIT2, EN_DRAM_REFRESH); 584 /* disables fbiinit writes */ 585 pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, PCI_EN_FIFO_WR); 586 587 /* set lfbmode : set mode + front buffer for reads/writes 588 + disable pipeline */ 589 switch (info->var.bits_per_pixel) { 590 case 16: 591 lfbmode = LFB_565; 592 break; 593 default: 594 return -EINVAL; 595 } 596 597#if defined(__BIG_ENDIAN) 598 /* Enable byte-swizzle functionality in hardware. 599 * With this enabled, all our read- and write-accesses to 600 * the voodoo framebuffer can be done in native format, and 601 * the hardware will automatically convert it to little-endian. 602 * - tested on HP-PARISC, Helge Deller <deller@gmx.de> */ 603 lfbmode |= ( LFB_WORD_SWIZZLE_WR | LFB_BYTE_SWIZZLE_WR | 604 LFB_WORD_SWIZZLE_RD | LFB_BYTE_SWIZZLE_RD ); 605#endif 606 607 if (clipping) { 608 sst_write(LFBMODE, lfbmode | EN_PXL_PIPELINE); 609 /* 610 * Set "clipping" dimensions. If clipping is disabled and 611 * writes to offscreen areas of the framebuffer are performed, 612 * the "behaviour is undefined" (_very_ undefined) - Urs 613 */ 614 /* btw, it requires enabling pixel pipeline in LFBMODE . 615 off screen read/writes will just wrap and read/print pixels 616 on screen. Ugly but not that dangerous */ 617 f_ddprintk("setting clipping dimensions 0..%d, 0..%d\n", 618 info->var.xres - 1, par->yDim - 1); 619 620 sst_write(CLIP_LEFT_RIGHT, info->var.xres); 621 sst_write(CLIP_LOWY_HIGHY, par->yDim); 622 sst_set_bits(FBZMODE, EN_CLIPPING | EN_RGB_WRITE); 623 } else { 624 /* no clipping : direct access, no pipeline */ 625 sst_write(LFBMODE, lfbmode); 626 } 627 return 0; 628} 629 630/** 631 * sstfb_setcolreg - Optional function. Sets a color register. 632 * @regno: hardware colormap register 633 * @red: frame buffer colormap structure 634 * @green: The green value which can be up to 16 bits wide 635 * @blue: The blue value which can be up to 16 bits wide. 636 * @transp: If supported the alpha value which can be up to 16 bits wide. 637 * @info: frame buffer info structure 638 */ 639static int sstfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 640 u_int transp, struct fb_info *info) 641{ 642 struct sstfb_par *par = info->par; 643 u32 col; 644 645 f_dddprintk("sstfb_setcolreg\n"); 646 f_dddprintk("%-2d rgbt: %#x, %#x, %#x, %#x\n", 647 regno, red, green, blue, transp); 648 if (regno > 15) 649 return 0; 650 651 red >>= (16 - info->var.red.length); 652 green >>= (16 - info->var.green.length); 653 blue >>= (16 - info->var.blue.length); 654 transp >>= (16 - info->var.transp.length); 655 col = (red << info->var.red.offset) 656 | (green << info->var.green.offset) 657 | (blue << info->var.blue.offset) 658 | (transp << info->var.transp.offset); 659 660 par->palette[regno] = col; 661 662 return 0; 663} 664 665static void sstfb_setvgapass( struct fb_info *info, int enable ) 666{ 667 struct sstfb_par *par = info->par; 668 struct pci_dev *sst_dev = par->dev; 669 u32 fbiinit0, tmp; 670 671 enable = enable ? 1:0; 672 if (par->vgapass == enable) 673 return; 674 par->vgapass = enable; 675 676 pci_read_config_dword(sst_dev, PCI_INIT_ENABLE, &tmp); 677 pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, 678 tmp | PCI_EN_INIT_WR ); 679 fbiinit0 = sst_read (FBIINIT0); 680 if (par->vgapass) { 681 sst_write(FBIINIT0, fbiinit0 & ~DIS_VGA_PASSTHROUGH); 682 printk(KERN_INFO "fb%d: Enabling VGA pass-through\n", info->node ); 683 } else { 684 sst_write(FBIINIT0, fbiinit0 | DIS_VGA_PASSTHROUGH); 685 printk(KERN_INFO "fb%d: Disabling VGA pass-through\n", info->node ); 686 } 687 pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, tmp); 688} 689 690static ssize_t store_vgapass(struct device *device, struct device_attribute *attr, 691 const char *buf, size_t count) 692{ 693 struct fb_info *info = dev_get_drvdata(device); 694 char ** last = NULL; 695 int val; 696 697 val = simple_strtoul(buf, last, 0); 698 sstfb_setvgapass(info, val); 699 700 return count; 701} 702 703static ssize_t show_vgapass(struct device *device, struct device_attribute *attr, 704 char *buf) 705{ 706 struct fb_info *info = dev_get_drvdata(device); 707 struct sstfb_par *par = info->par; 708 return snprintf(buf, PAGE_SIZE, "%d\n", par->vgapass); 709} 710 711static struct device_attribute device_attrs[] = { 712 __ATTR(vgapass, S_IRUGO|S_IWUSR, show_vgapass, store_vgapass) 713 }; 714 715static int sstfb_ioctl(struct fb_info *info, unsigned int cmd, 716 unsigned long arg) 717{ 718 struct sstfb_par *par; 719 u32 val; 720 721 switch (cmd) { 722 /* set/get VGA pass_through mode */ 723 case SSTFB_SET_VGAPASS: 724 if (copy_from_user(&val, (void __user *)arg, sizeof(val))) 725 return -EFAULT; 726 sstfb_setvgapass(info, val); 727 return 0; 728 case SSTFB_GET_VGAPASS: 729 par = info->par; 730 val = par->vgapass; 731 if (copy_to_user((void __user *)arg, &val, sizeof(val))) 732 return -EFAULT; 733 return 0; 734 } 735 736 return -EINVAL; 737} 738 739 740/* 741 * Screen-to-Screen BitBlt 2D command (for the bmove fb op.) - Voodoo2 only 742 */ 743 744 745/* 746 * FillRect 2D command (solidfill or invert (via ROP_XOR)) - Voodoo2 only 747 */ 748 749 750 751/* 752 * get lfb size 753 */ 754static int __devinit sst_get_memsize(struct fb_info *info, __u32 *memsize) 755{ 756 u8 __iomem *fbbase_virt = info->screen_base; 757 758 /* force memsize */ 759 if (mem >= 1 && mem <= 4) { 760 *memsize = (mem * 0x100000); 761 printk(KERN_INFO "supplied memsize: %#x\n", *memsize); 762 return 1; 763 } 764 765 writel(0xdeadbeef, fbbase_virt); 766 writel(0xdeadbeef, fbbase_virt+0x100000); 767 writel(0xdeadbeef, fbbase_virt+0x200000); 768 f_ddprintk("0MB: %#x, 1MB: %#x, 2MB: %#x\n", 769 readl(fbbase_virt), readl(fbbase_virt + 0x100000), 770 readl(fbbase_virt + 0x200000)); 771 772 writel(0xabcdef01, fbbase_virt); 773 774 f_ddprintk("0MB: %#x, 1MB: %#x, 2MB: %#x\n", 775 readl(fbbase_virt), readl(fbbase_virt + 0x100000), 776 readl(fbbase_virt + 0x200000)); 777 778 /* checks for 4mb lfb, then 2, then defaults to 1 */ 779 if (readl(fbbase_virt + 0x200000) == 0xdeadbeef) 780 *memsize = 0x400000; 781 else if (readl(fbbase_virt + 0x100000) == 0xdeadbeef) 782 *memsize = 0x200000; 783 else 784 *memsize = 0x100000; 785 f_ddprintk("detected memsize: %dMB\n", *memsize >> 20); 786 return 1; 787} 788 789 790/* 791 * DAC detection routines 792 */ 793 794/* fbi should be idle, and fifo emty and mem disabled */ 795/* supposed to detect AT&T ATT20C409 and Ti TVP3409 ramdacs */ 796 797static int __devinit sst_detect_att(struct fb_info *info) 798{ 799 struct sstfb_par *par = info->par; 800 int i, mir, dir; 801 802 for (i = 0; i < 3; i++) { 803 sst_dac_write(DACREG_WMA, 0); /* backdoor */ 804 sst_dac_read(DACREG_RMR); /* read 4 times RMR */ 805 sst_dac_read(DACREG_RMR); 806 sst_dac_read(DACREG_RMR); 807 sst_dac_read(DACREG_RMR); 808 /* the fifth time, CR0 is read */ 809 sst_dac_read(DACREG_RMR); 810 /* the 6th, manufacturer id register */ 811 mir = sst_dac_read(DACREG_RMR); 812 /*the 7th, device ID register */ 813 dir = sst_dac_read(DACREG_RMR); 814 f_ddprintk("mir: %#x, dir: %#x\n", mir, dir); 815 if (mir == DACREG_MIR_ATT && dir == DACREG_DIR_ATT) { 816 return 1; 817 } 818 } 819 return 0; 820} 821 822static int __devinit sst_detect_ti(struct fb_info *info) 823{ 824 struct sstfb_par *par = info->par; 825 int i, mir, dir; 826 827 for (i = 0; i<3; i++) { 828 sst_dac_write(DACREG_WMA, 0); /* backdoor */ 829 sst_dac_read(DACREG_RMR); /* read 4 times RMR */ 830 sst_dac_read(DACREG_RMR); 831 sst_dac_read(DACREG_RMR); 832 sst_dac_read(DACREG_RMR); 833 /* the fifth time, CR0 is read */ 834 sst_dac_read(DACREG_RMR); 835 /* the 6th, manufacturer id register */ 836 mir = sst_dac_read(DACREG_RMR); 837 /*the 7th, device ID register */ 838 dir = sst_dac_read(DACREG_RMR); 839 f_ddprintk("mir: %#x, dir: %#x\n", mir, dir); 840 if ((mir == DACREG_MIR_TI ) && (dir == DACREG_DIR_TI)) { 841 return 1; 842 } 843 } 844 return 0; 845} 846 847/* 848 * try to detect ICS5342 ramdac 849 * we get the 1st byte (M value) of preset f1,f7 and fB 850 * why those 3 ? mmmh... for now, i'll do it the glide way... 851 * and ask questions later. anyway, it seems that all the freq registers are 852 * realy at their default state (cf specs) so i ask again, why those 3 regs ? 853 * mmmmh.. it seems that's much more ugly than i thought. we use f0 and fA for 854 * pll programming, so in fact, we *hope* that the f1, f7 & fB won't be 855 * touched... 856 * is it realy safe ? how can i reset this ramdac ? geee... 857 */ 858static int __devinit sst_detect_ics(struct fb_info *info) 859{ 860 struct sstfb_par *par = info->par; 861 int m_clk0_1, m_clk0_7, m_clk1_b; 862 int n_clk0_1, n_clk0_7, n_clk1_b; 863 int i; 864 865 for (i = 0; i<5; i++ ) { 866 sst_dac_write(DACREG_ICS_PLLRMA, 0x1); /* f1 */ 867 m_clk0_1 = sst_dac_read(DACREG_ICS_PLLDATA); 868 n_clk0_1 = sst_dac_read(DACREG_ICS_PLLDATA); 869 sst_dac_write(DACREG_ICS_PLLRMA, 0x7); /* f7 */ 870 m_clk0_7 = sst_dac_read(DACREG_ICS_PLLDATA); 871 n_clk0_7 = sst_dac_read(DACREG_ICS_PLLDATA); 872 sst_dac_write(DACREG_ICS_PLLRMA, 0xb); /* fB */ 873 m_clk1_b= sst_dac_read(DACREG_ICS_PLLDATA); 874 n_clk1_b= sst_dac_read(DACREG_ICS_PLLDATA); 875 f_ddprintk("m_clk0_1: %#x, m_clk0_7: %#x, m_clk1_b: %#x\n", 876 m_clk0_1, m_clk0_7, m_clk1_b); 877 f_ddprintk("n_clk0_1: %#x, n_clk0_7: %#x, n_clk1_b: %#x\n", 878 n_clk0_1, n_clk0_7, n_clk1_b); 879 if (( m_clk0_1 == DACREG_ICS_PLL_CLK0_1_INI) 880 && (m_clk0_7 == DACREG_ICS_PLL_CLK0_7_INI) 881 && (m_clk1_b == DACREG_ICS_PLL_CLK1_B_INI)) { 882 return 1; 883 } 884 } 885 return 0; 886} 887 888 889/* 890 * gfx, video, pci fifo should be reset, dram refresh disabled 891 * see detect_dac 892 */ 893 894static int sst_set_pll_att_ti(struct fb_info *info, 895 const struct pll_timing *t, const int clock) 896{ 897 struct sstfb_par *par = info->par; 898 u8 cr0, cc; 899 900 /* enable indexed mode */ 901 sst_dac_write(DACREG_WMA, 0); /* backdoor */ 902 sst_dac_read(DACREG_RMR); /* 1 time: RMR */ 903 sst_dac_read(DACREG_RMR); /* 2 RMR */ 904 sst_dac_read(DACREG_RMR); /* 3 // */ 905 sst_dac_read(DACREG_RMR); /* 4 // */ 906 cr0 = sst_dac_read(DACREG_RMR); /* 5 CR0 */ 907 908 sst_dac_write(DACREG_WMA, 0); 909 sst_dac_read(DACREG_RMR); 910 sst_dac_read(DACREG_RMR); 911 sst_dac_read(DACREG_RMR); 912 sst_dac_read(DACREG_RMR); 913 sst_dac_write(DACREG_RMR, (cr0 & 0xf0) 914 | DACREG_CR0_EN_INDEXED 915 | DACREG_CR0_8BIT 916 | DACREG_CR0_PWDOWN ); 917 /* so, now we are in indexed mode . dunno if its common, but 918 i find this way of doing things a little bit weird :p */ 919 920 udelay(300); 921 cc = dac_i_read(DACREG_CC_I); 922 switch (clock) { 923 case VID_CLOCK: 924 dac_i_write(DACREG_AC0_I, t->m); 925 dac_i_write(DACREG_AC1_I, t->p << 6 | t->n); 926 dac_i_write(DACREG_CC_I, 927 (cc & 0x0f) | DACREG_CC_CLKA | DACREG_CC_CLKA_C); 928 break; 929 case GFX_CLOCK: 930 dac_i_write(DACREG_BD0_I, t->m); 931 dac_i_write(DACREG_BD1_I, t->p << 6 | t->n); 932 dac_i_write(DACREG_CC_I, 933 (cc & 0xf0) | DACREG_CC_CLKB | DACREG_CC_CLKB_D); 934 break; 935 default: 936 dprintk("%s: wrong clock code '%d'\n", 937 __FUNCTION__, clock); 938 return 0; 939 } 940 udelay(300); 941 942 /* power up the dac & return to "normal" non-indexed mode */ 943 dac_i_write(DACREG_CR0_I, 944 cr0 & ~DACREG_CR0_PWDOWN & ~DACREG_CR0_EN_INDEXED); 945 return 1; 946} 947 948static int sst_set_pll_ics(struct fb_info *info, 949 const struct pll_timing *t, const int clock) 950{ 951 struct sstfb_par *par = info->par; 952 u8 pll_ctrl; 953 954 sst_dac_write(DACREG_ICS_PLLRMA, DACREG_ICS_PLL_CTRL); 955 pll_ctrl = sst_dac_read(DACREG_ICS_PLLDATA); 956 switch(clock) { 957 case VID_CLOCK: 958 sst_dac_write(DACREG_ICS_PLLWMA, 0x0); /* CLK0, f0 */ 959 sst_dac_write(DACREG_ICS_PLLDATA, t->m); 960 sst_dac_write(DACREG_ICS_PLLDATA, t->p << 5 | t->n); 961 /* selects freq f0 for clock 0 */ 962 sst_dac_write(DACREG_ICS_PLLWMA, DACREG_ICS_PLL_CTRL); 963 sst_dac_write(DACREG_ICS_PLLDATA, 964 (pll_ctrl & 0xd8) 965 | DACREG_ICS_CLK0 966 | DACREG_ICS_CLK0_0); 967 break; 968 case GFX_CLOCK : 969 sst_dac_write(DACREG_ICS_PLLWMA, 0xa); /* CLK1, fA */ 970 sst_dac_write(DACREG_ICS_PLLDATA, t->m); 971 sst_dac_write(DACREG_ICS_PLLDATA, t->p << 5 | t->n); 972 /* selects freq fA for clock 1 */ 973 sst_dac_write(DACREG_ICS_PLLWMA, DACREG_ICS_PLL_CTRL); 974 sst_dac_write(DACREG_ICS_PLLDATA, 975 (pll_ctrl & 0xef) | DACREG_ICS_CLK1_A); 976 break; 977 default: 978 dprintk("%s: wrong clock code '%d'\n", 979 __FUNCTION__, clock); 980 return 0; 981 } 982 udelay(300); 983 return 1; 984} 985 986static void sst_set_vidmod_att_ti(struct fb_info *info, const int bpp) 987{ 988 struct sstfb_par *par = info->par; 989 u8 cr0; 990 991 sst_dac_write(DACREG_WMA, 0); /* backdoor */ 992 sst_dac_read(DACREG_RMR); /* read 4 times RMR */ 993 sst_dac_read(DACREG_RMR); 994 sst_dac_read(DACREG_RMR); 995 sst_dac_read(DACREG_RMR); 996 /* the fifth time, CR0 is read */ 997 cr0 = sst_dac_read(DACREG_RMR); 998 999 sst_dac_write(DACREG_WMA, 0); /* backdoor */ 1000 sst_dac_read(DACREG_RMR); /* read 4 times RMR */ 1001 sst_dac_read(DACREG_RMR); 1002 sst_dac_read(DACREG_RMR); 1003 sst_dac_read(DACREG_RMR); 1004 /* cr0 */ 1005 switch(bpp) { 1006 case 16: 1007 sst_dac_write(DACREG_RMR, (cr0 & 0x0f) | DACREG_CR0_16BPP); 1008 break; 1009 default: 1010 dprintk("%s: bad depth '%u'\n", __FUNCTION__, bpp); 1011 break; 1012 } 1013} 1014 1015static void sst_set_vidmod_ics(struct fb_info *info, const int bpp) 1016{ 1017 struct sstfb_par *par = info->par; 1018 1019 switch(bpp) { 1020 case 16: 1021 sst_dac_write(DACREG_ICS_CMD, DACREG_ICS_CMD_16BPP); 1022 break; 1023 default: 1024 dprintk("%s: bad depth '%u'\n", __FUNCTION__, bpp); 1025 break; 1026 } 1027} 1028 1029/* 1030 * detect dac type 1031 * prerequisite : write to FbiInitx enabled, video and fbi and pci fifo reset, 1032 * dram refresh disabled, FbiInit remaped. 1033 * TODO: mmh.. maybe i shoud put the "prerequisite" in the func ... 1034 */ 1035 1036 1037static struct dac_switch dacs[] __devinitdata = { 1038 { .name = "TI TVP3409", 1039 .detect = sst_detect_ti, 1040 .set_pll = sst_set_pll_att_ti, 1041 .set_vidmod = sst_set_vidmod_att_ti }, 1042 1043 { .name = "AT&T ATT20C409", 1044 .detect = sst_detect_att, 1045 .set_pll = sst_set_pll_att_ti, 1046 .set_vidmod = sst_set_vidmod_att_ti }, 1047 { .name = "ICS ICS5342", 1048 .detect = sst_detect_ics, 1049 .set_pll = sst_set_pll_ics, 1050 .set_vidmod = sst_set_vidmod_ics }, 1051}; 1052 1053static int __devinit sst_detect_dactype(struct fb_info *info, struct sstfb_par *par) 1054{ 1055 int i, ret = 0; 1056 1057 for (i = 0; i < ARRAY_SIZE(dacs); i++) { 1058 ret = dacs[i].detect(info); 1059 if (ret) 1060 break; 1061 } 1062 if (!ret) 1063 return 0; 1064 f_dprintk("%s found %s\n", __FUNCTION__, dacs[i].name); 1065 par->dac_sw = dacs[i]; 1066 return 1; 1067} 1068 1069/* 1070 * Internal Routines 1071 */ 1072static int __devinit sst_init(struct fb_info *info, struct sstfb_par *par) 1073{ 1074 u32 fbiinit0, fbiinit1, fbiinit4; 1075 struct pci_dev *dev = par->dev; 1076 struct pll_timing gfx_timings; 1077 struct sst_spec *spec; 1078 int Fout; 1079 int gfx_clock; 1080 1081 spec = &voodoo_spec[par->type]; 1082 f_ddprintk(" fbiinit0 fbiinit1 fbiinit2 fbiinit3 fbiinit4 " 1083 " fbiinit6\n"); 1084 f_ddprintk("%0#10x %0#10x %0#10x %0#10x %0#10x %0#10x\n", 1085 sst_read(FBIINIT0), sst_read(FBIINIT1), sst_read(FBIINIT2), 1086 sst_read(FBIINIT3), sst_read(FBIINIT4), sst_read(FBIINIT6)); 1087 /* disable video clock */ 1088 pci_write_config_dword(dev, PCI_VCLK_DISABLE, 0); 1089 1090 /* enable writing to init registers, disable pci fifo */ 1091 pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR); 1092 /* reset video */ 1093 sst_set_bits(FBIINIT1, VIDEO_RESET); 1094 sst_wait_idle(); 1095 /* reset gfx + pci fifo */ 1096 sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET); 1097 sst_wait_idle(); 1098 1099 /* unreset fifo */ 1100 /*sst_unset_bits(FBIINIT0, FIFO_RESET); 1101 sst_wait_idle();*/ 1102 /* unreset FBI */ 1103 /*sst_unset_bits(FBIINIT0, FBI_RESET); 1104 sst_wait_idle();*/ 1105 1106 /* disable dram refresh */ 1107 sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH); 1108 sst_wait_idle(); 1109 /* remap fbinit2/3 to dac */ 1110 pci_write_config_dword(dev, PCI_INIT_ENABLE, 1111 PCI_EN_INIT_WR | PCI_REMAP_DAC ); 1112 /* detect dac type */ 1113 if (!sst_detect_dactype(info, par)) { 1114 printk(KERN_ERR "sstfb: unknown dac type.\n"); 1115 return 0; 1116 } 1117 1118 /* set graphic clock */ 1119 gfx_clock = spec->default_gfx_clock; 1120 if ((gfxclk >10 ) && (gfxclk < spec->max_gfxclk)) { 1121 printk(KERN_INFO "sstfb: Using supplied graphic freq : %dMHz\n", gfxclk); 1122 gfx_clock = gfxclk *1000; 1123 } else if (gfxclk) { 1124 printk(KERN_WARNING "sstfb: %dMhz is way out of spec! Using default\n", gfxclk); 1125 } 1126 1127 sst_calc_pll(gfx_clock, &Fout, &gfx_timings); 1128 par->dac_sw.set_pll(info, &gfx_timings, GFX_CLOCK); 1129 1130 /* disable fbiinit remap */ 1131 pci_write_config_dword(dev, PCI_INIT_ENABLE, 1132 PCI_EN_INIT_WR| PCI_EN_FIFO_WR ); 1133 /* defaults init registers */ 1134 /* FbiInit0: unreset gfx, unreset fifo */ 1135 fbiinit0 = FBIINIT0_DEFAULT; 1136 fbiinit1 = FBIINIT1_DEFAULT; 1137 fbiinit4 = FBIINIT4_DEFAULT; 1138 par->vgapass = vgapass; 1139 if (par->vgapass) 1140 fbiinit0 &= ~DIS_VGA_PASSTHROUGH; 1141 else 1142 fbiinit0 |= DIS_VGA_PASSTHROUGH; 1143 if (slowpci) { 1144 fbiinit1 |= SLOW_PCI_WRITES; 1145 fbiinit4 |= SLOW_PCI_READS; 1146 } else { 1147 fbiinit1 &= ~SLOW_PCI_WRITES; 1148 fbiinit4 &= ~SLOW_PCI_READS; 1149 } 1150 sst_write(FBIINIT0, fbiinit0); 1151 sst_wait_idle(); 1152 sst_write(FBIINIT1, fbiinit1); 1153 sst_wait_idle(); 1154 sst_write(FBIINIT2, FBIINIT2_DEFAULT); 1155 sst_wait_idle(); 1156 sst_write(FBIINIT3, FBIINIT3_DEFAULT); 1157 sst_wait_idle(); 1158 sst_write(FBIINIT4, fbiinit4); 1159 sst_wait_idle(); 1160 if (IS_VOODOO2(par)) { 1161 sst_write(FBIINIT6, FBIINIT6_DEFAULT); 1162 sst_wait_idle(); 1163 } 1164 1165 pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_FIFO_WR); 1166 pci_write_config_dword(dev, PCI_VCLK_ENABLE, 0); 1167 return 1; 1168} 1169 1170static void __devexit sst_shutdown(struct fb_info *info) 1171{ 1172 struct sstfb_par *par = info->par; 1173 struct pci_dev *dev = par->dev; 1174 struct pll_timing gfx_timings; 1175 int Fout; 1176 1177 /* reset video, gfx, fifo, disable dram + remap fbiinit2/3 */ 1178 pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR); 1179 sst_set_bits(FBIINIT1, VIDEO_RESET | EN_BLANKING); 1180 sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH); 1181 sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET); 1182 sst_wait_idle(); 1183 pci_write_config_dword(dev, PCI_INIT_ENABLE, 1184 PCI_EN_INIT_WR | PCI_REMAP_DAC); 1185 /* set 20Mhz gfx clock */ 1186 sst_calc_pll(20000, &Fout, &gfx_timings); 1187 par->dac_sw.set_pll(info, &gfx_timings, GFX_CLOCK); 1188 /* TODO maybe shutdown the dac, vrefresh and so on... */ 1189 pci_write_config_dword(dev, PCI_INIT_ENABLE, 1190 PCI_EN_INIT_WR); 1191 sst_unset_bits(FBIINIT0, FBI_RESET | FIFO_RESET | DIS_VGA_PASSTHROUGH); 1192 pci_write_config_dword(dev, PCI_VCLK_DISABLE,0); 1193 /* maybe keep fbiinit* and PCI_INIT_enable in the fb_info struct 1194 * from start ? */ 1195 pci_write_config_dword(dev, PCI_INIT_ENABLE, 0); 1196 1197} 1198 1199/* 1200 * Interface to the world 1201 */ 1202static int __devinit sstfb_setup(char *options) 1203{ 1204 char *this_opt; 1205 1206 if (!options || !*options) 1207 return 0; 1208 1209 while ((this_opt = strsep(&options, ",")) != NULL) { 1210 if (!*this_opt) continue; 1211 1212 f_ddprintk("option %s\n", this_opt); 1213 1214 if (!strcmp(this_opt, "vganopass")) 1215 vgapass = 0; 1216 else if (!strcmp(this_opt, "vgapass")) 1217 vgapass = 1; 1218 else if (!strcmp(this_opt, "clipping")) 1219 clipping = 1; 1220 else if (!strcmp(this_opt, "noclipping")) 1221 clipping = 0; 1222 else if (!strcmp(this_opt, "fastpci")) 1223 slowpci = 0; 1224 else if (!strcmp(this_opt, "slowpci")) 1225 slowpci = 1; 1226 else if (!strncmp(this_opt, "mem:",4)) 1227 mem = simple_strtoul (this_opt+4, NULL, 0); 1228 else if (!strncmp(this_opt, "gfxclk:",7)) 1229 gfxclk = simple_strtoul (this_opt+7, NULL, 0); 1230 else 1231 mode_option = this_opt; 1232 } 1233 return 0; 1234} 1235 1236 1237static struct fb_ops sstfb_ops = { 1238 .owner = THIS_MODULE, 1239 .fb_check_var = sstfb_check_var, 1240 .fb_set_par = sstfb_set_par, 1241 .fb_setcolreg = sstfb_setcolreg, 1242 .fb_fillrect = cfb_fillrect, /* sstfb_fillrect */ 1243 .fb_copyarea = cfb_copyarea, /* sstfb_copyarea */ 1244 .fb_imageblit = cfb_imageblit, 1245 .fb_ioctl = sstfb_ioctl, 1246}; 1247 1248static int __devinit sstfb_probe(struct pci_dev *pdev, 1249 const struct pci_device_id *id) 1250{ 1251 struct fb_info *info; 1252 struct fb_fix_screeninfo *fix; 1253 struct sstfb_par *par; 1254 struct sst_spec *spec; 1255 int err; 1256 1257 /* Enable device in PCI config. */ 1258 if ((err=pci_enable_device(pdev))) { 1259 printk(KERN_ERR "cannot enable device\n"); 1260 return err; 1261 } 1262 1263 /* Allocate the fb and par structures. */ 1264 info = framebuffer_alloc(sizeof(struct sstfb_par), &pdev->dev); 1265 if (!info) 1266 return -ENOMEM; 1267 1268 pci_set_drvdata(pdev, info); 1269 1270 par = info->par; 1271 fix = &info->fix; 1272 1273 par->type = id->driver_data; 1274 spec = &voodoo_spec[par->type]; 1275 f_ddprintk("found device : %s\n", spec->name); 1276 1277 par->dev = pdev; 1278 pci_read_config_byte(pdev, PCI_REVISION_ID, &par->revision); 1279 1280 fix->mmio_start = pci_resource_start(pdev,0); 1281 fix->mmio_len = 0x400000; 1282 fix->smem_start = fix->mmio_start + 0x400000; 1283 1284 if (!request_mem_region(fix->mmio_start, fix->mmio_len, "sstfb MMIO")) { 1285 printk(KERN_ERR "sstfb: cannot reserve mmio memory\n"); 1286 goto fail_mmio_mem; 1287 } 1288 1289 if (!request_mem_region(fix->smem_start, 0x400000,"sstfb FB")) { 1290 printk(KERN_ERR "sstfb: cannot reserve fb memory\n"); 1291 goto fail_fb_mem; 1292 } 1293 1294 par->mmio_vbase = ioremap_nocache(fix->mmio_start, 1295 fix->mmio_len); 1296 if (!par->mmio_vbase) { 1297 printk(KERN_ERR "sstfb: cannot remap register area %#lx\n", 1298 fix->mmio_start); 1299 goto fail_mmio_remap; 1300 } 1301 info->screen_base = ioremap_nocache(fix->smem_start, 0x400000); 1302 if (!info->screen_base) { 1303 printk(KERN_ERR "sstfb: cannot remap framebuffer %#lx\n", 1304 fix->smem_start); 1305 goto fail_fb_remap; 1306 } 1307 1308 if (!sst_init(info, par)) { 1309 printk(KERN_ERR "sstfb: Init failed\n"); 1310 goto fail; 1311 } 1312 sst_get_memsize(info, &fix->smem_len); 1313 strlcpy(fix->id, spec->name, sizeof(fix->id)); 1314 1315 printk(KERN_INFO "%s (revision %d) with %s dac\n", 1316 fix->id, par->revision, par->dac_sw.name); 1317 printk(KERN_INFO "framebuffer at %#lx, mapped to 0x%p, size %dMB\n", 1318 fix->smem_start, info->screen_base, 1319 fix->smem_len >> 20); 1320 1321 f_ddprintk("regbase_virt: %#lx\n", par->mmio_vbase); 1322 f_ddprintk("membase_phys: %#lx\n", fix->smem_start); 1323 f_ddprintk("fbbase_virt: %p\n", info->screen_base); 1324 1325 info->flags = FBINFO_DEFAULT; 1326 info->fbops = &sstfb_ops; 1327 info->pseudo_palette = par->palette; 1328 1329 fix->type = FB_TYPE_PACKED_PIXELS; 1330 fix->visual = FB_VISUAL_TRUECOLOR; 1331 fix->accel = FB_ACCEL_NONE; 1332 /* 1333 * According to the specs, the linelength must be of 1024 *pixels* 1334 * and the 24bpp mode is in fact a 32 bpp mode (and both are in 1335 * fact dithered to 16bit). 1336 */ 1337 fix->line_length = 2048; /* default value, for 24 or 32bit: 4096 */ 1338 1339 fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 16); 1340 1341 if (sstfb_check_var(&info->var, info)) { 1342 printk(KERN_ERR "sstfb: invalid video mode.\n"); 1343 goto fail; 1344 } 1345 1346 if (sstfb_set_par(info)) { 1347 printk(KERN_ERR "sstfb: can't set default video mode.\n"); 1348 goto fail; 1349 } 1350 1351 fb_alloc_cmap(&info->cmap, 256, 0); 1352 1353 /* register fb */ 1354 info->device = &pdev->dev; 1355 if (register_framebuffer(info) < 0) { 1356 printk(KERN_ERR "sstfb: can't register framebuffer.\n"); 1357 goto fail; 1358 } 1359 1360 sstfb_clear_screen(info); 1361 1362 if (device_create_file(info->dev, &device_attrs[0])) 1363 printk(KERN_WARNING "sstfb: can't create sysfs entry.\n"); 1364 1365 1366 printk(KERN_INFO "fb%d: %s frame buffer device at 0x%p\n", 1367 info->node, fix->id, info->screen_base); 1368 1369 return 0; 1370 1371fail: 1372 fb_dealloc_cmap(&info->cmap); 1373 iounmap(info->screen_base); 1374fail_fb_remap: 1375 iounmap(par->mmio_vbase); 1376fail_mmio_remap: 1377 release_mem_region(fix->smem_start, 0x400000); 1378fail_fb_mem: 1379 release_mem_region(fix->mmio_start, info->fix.mmio_len); 1380fail_mmio_mem: 1381 framebuffer_release(info); 1382 return -ENXIO; /* no voodoo detected */ 1383} 1384 1385static void __devexit sstfb_remove(struct pci_dev *pdev) 1386{ 1387 struct sstfb_par *par; 1388 struct fb_info *info; 1389 1390 info = pci_get_drvdata(pdev); 1391 par = info->par; 1392 1393 device_remove_file(info->dev, &device_attrs[0]); 1394 sst_shutdown(info); 1395 iounmap(info->screen_base); 1396 iounmap(par->mmio_vbase); 1397 release_mem_region(info->fix.smem_start, 0x400000); 1398 release_mem_region(info->fix.mmio_start, info->fix.mmio_len); 1399 fb_dealloc_cmap(&info->cmap); 1400 unregister_framebuffer(info); 1401 framebuffer_release(info); 1402} 1403 1404 1405static const struct pci_device_id sstfb_id_tbl[] = { 1406 { PCI_DEVICE(PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO ), 1407 .driver_data = ID_VOODOO1, }, 1408 { PCI_DEVICE(PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO2), 1409 .driver_data = ID_VOODOO2, }, 1410 { 0 }, 1411}; 1412 1413static struct pci_driver sstfb_driver = { 1414 .name = "sstfb", 1415 .id_table = sstfb_id_tbl, 1416 .probe = sstfb_probe, 1417 .remove = __devexit_p(sstfb_remove), 1418}; 1419 1420 1421static int __devinit sstfb_init(void) 1422{ 1423 char *option = NULL; 1424 1425 if (fb_get_options("sstfb", &option)) 1426 return -ENODEV; 1427 sstfb_setup(option); 1428 1429 return pci_register_driver(&sstfb_driver); 1430} 1431 1432static void __devexit sstfb_exit(void) 1433{ 1434 pci_unregister_driver(&sstfb_driver); 1435} 1436 1437 1438module_init(sstfb_init); 1439module_exit(sstfb_exit); 1440 1441MODULE_AUTHOR("(c) 2000,2002 Ghozlane Toumi <gtoumi@laposte.net>"); 1442MODULE_DESCRIPTION("FBDev driver for 3dfx Voodoo Graphics and Voodoo2 based video boards"); 1443MODULE_LICENSE("GPL"); 1444 1445module_param(mem, int, 0); 1446MODULE_PARM_DESC(mem, "Size of frame buffer memory in MB (1, 2, 4 MB, default=autodetect)"); 1447module_param(vgapass, bool, 0); 1448MODULE_PARM_DESC(vgapass, "Enable VGA PassThrough mode (0 or 1) (default=0)"); 1449module_param(clipping, bool, 0); 1450MODULE_PARM_DESC(clipping, "Enable clipping (slower, safer) (0 or 1) (default=1)"); 1451module_param(gfxclk, int, 0); 1452MODULE_PARM_DESC(gfxclk, "Force graphic chip frequency in MHz. DANGEROUS. (default=auto)"); 1453module_param(slowpci, bool, 0); 1454MODULE_PARM_DESC(slowpci, "Uses slow PCI settings (0 or 1) (default=0)"); 1455module_param(mode_option, charp, 0); 1456MODULE_PARM_DESC(mode_option, "Initial video mode (default=" DEFAULT_VIDEO_MODE ")"); 1457